1 /*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ata.h" 31 #include <sys/param.h> 32 #include <sys/module.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/ata.h> 36 #include <sys/bus.h> 37 #include <sys/endian.h> 38 #include <sys/malloc.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/sema.h> 42 #include <sys/taskqueue.h> 43 #include <vm/uma.h> 44 #include <machine/stdarg.h> 45 #include <machine/resource.h> 46 #include <machine/bus.h> 47 #include <sys/rman.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/ata/ata-all.h> 51 #include <dev/ata/ata-pci.h> 52 #include <ata_if.h> 53 54 /* local prototypes */ 55 static int ata_via_chipinit(device_t dev); 56 static int ata_via_ch_attach(device_t dev); 57 static int ata_via_ch_detach(device_t dev); 58 static void ata_via_reset(device_t dev); 59 static int ata_via_status(device_t dev); 60 static int ata_via_old_setmode(device_t dev, int target, int mode); 61 static void ata_via_southbridge_fixup(device_t dev); 62 static int ata_via_new_setmode(device_t dev, int target, int mode); 63 static int ata_via_sata_ch_attach(device_t dev); 64 static int ata_via_sata_getrev(device_t dev, int target); 65 static int ata_via_sata_setmode(device_t dev, int target, int mode); 66 static void ata_via_sata_reset(device_t dev); 67 static int ata_via_sata_scr_read(device_t dev, int port, int reg, 68 u_int32_t *result); 69 static int ata_via_sata_scr_write(device_t dev, int port, int reg, 70 u_int32_t value); 71 static int ata_via_sata_status(device_t dev); 72 73 /* misc defines */ 74 #define VIA33 0 75 #define VIA66 1 76 #define VIA100 2 77 #define VIA133 3 78 79 #define VIACLK 0x01 80 #define VIABUG 0x02 81 #define VIABAR 0x04 82 #define VIAAHCI 0x08 83 #define VIASATA 0x10 84 85 86 /* 87 * VIA Technologies Inc. chipset support functions 88 */ 89 static int 90 ata_via_probe(device_t dev) 91 { 92 struct ata_pci_controller *ctlr = device_get_softc(dev); 93 static struct ata_chip_id ids[] = 94 {{ ATA_VIA82C586, 0x02, VIA33, 0x00, ATA_UDMA2, "82C586B" }, 95 { ATA_VIA82C586, 0x00, VIA33, 0x00, ATA_WDMA2, "82C586" }, 96 { ATA_VIA82C596, 0x12, VIA66, VIACLK, ATA_UDMA4, "82C596B" }, 97 { ATA_VIA82C596, 0x00, VIA33, 0x00, ATA_UDMA2, "82C596" }, 98 { ATA_VIA82C686, 0x40, VIA100, VIABUG, ATA_UDMA5, "82C686B"}, 99 { ATA_VIA82C686, 0x10, VIA66, VIACLK, ATA_UDMA4, "82C686A" }, 100 { ATA_VIA82C686, 0x00, VIA33, 0x00, ATA_UDMA2, "82C686" }, 101 { ATA_VIA8231, 0x00, VIA100, VIABUG, ATA_UDMA5, "8231" }, 102 { ATA_VIA8233, 0x00, VIA100, 0x00, ATA_UDMA5, "8233" }, 103 { ATA_VIA8233C, 0x00, VIA100, 0x00, ATA_UDMA5, "8233C" }, 104 { ATA_VIA8233A, 0x00, VIA133, 0x00, ATA_UDMA6, "8233A" }, 105 { ATA_VIA8235, 0x00, VIA133, 0x00, ATA_UDMA6, "8235" }, 106 { ATA_VIA8237, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" }, 107 { ATA_VIA8237A, 0x00, VIA133, 0x00, ATA_UDMA6, "8237A" }, 108 { ATA_VIA8237S, 0x00, VIA133, 0x00, ATA_UDMA6, "8237S" }, 109 { ATA_VIA8237_5372, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" }, 110 { ATA_VIA8237_7372, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" }, 111 { ATA_VIA8251, 0x00, VIA133, 0x00, ATA_UDMA6, "8251" }, 112 { ATA_VIACX700, 0x00, VIA133, VIASATA, ATA_SA150, "CX700" }, 113 { ATA_VIAVX800, 0x00, VIA133, VIASATA, ATA_SA150, "VX800" }, 114 { ATA_VIAVX855, 0x00, VIA133, 0x00, ATA_UDMA6, "VX855" }, 115 { ATA_VIAVX900, 0x00, VIA133, VIASATA, ATA_SA300, "VX900" }, 116 { 0, 0, 0, 0, 0, 0 }}; 117 static struct ata_chip_id new_ids[] = 118 {{ ATA_VIA6410, 0x00, 0, 0x00, ATA_UDMA6, "6410" }, 119 { ATA_VIA6420, 0x00, 7, 0x00, ATA_SA150, "6420" }, 120 { ATA_VIA6421, 0x00, 6, VIABAR, ATA_SA150, "6421" }, 121 { ATA_VIA8237A, 0x00, 7, 0x00, ATA_SA150, "8237A" }, 122 { ATA_VIA8237S, 0x00, 7, 0x00, ATA_SA150, "8237S" }, 123 { ATA_VIA8237_5372, 0x00, 7, 0x00, ATA_SA300, "8237" }, 124 { ATA_VIA8237_7372, 0x00, 7, 0x00, ATA_SA300, "8237" }, 125 { ATA_VIA8251, 0x00, 0, VIAAHCI, ATA_SA300, "8251" }, 126 { 0, 0, 0, 0, 0, 0 }}; 127 128 if (pci_get_vendor(dev) != ATA_VIA_ID) 129 return ENXIO; 130 131 if (pci_get_devid(dev) == ATA_VIA82C571 || 132 pci_get_devid(dev) == ATA_VIACX700IDE || 133 pci_get_devid(dev) == ATA_VIASATAIDE || 134 pci_get_devid(dev) == ATA_VIASATAIDE2 || 135 pci_get_devid(dev) == ATA_VIASATAIDE3) { 136 if (!(ctlr->chip = ata_find_chip(dev, ids, -99))) 137 return ENXIO; 138 } 139 else { 140 if (!(ctlr->chip = ata_match_chip(dev, new_ids))) 141 return ENXIO; 142 } 143 144 ata_set_desc(dev); 145 ctlr->chipinit = ata_via_chipinit; 146 return (BUS_PROBE_DEFAULT); 147 } 148 149 static int 150 ata_via_chipinit(device_t dev) 151 { 152 struct ata_pci_controller *ctlr = device_get_softc(dev); 153 154 if (ata_setup_interrupt(dev, ata_generic_intr)) 155 return ENXIO; 156 157 /* AHCI SATA */ 158 if (ctlr->chip->cfg2 & VIAAHCI) { 159 if (ata_ahci_chipinit(dev) != ENXIO) 160 return (0); 161 } 162 /* 2 SATA with "SATA registers" at PCI config space + PATA on secondary */ 163 if (ctlr->chip->cfg2 & VIASATA) { 164 ctlr->ch_attach = ata_via_sata_ch_attach; 165 ctlr->setmode = ata_via_sata_setmode; 166 ctlr->getrev = ata_via_sata_getrev; 167 ctlr->reset = ata_via_sata_reset; 168 return 0; 169 } 170 /* Legacy SATA/SATA+PATA with SATA registers in BAR(5). */ 171 if (ctlr->chip->max_dma >= ATA_SA150) { 172 ctlr->r_type2 = SYS_RES_IOPORT; 173 ctlr->r_rid2 = PCIR_BAR(5); 174 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 175 &ctlr->r_rid2, RF_ACTIVE))) { 176 ctlr->ch_attach = ata_via_ch_attach; 177 ctlr->ch_detach = ata_via_ch_detach; 178 ctlr->reset = ata_via_reset; 179 } 180 if (ctlr->chip->cfg2 & VIABAR) { 181 ctlr->channels = 3; 182 ctlr->setmode = ata_via_new_setmode; 183 } else 184 ctlr->setmode = ata_sata_setmode; 185 ctlr->getrev = ata_sata_getrev; 186 return 0; 187 } 188 189 /* prepare for ATA-66 on the 82C686a and 82C596b */ 190 if (ctlr->chip->cfg2 & VIACLK) 191 pci_write_config(dev, 0x50, 0x030b030b, 4); 192 193 /* the southbridge might need the data corruption fix */ 194 if (ctlr->chip->cfg2 & VIABUG) 195 ata_via_southbridge_fixup(dev); 196 197 /* set fifo configuration half'n'half */ 198 pci_write_config(dev, 0x43, 199 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1); 200 201 /* set status register read retry */ 202 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1); 203 204 /* set DMA read & end-of-sector fifo flush */ 205 pci_write_config(dev, 0x46, 206 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1); 207 208 /* set sector size */ 209 pci_write_config(dev, 0x60, DEV_BSIZE, 2); 210 pci_write_config(dev, 0x68, DEV_BSIZE, 2); 211 212 ctlr->setmode = ata_via_old_setmode; 213 return 0; 214 } 215 216 static int 217 ata_via_ch_attach(device_t dev) 218 { 219 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 220 struct ata_channel *ch = device_get_softc(dev); 221 222 /* newer SATA chips has resources in one BAR for each channel */ 223 if (ctlr->chip->cfg2 & VIABAR) { 224 struct resource *r_io; 225 int i, rid; 226 227 ata_pci_dmainit(dev); 228 229 rid = PCIR_BAR(ch->unit); 230 if (!(r_io = bus_alloc_resource_any(device_get_parent(dev), 231 SYS_RES_IOPORT, 232 &rid, RF_ACTIVE))) 233 return ENXIO; 234 235 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) { 236 ch->r_io[i].res = r_io; 237 ch->r_io[i].offset = i; 238 } 239 ch->r_io[ATA_CONTROL].res = r_io; 240 ch->r_io[ATA_CONTROL].offset = 2 + ATA_IOSIZE; 241 ch->r_io[ATA_IDX_ADDR].res = r_io; 242 ata_default_registers(dev); 243 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) { 244 ch->r_io[i].res = ctlr->r_res1; 245 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE); 246 } 247 ata_pci_hw(dev); 248 if (ch->unit >= 2) 249 return 0; 250 } 251 else { 252 /* setup the usual register normal pci style */ 253 if (ata_pci_ch_attach(dev)) 254 return ENXIO; 255 } 256 257 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 258 ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1); 259 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 260 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1); 261 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 262 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1); 263 ch->hw.status = ata_via_status; 264 ch->flags |= ATA_NO_SLAVE; 265 ch->flags |= ATA_SATA; 266 ch->flags |= ATA_PERIODIC_POLL; 267 268 ata_sata_scr_write(ch, -1, ATA_SERROR, 0xffffffff); 269 270 return 0; 271 } 272 273 static int 274 ata_via_ch_detach(device_t dev) 275 { 276 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 277 struct ata_channel *ch = device_get_softc(dev); 278 279 /* newer SATA chips has resources in one BAR for each channel */ 280 if (ctlr->chip->cfg2 & VIABAR) { 281 int rid; 282 283 rid = PCIR_BAR(ch->unit); 284 bus_release_resource(device_get_parent(dev), 285 SYS_RES_IOPORT, rid, ch->r_io[ATA_CONTROL].res); 286 287 ata_pci_dmafini(dev); 288 } 289 else { 290 /* setup the usual register normal pci style */ 291 if (ata_pci_ch_detach(dev)) 292 return ENXIO; 293 } 294 295 return 0; 296 } 297 298 static void 299 ata_via_reset(device_t dev) 300 { 301 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 302 struct ata_channel *ch = device_get_softc(dev); 303 304 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) 305 ata_generic_reset(dev); 306 else { 307 if (ata_sata_phy_reset(dev, -1, 1)) 308 ata_generic_reset(dev); 309 else 310 ch->devices = 0; 311 } 312 } 313 314 static int 315 ata_via_status(device_t dev) 316 { 317 318 ata_sata_phy_check_events(dev, -1); 319 return (ata_pci_status(dev)); 320 } 321 322 static int 323 ata_via_new_setmode(device_t dev, int target, int mode) 324 { 325 device_t parent = device_get_parent(dev); 326 struct ata_pci_controller *ctlr = device_get_softc(parent); 327 struct ata_channel *ch = device_get_softc(dev); 328 329 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) { 330 int piomode; 331 u_int8_t pio_timings[] = { 0xa8, 0x65, 0x65, 0x32, 0x20 }; 332 u_int8_t dma_timings[] = { 0xee, 0xe8, 0xe6, 0xe4, 0xe2, 0xe1, 0xe0 }; 333 334 /* This chip can't do WDMA. */ 335 if (mode >= ATA_WDMA0 && mode < ATA_UDMA0) 336 mode = ATA_PIO4; 337 if (mode >= ATA_UDMA0) { 338 pci_write_config(parent, 0xb3, 339 dma_timings[mode & ATA_MODE_MASK], 1); 340 piomode = ATA_PIO4; 341 } else 342 piomode = mode; 343 pci_write_config(parent, 0xab, pio_timings[ata_mode2idx(piomode)], 1); 344 } else 345 mode = ata_sata_setmode(dev, target, mode); 346 return (mode); 347 } 348 349 static int 350 ata_via_old_setmode(device_t dev, int target, int mode) 351 { 352 device_t parent = device_get_parent(dev); 353 struct ata_pci_controller *ctlr = device_get_softc(parent); 354 struct ata_channel *ch = device_get_softc(dev); 355 int devno = (ch->unit << 1) + target; 356 int reg = 0x53 - devno; 357 int piomode; 358 uint8_t timings[] = { 0xa8, 0x65, 0x42, 0x22, 0x20, 0xa8, 0x22, 0x20 }; 359 uint8_t modes[][7] = { 360 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */ 361 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */ 362 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */ 363 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 } }; /* VIA ATA133 */ 364 365 mode = min(mode, ctlr->chip->max_dma); 366 /* Set UDMA timings */ 367 if (mode >= ATA_UDMA0) { 368 pci_write_config(parent, reg, 369 modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1); 370 piomode = ATA_PIO4; 371 } else { 372 pci_write_config(parent, reg, 0x8b, 1); 373 piomode = mode; 374 } 375 /* Set WDMA/PIO timings */ 376 pci_write_config(parent, reg - 0x08,timings[ata_mode2idx(piomode)], 1); 377 return (mode); 378 } 379 380 static void 381 ata_via_southbridge_fixup(device_t dev) 382 { 383 device_t *children; 384 int nchildren, i; 385 386 if (device_get_children(device_get_parent(dev), &children, &nchildren)) 387 return; 388 389 for (i = 0; i < nchildren; i++) { 390 if (pci_get_devid(children[i]) == ATA_VIA8363 || 391 pci_get_devid(children[i]) == ATA_VIA8371 || 392 pci_get_devid(children[i]) == ATA_VIA8662 || 393 pci_get_devid(children[i]) == ATA_VIA8361) { 394 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1); 395 396 if ((reg76 & 0xf0) != 0xd0) { 397 device_printf(dev, 398 "Correcting VIA config for southbridge data corruption bug\n"); 399 pci_write_config(children[i], 0x75, 0x80, 1); 400 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1); 401 } 402 break; 403 } 404 } 405 free(children, M_TEMP); 406 } 407 408 static int 409 ata_via_sata_ch_attach(device_t dev) 410 { 411 struct ata_channel *ch = device_get_softc(dev); 412 413 if (ata_pci_ch_attach(dev)) 414 return ENXIO; 415 if (ch->unit == 0) { 416 ch->hw.status = ata_via_sata_status; 417 ch->hw.pm_read = ata_via_sata_scr_read; 418 ch->hw.pm_write = ata_via_sata_scr_write; 419 ch->flags |= ATA_PERIODIC_POLL; 420 ch->flags |= ATA_SATA; 421 ata_sata_scr_write(ch, 0, ATA_SERROR, 0xffffffff); 422 ata_sata_scr_write(ch, 1, ATA_SERROR, 0xffffffff); 423 } 424 return (0); 425 } 426 427 static int 428 ata_via_sata_getrev(device_t dev, int target) 429 { 430 device_t parent = device_get_parent(dev); 431 struct ata_channel *ch = device_get_softc(dev); 432 433 if (ch->unit == 0) { 434 if (pci_read_config(parent, 0xa0 + target, 1) & 0x10) 435 return (2); 436 else 437 return (1); 438 } 439 return (0); 440 } 441 442 static int 443 ata_via_sata_setmode(device_t dev, int target, int mode) 444 { 445 struct ata_channel *ch = device_get_softc(dev); 446 447 if (ch->unit == 0) 448 return (mode); 449 return (ata_via_old_setmode(dev, target, mode)); 450 } 451 452 static void 453 ata_via_sata_reset(device_t dev) 454 { 455 struct ata_channel *ch = device_get_softc(dev); 456 int devs; 457 458 if (ch->unit == 0) { 459 devs = ata_sata_phy_reset(dev, 0, 0); 460 DELAY(10000); 461 devs += ata_sata_phy_reset(dev, 1, 0); 462 } else 463 devs = 1; 464 if (devs) 465 ata_generic_reset(dev); 466 else 467 ch->devices = 0; 468 } 469 470 static int 471 ata_via_sata_scr_read(device_t dev, int port, int reg, u_int32_t *result) 472 { 473 struct ata_channel *ch; 474 device_t parent; 475 uint32_t val; 476 477 parent = device_get_parent(dev); 478 ch = device_get_softc(dev); 479 port = (port == 1) ? 1 : 0; 480 switch (reg) { 481 case ATA_SSTATUS: 482 val = pci_read_config(parent, 0xa0 + port, 1); 483 *result = val & 0x03; 484 if (*result != ATA_SS_DET_NO_DEVICE) { 485 if (val & 0x04) 486 *result |= ATA_SS_IPM_PARTIAL; 487 else if (val & 0x08) 488 *result |= ATA_SS_IPM_SLUMBER; 489 else 490 *result |= ATA_SS_IPM_ACTIVE; 491 if (val & 0x10) 492 *result |= ATA_SS_SPD_GEN2; 493 else 494 *result |= ATA_SS_SPD_GEN1; 495 } 496 break; 497 case ATA_SERROR: 498 *result = pci_read_config(parent, 0xa8 + port * 4, 4); 499 break; 500 case ATA_SCONTROL: 501 val = pci_read_config(parent, 0xa4 + port, 1); 502 *result = 0; 503 if (val & 0x01) 504 *result |= ATA_SC_DET_RESET; 505 if (val & 0x02) 506 *result |= ATA_SC_DET_DISABLE; 507 if (val & 0x04) 508 *result |= ATA_SC_IPM_DIS_PARTIAL; 509 if (val & 0x08) 510 *result |= ATA_SC_IPM_DIS_SLUMBER; 511 break; 512 default: 513 return (EINVAL); 514 } 515 return (0); 516 } 517 518 static int 519 ata_via_sata_scr_write(device_t dev, int port, int reg, u_int32_t value) 520 { 521 struct ata_channel *ch; 522 device_t parent; 523 uint32_t val; 524 525 parent = device_get_parent(dev); 526 ch = device_get_softc(dev); 527 port = (port == 1) ? 1 : 0; 528 switch (reg) { 529 case ATA_SERROR: 530 pci_write_config(parent, 0xa8 + port * 4, value, 4); 531 break; 532 case ATA_SCONTROL: 533 val = 0; 534 if (value & ATA_SC_DET_RESET) 535 val |= 0x01; 536 if (value & ATA_SC_DET_DISABLE) 537 val |= 0x02; 538 if (value & ATA_SC_IPM_DIS_PARTIAL) 539 val |= 0x04; 540 if (value & ATA_SC_IPM_DIS_SLUMBER) 541 val |= 0x08; 542 pci_write_config(parent, 0xa4 + port, val, 1); 543 break; 544 default: 545 return (EINVAL); 546 } 547 return (0); 548 } 549 550 static int 551 ata_via_sata_status(device_t dev) 552 { 553 554 ata_sata_phy_check_events(dev, 0); 555 ata_sata_phy_check_events(dev, 1); 556 return (ata_pci_status(dev)); 557 } 558 559 ATA_DECLARE_DRIVER(ata_via); 560 MODULE_DEPEND(ata_via, ata_ahci, 1, 1, 1); 561