1 /*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ata.h" 31 #include <sys/param.h> 32 #include <sys/module.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/ata.h> 36 #include <sys/bus.h> 37 #include <sys/endian.h> 38 #include <sys/malloc.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/sema.h> 42 #include <sys/taskqueue.h> 43 #include <vm/uma.h> 44 #include <machine/stdarg.h> 45 #include <machine/resource.h> 46 #include <machine/bus.h> 47 #include <sys/rman.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/ata/ata-all.h> 51 #include <dev/ata/ata-pci.h> 52 #include <ata_if.h> 53 54 /* local prototypes */ 55 static int ata_via_chipinit(device_t dev); 56 static int ata_via_ch_attach(device_t dev); 57 static int ata_via_ch_detach(device_t dev); 58 static void ata_via_reset(device_t dev); 59 static int ata_via_status(device_t dev); 60 static int ata_via_old_setmode(device_t dev, int target, int mode); 61 static void ata_via_southbridge_fixup(device_t dev); 62 static int ata_via_new_setmode(device_t dev, int target, int mode); 63 static int ata_via_sata_ch_attach(device_t dev); 64 static int ata_via_sata_getrev(device_t dev, int target); 65 static int ata_via_sata_setmode(device_t dev, int target, int mode); 66 67 /* misc defines */ 68 #define VIA33 0 69 #define VIA66 1 70 #define VIA100 2 71 #define VIA133 3 72 73 #define VIACLK 0x01 74 #define VIABUG 0x02 75 #define VIABAR 0x04 76 #define VIAAHCI 0x08 77 #define VIASATA 0x10 78 79 80 /* 81 * VIA Technologies Inc. chipset support functions 82 */ 83 static int 84 ata_via_probe(device_t dev) 85 { 86 struct ata_pci_controller *ctlr = device_get_softc(dev); 87 static struct ata_chip_id ids[] = 88 {{ ATA_VIA82C586, 0x02, VIA33, 0x00, ATA_UDMA2, "82C586B" }, 89 { ATA_VIA82C586, 0x00, VIA33, 0x00, ATA_WDMA2, "82C586" }, 90 { ATA_VIA82C596, 0x12, VIA66, VIACLK, ATA_UDMA4, "82C596B" }, 91 { ATA_VIA82C596, 0x00, VIA33, 0x00, ATA_UDMA2, "82C596" }, 92 { ATA_VIA82C686, 0x40, VIA100, VIABUG, ATA_UDMA5, "82C686B"}, 93 { ATA_VIA82C686, 0x10, VIA66, VIACLK, ATA_UDMA4, "82C686A" }, 94 { ATA_VIA82C686, 0x00, VIA33, 0x00, ATA_UDMA2, "82C686" }, 95 { ATA_VIA8231, 0x00, VIA100, VIABUG, ATA_UDMA5, "8231" }, 96 { ATA_VIA8233, 0x00, VIA100, 0x00, ATA_UDMA5, "8233" }, 97 { ATA_VIA8233C, 0x00, VIA100, 0x00, ATA_UDMA5, "8233C" }, 98 { ATA_VIA8233A, 0x00, VIA133, 0x00, ATA_UDMA6, "8233A" }, 99 { ATA_VIA8235, 0x00, VIA133, 0x00, ATA_UDMA6, "8235" }, 100 { ATA_VIA8237, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" }, 101 { ATA_VIA8237A, 0x00, VIA133, 0x00, ATA_UDMA6, "8237A" }, 102 { ATA_VIA8237S, 0x00, VIA133, 0x00, ATA_UDMA6, "8237S" }, 103 { ATA_VIA8237_5372, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" }, 104 { ATA_VIA8237_7372, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" }, 105 { ATA_VIA8251, 0x00, VIA133, 0x00, ATA_UDMA6, "8251" }, 106 { ATA_VIACX700, 0x00, VIA133, VIASATA, ATA_SA150, "CX700" }, 107 { ATA_VIAVX800, 0x00, VIA133, VIASATA, ATA_SA150, "VX800" }, 108 { ATA_VIAVX855, 0x00, VIA133, 0x00, ATA_UDMA6, "VX855" }, 109 { 0, 0, 0, 0, 0, 0 }}; 110 static struct ata_chip_id new_ids[] = 111 {{ ATA_VIA6410, 0x00, 0, 0x00, ATA_UDMA6, "6410" }, 112 { ATA_VIA6420, 0x00, 7, 0x00, ATA_SA150, "6420" }, 113 { ATA_VIA6421, 0x00, 6, VIABAR, ATA_SA150, "6421" }, 114 { ATA_VIA8237A, 0x00, 7, 0x00, ATA_SA150, "8237A" }, 115 { ATA_VIA8237S, 0x00, 7, 0x00, ATA_SA150, "8237S" }, 116 { ATA_VIA8237_5372, 0x00, 7, 0x00, ATA_SA300, "8237" }, 117 { ATA_VIA8237_7372, 0x00, 7, 0x00, ATA_SA300, "8237" }, 118 { ATA_VIA8251, 0x00, 0, VIAAHCI, ATA_SA300, "8251" }, 119 { 0, 0, 0, 0, 0, 0 }}; 120 121 if (pci_get_vendor(dev) != ATA_VIA_ID) 122 return ENXIO; 123 124 if (pci_get_devid(dev) == ATA_VIA82C571 || 125 pci_get_devid(dev) == ATA_VIACX700IDE || 126 pci_get_devid(dev) == ATA_VIASATAIDE) { 127 if (!(ctlr->chip = ata_find_chip(dev, ids, -99))) 128 return ENXIO; 129 } 130 else { 131 if (!(ctlr->chip = ata_match_chip(dev, new_ids))) 132 return ENXIO; 133 } 134 135 ata_set_desc(dev); 136 ctlr->chipinit = ata_via_chipinit; 137 return (BUS_PROBE_DEFAULT); 138 } 139 140 static int 141 ata_via_chipinit(device_t dev) 142 { 143 struct ata_pci_controller *ctlr = device_get_softc(dev); 144 145 if (ata_setup_interrupt(dev, ata_generic_intr)) 146 return ENXIO; 147 148 /* AHCI SATA */ 149 if (ctlr->chip->cfg2 & VIAAHCI) { 150 if (ata_ahci_chipinit(dev) != ENXIO) 151 return (0); 152 } 153 /* 2 SATA without SATA registers on first channel + 1 PATA on second */ 154 if (ctlr->chip->cfg2 & VIASATA) { 155 ctlr->ch_attach = ata_via_sata_ch_attach; 156 ctlr->setmode = ata_via_sata_setmode; 157 ctlr->getrev = ata_via_sata_getrev; 158 return 0; 159 } 160 /* Legacy SATA/SATA+PATA with SATA registers in BAR(5). */ 161 if (ctlr->chip->max_dma >= ATA_SA150) { 162 ctlr->r_type2 = SYS_RES_IOPORT; 163 ctlr->r_rid2 = PCIR_BAR(5); 164 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 165 &ctlr->r_rid2, RF_ACTIVE))) { 166 ctlr->ch_attach = ata_via_ch_attach; 167 ctlr->ch_detach = ata_via_ch_detach; 168 ctlr->reset = ata_via_reset; 169 } 170 if (ctlr->chip->cfg2 & VIABAR) { 171 ctlr->channels = 3; 172 ctlr->setmode = ata_via_new_setmode; 173 } else 174 ctlr->setmode = ata_sata_setmode; 175 ctlr->getrev = ata_sata_getrev; 176 return 0; 177 } 178 179 /* prepare for ATA-66 on the 82C686a and 82C596b */ 180 if (ctlr->chip->cfg2 & VIACLK) 181 pci_write_config(dev, 0x50, 0x030b030b, 4); 182 183 /* the southbridge might need the data corruption fix */ 184 if (ctlr->chip->cfg2 & VIABUG) 185 ata_via_southbridge_fixup(dev); 186 187 /* set fifo configuration half'n'half */ 188 pci_write_config(dev, 0x43, 189 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1); 190 191 /* set status register read retry */ 192 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1); 193 194 /* set DMA read & end-of-sector fifo flush */ 195 pci_write_config(dev, 0x46, 196 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1); 197 198 /* set sector size */ 199 pci_write_config(dev, 0x60, DEV_BSIZE, 2); 200 pci_write_config(dev, 0x68, DEV_BSIZE, 2); 201 202 ctlr->setmode = ata_via_old_setmode; 203 return 0; 204 } 205 206 static int 207 ata_via_ch_attach(device_t dev) 208 { 209 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 210 struct ata_channel *ch = device_get_softc(dev); 211 212 /* newer SATA chips has resources in one BAR for each channel */ 213 if (ctlr->chip->cfg2 & VIABAR) { 214 struct resource *r_io; 215 int i, rid; 216 217 ata_pci_dmainit(dev); 218 219 rid = PCIR_BAR(ch->unit); 220 if (!(r_io = bus_alloc_resource_any(device_get_parent(dev), 221 SYS_RES_IOPORT, 222 &rid, RF_ACTIVE))) 223 return ENXIO; 224 225 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) { 226 ch->r_io[i].res = r_io; 227 ch->r_io[i].offset = i; 228 } 229 ch->r_io[ATA_CONTROL].res = r_io; 230 ch->r_io[ATA_CONTROL].offset = 2 + ATA_IOSIZE; 231 ch->r_io[ATA_IDX_ADDR].res = r_io; 232 ata_default_registers(dev); 233 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) { 234 ch->r_io[i].res = ctlr->r_res1; 235 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE); 236 } 237 ata_pci_hw(dev); 238 if (ch->unit >= 2) 239 return 0; 240 } 241 else { 242 /* setup the usual register normal pci style */ 243 if (ata_pci_ch_attach(dev)) 244 return ENXIO; 245 } 246 247 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 248 ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1); 249 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 250 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1); 251 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 252 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1); 253 ch->hw.status = ata_via_status; 254 ch->flags |= ATA_NO_SLAVE; 255 ch->flags |= ATA_SATA; 256 ch->flags |= ATA_PERIODIC_POLL; 257 258 ata_sata_scr_write(ch, -1, ATA_SERROR, 0xffffffff); 259 260 return 0; 261 } 262 263 static int 264 ata_via_ch_detach(device_t dev) 265 { 266 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 267 struct ata_channel *ch = device_get_softc(dev); 268 269 /* newer SATA chips has resources in one BAR for each channel */ 270 if (ctlr->chip->cfg2 & VIABAR) { 271 int rid; 272 273 rid = PCIR_BAR(ch->unit); 274 bus_release_resource(device_get_parent(dev), 275 SYS_RES_IOPORT, rid, ch->r_io[ATA_CONTROL].res); 276 277 ata_pci_dmafini(dev); 278 } 279 else { 280 /* setup the usual register normal pci style */ 281 if (ata_pci_ch_detach(dev)) 282 return ENXIO; 283 } 284 285 return 0; 286 } 287 288 static void 289 ata_via_reset(device_t dev) 290 { 291 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 292 struct ata_channel *ch = device_get_softc(dev); 293 294 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) 295 ata_generic_reset(dev); 296 else { 297 if (ata_sata_phy_reset(dev, -1, 1)) 298 ata_generic_reset(dev); 299 else 300 ch->devices = 0; 301 } 302 } 303 304 static int 305 ata_via_status(device_t dev) 306 { 307 308 ata_sata_phy_check_events(dev, -1); 309 return (ata_pci_status(dev)); 310 } 311 312 static int 313 ata_via_new_setmode(device_t dev, int target, int mode) 314 { 315 device_t parent = device_get_parent(dev); 316 struct ata_pci_controller *ctlr = device_get_softc(parent); 317 struct ata_channel *ch = device_get_softc(dev); 318 319 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) { 320 int piomode; 321 u_int8_t pio_timings[] = { 0xa8, 0x65, 0x65, 0x32, 0x20 }; 322 u_int8_t dma_timings[] = { 0xee, 0xe8, 0xe6, 0xe4, 0xe2, 0xe1, 0xe0 }; 323 324 /* This chip can't do WDMA. */ 325 if (mode >= ATA_WDMA0 && mode < ATA_UDMA0) 326 mode = ATA_PIO4; 327 if (mode >= ATA_UDMA0) { 328 pci_write_config(parent, 0xb3, 329 dma_timings[mode & ATA_MODE_MASK], 1); 330 piomode = ATA_PIO4; 331 } else 332 piomode = mode; 333 pci_write_config(parent, 0xab, pio_timings[ata_mode2idx(piomode)], 1); 334 } else 335 mode = ata_sata_setmode(dev, target, mode); 336 return (mode); 337 } 338 339 static int 340 ata_via_old_setmode(device_t dev, int target, int mode) 341 { 342 device_t parent = device_get_parent(dev); 343 struct ata_pci_controller *ctlr = device_get_softc(parent); 344 struct ata_channel *ch = device_get_softc(dev); 345 int devno = (ch->unit << 1) + target; 346 int reg = 0x53 - devno; 347 int piomode; 348 uint8_t timings[] = { 0xa8, 0x65, 0x42, 0x22, 0x20, 0xa8, 0x22, 0x20 }; 349 uint8_t modes[][7] = { 350 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */ 351 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */ 352 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */ 353 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 } }; /* VIA ATA133 */ 354 355 mode = min(mode, ctlr->chip->max_dma); 356 /* Set UDMA timings */ 357 if (mode >= ATA_UDMA0) { 358 pci_write_config(parent, reg, 359 modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1); 360 piomode = ATA_PIO4; 361 } else { 362 pci_write_config(parent, reg, 0x8b, 1); 363 piomode = mode; 364 } 365 /* Set WDMA/PIO timings */ 366 pci_write_config(parent, reg - 0x08,timings[ata_mode2idx(piomode)], 1); 367 return (mode); 368 } 369 370 static void 371 ata_via_southbridge_fixup(device_t dev) 372 { 373 device_t *children; 374 int nchildren, i; 375 376 if (device_get_children(device_get_parent(dev), &children, &nchildren)) 377 return; 378 379 for (i = 0; i < nchildren; i++) { 380 if (pci_get_devid(children[i]) == ATA_VIA8363 || 381 pci_get_devid(children[i]) == ATA_VIA8371 || 382 pci_get_devid(children[i]) == ATA_VIA8662 || 383 pci_get_devid(children[i]) == ATA_VIA8361) { 384 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1); 385 386 if ((reg76 & 0xf0) != 0xd0) { 387 device_printf(dev, 388 "Correcting VIA config for southbridge data corruption bug\n"); 389 pci_write_config(children[i], 0x75, 0x80, 1); 390 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1); 391 } 392 break; 393 } 394 } 395 free(children, M_TEMP); 396 } 397 398 static int 399 ata_via_sata_ch_attach(device_t dev) 400 { 401 struct ata_channel *ch = device_get_softc(dev); 402 403 if (ata_pci_ch_attach(dev)) 404 return ENXIO; 405 if (ch->unit == 0) 406 ch->flags |= ATA_SATA; 407 return (0); 408 } 409 410 static int 411 ata_via_sata_getrev(device_t dev, int target) 412 { 413 struct ata_channel *ch = device_get_softc(dev); 414 415 if (ch->unit == 0) 416 return (1); 417 return (0); 418 } 419 420 static int 421 ata_via_sata_setmode(device_t dev, int target, int mode) 422 { 423 struct ata_channel *ch = device_get_softc(dev); 424 425 if (ch->unit == 0) 426 return (mode); 427 return (ata_via_old_setmode(dev, target, mode)); 428 } 429 430 ATA_DECLARE_DRIVER(ata_via); 431 MODULE_DEPEND(ata_via, ata_ahci, 1, 1, 1); 432