1 /*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ata.h" 31 #include <sys/param.h> 32 #include <sys/module.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/ata.h> 36 #include <sys/bus.h> 37 #include <sys/endian.h> 38 #include <sys/malloc.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/sema.h> 42 #include <sys/taskqueue.h> 43 #include <vm/uma.h> 44 #include <machine/stdarg.h> 45 #include <machine/resource.h> 46 #include <machine/bus.h> 47 #include <sys/rman.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/ata/ata-all.h> 51 #include <dev/ata/ata-pci.h> 52 #include <ata_if.h> 53 54 /* local prototypes */ 55 static int ata_via_chipinit(device_t dev); 56 static int ata_via_ch_attach(device_t dev); 57 static int ata_via_ch_detach(device_t dev); 58 static void ata_via_reset(device_t dev); 59 static int ata_via_old_setmode(device_t dev, int target, int mode); 60 static void ata_via_southbridge_fixup(device_t dev); 61 static int ata_via_new_setmode(device_t dev, int target, int mode); 62 static int ata_via_sata_ch_attach(device_t dev); 63 static int ata_via_sata_getrev(device_t dev, int target); 64 static int ata_via_sata_setmode(device_t dev, int target, int mode); 65 66 /* misc defines */ 67 #define VIA33 0 68 #define VIA66 1 69 #define VIA100 2 70 #define VIA133 3 71 72 #define VIACLK 0x01 73 #define VIABUG 0x02 74 #define VIABAR 0x04 75 #define VIAAHCI 0x08 76 #define VIASATA 0x10 77 78 79 /* 80 * VIA Technologies Inc. chipset support functions 81 */ 82 static int 83 ata_via_probe(device_t dev) 84 { 85 struct ata_pci_controller *ctlr = device_get_softc(dev); 86 static struct ata_chip_id ids[] = 87 {{ ATA_VIA82C586, 0x02, VIA33, 0x00, ATA_UDMA2, "82C586B" }, 88 { ATA_VIA82C586, 0x00, VIA33, 0x00, ATA_WDMA2, "82C586" }, 89 { ATA_VIA82C596, 0x12, VIA66, VIACLK, ATA_UDMA4, "82C596B" }, 90 { ATA_VIA82C596, 0x00, VIA33, 0x00, ATA_UDMA2, "82C596" }, 91 { ATA_VIA82C686, 0x40, VIA100, VIABUG, ATA_UDMA5, "82C686B"}, 92 { ATA_VIA82C686, 0x10, VIA66, VIACLK, ATA_UDMA4, "82C686A" }, 93 { ATA_VIA82C686, 0x00, VIA33, 0x00, ATA_UDMA2, "82C686" }, 94 { ATA_VIA8231, 0x00, VIA100, VIABUG, ATA_UDMA5, "8231" }, 95 { ATA_VIA8233, 0x00, VIA100, 0x00, ATA_UDMA5, "8233" }, 96 { ATA_VIA8233C, 0x00, VIA100, 0x00, ATA_UDMA5, "8233C" }, 97 { ATA_VIA8233A, 0x00, VIA133, 0x00, ATA_UDMA6, "8233A" }, 98 { ATA_VIA8235, 0x00, VIA133, 0x00, ATA_UDMA6, "8235" }, 99 { ATA_VIA8237, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" }, 100 { ATA_VIA8237A, 0x00, VIA133, 0x00, ATA_UDMA6, "8237A" }, 101 { ATA_VIA8237S, 0x00, VIA133, 0x00, ATA_UDMA6, "8237S" }, 102 { ATA_VIA8237_5372, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" }, 103 { ATA_VIA8237_7372, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" }, 104 { ATA_VIA8251, 0x00, VIA133, 0x00, ATA_UDMA6, "8251" }, 105 { ATA_VIACX700, 0x00, VIA133, VIASATA, ATA_SA150, "CX700" }, 106 { ATA_VIAVX800, 0x00, VIA133, VIASATA, ATA_SA150, "VX800" }, 107 { ATA_VIAVX855, 0x00, VIA133, 0x00, ATA_UDMA6, "VX855" }, 108 { 0, 0, 0, 0, 0, 0 }}; 109 static struct ata_chip_id new_ids[] = 110 {{ ATA_VIA6410, 0x00, 0, 0x00, ATA_UDMA6, "6410" }, 111 { ATA_VIA6420, 0x00, 7, 0x00, ATA_SA150, "6420" }, 112 { ATA_VIA6421, 0x00, 6, VIABAR, ATA_SA150, "6421" }, 113 { ATA_VIA8237A, 0x00, 7, 0x00, ATA_SA150, "8237A" }, 114 { ATA_VIA8237S, 0x00, 7, 0x00, ATA_SA150, "8237S" }, 115 { ATA_VIA8237_5372, 0x00, 7, 0x00, ATA_SA300, "8237" }, 116 { ATA_VIA8237_7372, 0x00, 7, 0x00, ATA_SA300, "8237" }, 117 { ATA_VIA8251, 0x00, 0, VIAAHCI, ATA_SA300, "8251" }, 118 { 0, 0, 0, 0, 0, 0 }}; 119 120 if (pci_get_vendor(dev) != ATA_VIA_ID) 121 return ENXIO; 122 123 if (pci_get_devid(dev) == ATA_VIA82C571 || 124 pci_get_devid(dev) == ATA_VIACX700IDE || 125 pci_get_devid(dev) == ATA_VIASATAIDE) { 126 if (!(ctlr->chip = ata_find_chip(dev, ids, -99))) 127 return ENXIO; 128 } 129 else { 130 if (!(ctlr->chip = ata_match_chip(dev, new_ids))) 131 return ENXIO; 132 } 133 134 ata_set_desc(dev); 135 ctlr->chipinit = ata_via_chipinit; 136 return (BUS_PROBE_DEFAULT); 137 } 138 139 static int 140 ata_via_chipinit(device_t dev) 141 { 142 struct ata_pci_controller *ctlr = device_get_softc(dev); 143 144 if (ata_setup_interrupt(dev, ata_generic_intr)) 145 return ENXIO; 146 147 /* AHCI SATA */ 148 if (ctlr->chip->cfg2 & VIAAHCI) { 149 if (ata_ahci_chipinit(dev) != ENXIO) 150 return (0); 151 } 152 /* 2 SATA without SATA registers on first channel + 1 PATA on second */ 153 if (ctlr->chip->cfg2 & VIASATA) { 154 ctlr->ch_attach = ata_via_sata_ch_attach; 155 ctlr->setmode = ata_via_sata_setmode; 156 ctlr->getrev = ata_via_sata_getrev; 157 return 0; 158 } 159 /* Legacy SATA/SATA+PATA with SATA registers in BAR(5). */ 160 if (ctlr->chip->max_dma >= ATA_SA150) { 161 ctlr->r_type2 = SYS_RES_IOPORT; 162 ctlr->r_rid2 = PCIR_BAR(5); 163 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 164 &ctlr->r_rid2, RF_ACTIVE))) { 165 ctlr->ch_attach = ata_via_ch_attach; 166 ctlr->ch_detach = ata_via_ch_detach; 167 ctlr->reset = ata_via_reset; 168 } 169 if (ctlr->chip->cfg2 & VIABAR) { 170 ctlr->channels = 3; 171 ctlr->setmode = ata_via_new_setmode; 172 } else 173 ctlr->setmode = ata_sata_setmode; 174 ctlr->getrev = ata_sata_getrev; 175 return 0; 176 } 177 178 /* prepare for ATA-66 on the 82C686a and 82C596b */ 179 if (ctlr->chip->cfg2 & VIACLK) 180 pci_write_config(dev, 0x50, 0x030b030b, 4); 181 182 /* the southbridge might need the data corruption fix */ 183 if (ctlr->chip->cfg2 & VIABUG) 184 ata_via_southbridge_fixup(dev); 185 186 /* set fifo configuration half'n'half */ 187 pci_write_config(dev, 0x43, 188 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1); 189 190 /* set status register read retry */ 191 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1); 192 193 /* set DMA read & end-of-sector fifo flush */ 194 pci_write_config(dev, 0x46, 195 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1); 196 197 /* set sector size */ 198 pci_write_config(dev, 0x60, DEV_BSIZE, 2); 199 pci_write_config(dev, 0x68, DEV_BSIZE, 2); 200 201 ctlr->setmode = ata_via_old_setmode; 202 return 0; 203 } 204 205 static int 206 ata_via_ch_attach(device_t dev) 207 { 208 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 209 struct ata_channel *ch = device_get_softc(dev); 210 211 /* newer SATA chips has resources in one BAR for each channel */ 212 if (ctlr->chip->cfg2 & VIABAR) { 213 struct resource *r_io; 214 int i, rid; 215 216 ata_pci_dmainit(dev); 217 218 rid = PCIR_BAR(ch->unit); 219 if (!(r_io = bus_alloc_resource_any(device_get_parent(dev), 220 SYS_RES_IOPORT, 221 &rid, RF_ACTIVE))) 222 return ENXIO; 223 224 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) { 225 ch->r_io[i].res = r_io; 226 ch->r_io[i].offset = i; 227 } 228 ch->r_io[ATA_CONTROL].res = r_io; 229 ch->r_io[ATA_CONTROL].offset = 2 + ATA_IOSIZE; 230 ch->r_io[ATA_IDX_ADDR].res = r_io; 231 ata_default_registers(dev); 232 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) { 233 ch->r_io[i].res = ctlr->r_res1; 234 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE); 235 } 236 ata_pci_hw(dev); 237 if (ch->unit >= 2) 238 return 0; 239 } 240 else { 241 /* setup the usual register normal pci style */ 242 if (ata_pci_ch_attach(dev)) 243 return ENXIO; 244 } 245 246 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 247 ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1); 248 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 249 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1); 250 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 251 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1); 252 ch->flags |= ATA_NO_SLAVE; 253 ch->flags |= ATA_SATA; 254 255 /* XXX SOS PHY hotplug handling missing in VIA chip ?? */ 256 /* XXX SOS unknown how to enable PHY state change interrupt */ 257 return 0; 258 } 259 260 static int 261 ata_via_ch_detach(device_t dev) 262 { 263 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 264 struct ata_channel *ch = device_get_softc(dev); 265 266 /* newer SATA chips has resources in one BAR for each channel */ 267 if (ctlr->chip->cfg2 & VIABAR) { 268 int rid; 269 270 rid = PCIR_BAR(ch->unit); 271 bus_release_resource(device_get_parent(dev), 272 SYS_RES_IOPORT, rid, ch->r_io[ATA_CONTROL].res); 273 274 ata_pci_dmafini(dev); 275 } 276 else { 277 /* setup the usual register normal pci style */ 278 if (ata_pci_ch_detach(dev)) 279 return ENXIO; 280 } 281 282 return 0; 283 } 284 285 static void 286 ata_via_reset(device_t dev) 287 { 288 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 289 struct ata_channel *ch = device_get_softc(dev); 290 291 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) 292 ata_generic_reset(dev); 293 else 294 if (ata_sata_phy_reset(dev, -1, 1)) 295 ata_generic_reset(dev); 296 } 297 298 static int 299 ata_via_new_setmode(device_t dev, int target, int mode) 300 { 301 device_t parent = device_get_parent(dev); 302 struct ata_pci_controller *ctlr = device_get_softc(parent); 303 struct ata_channel *ch = device_get_softc(dev); 304 305 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) { 306 int piomode; 307 u_int8_t pio_timings[] = { 0xa8, 0x65, 0x65, 0x32, 0x20 }; 308 u_int8_t dma_timings[] = { 0xee, 0xe8, 0xe6, 0xe4, 0xe2, 0xe1, 0xe0 }; 309 310 /* This chip can't do WDMA. */ 311 if (mode >= ATA_WDMA0 && mode < ATA_UDMA0) 312 mode = ATA_PIO4; 313 if (mode >= ATA_UDMA0) { 314 pci_write_config(parent, 0xb3, 315 dma_timings[mode & ATA_MODE_MASK], 1); 316 piomode = ATA_PIO4; 317 } else 318 piomode = mode; 319 pci_write_config(parent, 0xab, pio_timings[ata_mode2idx(piomode)], 1); 320 } else 321 mode = ata_sata_setmode(dev, target, mode); 322 return (mode); 323 } 324 325 static int 326 ata_via_old_setmode(device_t dev, int target, int mode) 327 { 328 device_t parent = device_get_parent(dev); 329 struct ata_pci_controller *ctlr = device_get_softc(parent); 330 struct ata_channel *ch = device_get_softc(dev); 331 int devno = (ch->unit << 1) + target; 332 int reg = 0x53 - devno; 333 int piomode; 334 uint8_t timings[] = { 0xa8, 0x65, 0x42, 0x22, 0x20, 0xa8, 0x22, 0x20 }; 335 uint8_t modes[][7] = { 336 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */ 337 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */ 338 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */ 339 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 } }; /* VIA ATA133 */ 340 341 mode = min(mode, ctlr->chip->max_dma); 342 /* Set UDMA timings */ 343 if (mode >= ATA_UDMA0) { 344 pci_write_config(parent, reg, 345 modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1); 346 piomode = ATA_PIO4; 347 } else { 348 pci_write_config(parent, reg, 0x8b, 1); 349 piomode = mode; 350 } 351 /* Set WDMA/PIO timings */ 352 if (ctlr->chip->cfg1 != VIA133) 353 pci_write_config(parent, reg - 0x08,timings[ata_mode2idx(piomode)], 1); 354 return (mode); 355 } 356 357 static void 358 ata_via_southbridge_fixup(device_t dev) 359 { 360 device_t *children; 361 int nchildren, i; 362 363 if (device_get_children(device_get_parent(dev), &children, &nchildren)) 364 return; 365 366 for (i = 0; i < nchildren; i++) { 367 if (pci_get_devid(children[i]) == ATA_VIA8363 || 368 pci_get_devid(children[i]) == ATA_VIA8371 || 369 pci_get_devid(children[i]) == ATA_VIA8662 || 370 pci_get_devid(children[i]) == ATA_VIA8361) { 371 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1); 372 373 if ((reg76 & 0xf0) != 0xd0) { 374 device_printf(dev, 375 "Correcting VIA config for southbridge data corruption bug\n"); 376 pci_write_config(children[i], 0x75, 0x80, 1); 377 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1); 378 } 379 break; 380 } 381 } 382 free(children, M_TEMP); 383 } 384 385 static int 386 ata_via_sata_ch_attach(device_t dev) 387 { 388 struct ata_channel *ch = device_get_softc(dev); 389 390 if (ata_pci_ch_attach(dev)) 391 return ENXIO; 392 if (ch->unit == 0) 393 ch->flags |= ATA_SATA; 394 return (0); 395 } 396 397 static int 398 ata_via_sata_getrev(device_t dev, int target) 399 { 400 struct ata_channel *ch = device_get_softc(dev); 401 402 if (ch->unit == 0) 403 return (1); 404 return (0); 405 } 406 407 static int 408 ata_via_sata_setmode(device_t dev, int target, int mode) 409 { 410 struct ata_channel *ch = device_get_softc(dev); 411 412 if (ch->unit == 0) 413 return (mode); 414 return (ata_via_old_setmode(dev, target, mode)); 415 } 416 417 ATA_DECLARE_DRIVER(ata_via); 418 MODULE_DEPEND(ata_via, ata_ahci, 1, 1, 1); 419