1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification, immediately at the beginning of the file. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/param.h> 30 #include <sys/module.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/ata.h> 34 #include <sys/bus.h> 35 #include <sys/endian.h> 36 #include <sys/malloc.h> 37 #include <sys/lock.h> 38 #include <sys/mutex.h> 39 #include <sys/sema.h> 40 #include <sys/taskqueue.h> 41 #include <vm/uma.h> 42 #include <machine/stdarg.h> 43 #include <machine/resource.h> 44 #include <machine/bus.h> 45 #include <sys/rman.h> 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcireg.h> 48 #include <dev/ata/ata-all.h> 49 #include <dev/ata/ata-pci.h> 50 #include <ata_if.h> 51 52 /* local prototypes */ 53 static int ata_via_chipinit(device_t dev); 54 static int ata_via_ch_attach(device_t dev); 55 static int ata_via_ch_detach(device_t dev); 56 static void ata_via_reset(device_t dev); 57 static int ata_via_status(device_t dev); 58 static int ata_via_old_setmode(device_t dev, int target, int mode); 59 static void ata_via_southbridge_fixup(device_t dev); 60 static int ata_via_new_setmode(device_t dev, int target, int mode); 61 static int ata_via_sata_ch_attach(device_t dev); 62 static int ata_via_sata_getrev(device_t dev, int target); 63 static int ata_via_sata_setmode(device_t dev, int target, int mode); 64 static void ata_via_sata_reset(device_t dev); 65 static int ata_via_sata_scr_read(device_t dev, int port, int reg, 66 u_int32_t *result); 67 static int ata_via_sata_scr_write(device_t dev, int port, int reg, 68 u_int32_t value); 69 static int ata_via_sata_status(device_t dev); 70 71 /* misc defines */ 72 #define VIA33 0 73 #define VIA66 1 74 #define VIA100 2 75 #define VIA133 3 76 77 #define VIACLK 0x01 78 #define VIABUG 0x02 79 #define VIABAR 0x04 80 #define VIASATA 0x10 81 82 /* 83 * VIA Technologies Inc. chipset support functions 84 */ 85 static int 86 ata_via_probe(device_t dev) 87 { 88 struct ata_pci_controller *ctlr = device_get_softc(dev); 89 static const struct ata_chip_id ids[] = 90 {{ ATA_VIA82C586, 0x02, VIA33, 0x00, ATA_UDMA2, "82C586B" }, 91 { ATA_VIA82C586, 0x00, VIA33, 0x00, ATA_WDMA2, "82C586" }, 92 { ATA_VIA82C596, 0x12, VIA66, VIACLK, ATA_UDMA4, "82C596B" }, 93 { ATA_VIA82C596, 0x00, VIA33, 0x00, ATA_UDMA2, "82C596" }, 94 { ATA_VIA82C686, 0x40, VIA100, VIABUG, ATA_UDMA5, "82C686B"}, 95 { ATA_VIA82C686, 0x10, VIA66, VIACLK, ATA_UDMA4, "82C686A" }, 96 { ATA_VIA82C686, 0x00, VIA33, 0x00, ATA_UDMA2, "82C686" }, 97 { ATA_VIA8231, 0x00, VIA100, VIABUG, ATA_UDMA5, "8231" }, 98 { ATA_VIA8233, 0x00, VIA100, 0x00, ATA_UDMA5, "8233" }, 99 { ATA_VIA8233C, 0x00, VIA100, 0x00, ATA_UDMA5, "8233C" }, 100 { ATA_VIA8233A, 0x00, VIA133, 0x00, ATA_UDMA6, "8233A" }, 101 { ATA_VIA8235, 0x00, VIA133, 0x00, ATA_UDMA6, "8235" }, 102 { ATA_VIA8237, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" }, 103 { ATA_VIA8237A, 0x00, VIA133, 0x00, ATA_UDMA6, "8237A" }, 104 { ATA_VIA8237S, 0x00, VIA133, 0x00, ATA_UDMA6, "8237S" }, 105 { ATA_VIA8237_5372, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" }, 106 { ATA_VIA8237_7372, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" }, 107 { ATA_VIA8251, 0x00, VIA133, 0x00, ATA_UDMA6, "8251" }, 108 { ATA_VIACX700, 0x00, VIA133, VIASATA, ATA_SA150, "CX700" }, 109 { ATA_VIAVX800, 0x00, VIA133, VIASATA, ATA_SA150, "VX800" }, 110 { ATA_VIAVX855, 0x00, VIA133, 0x00, ATA_UDMA6, "VX855" }, 111 { ATA_VIAVX900, 0x00, VIA133, VIASATA, ATA_SA300, "VX900" }, 112 { 0, 0, 0, 0, 0, 0 }}; 113 static const struct ata_chip_id new_ids[] = 114 {{ ATA_VIA6410, 0x00, 0, 0x00, ATA_UDMA6, "6410" }, 115 { ATA_VIA6420, 0x00, 7, 0x00, ATA_SA150, "6420" }, 116 { ATA_VIA6421, 0x00, 6, VIABAR, ATA_SA150, "6421" }, 117 { ATA_VIA8237A, 0x00, 7, 0x00, ATA_SA150, "8237A" }, 118 { ATA_VIA8237S, 0x00, 7, 0x00, ATA_SA150, "8237S" }, 119 { ATA_VIA8237_5372, 0x00, 7, 0x00, ATA_SA300, "8237" }, 120 { ATA_VIA8237_7372, 0x00, 7, 0x00, ATA_SA300, "8237" }, 121 { 0, 0, 0, 0, 0, 0 }}; 122 123 if (pci_get_vendor(dev) != ATA_VIA_ID) 124 return ENXIO; 125 126 if (pci_get_devid(dev) == ATA_VIA82C571 || 127 pci_get_devid(dev) == ATA_VIACX700IDE || 128 pci_get_devid(dev) == ATA_VIASATAIDE || 129 pci_get_devid(dev) == ATA_VIASATAIDE2 || 130 pci_get_devid(dev) == ATA_VIASATAIDE3) { 131 if (!(ctlr->chip = ata_find_chip(dev, ids, -99))) 132 return ENXIO; 133 } 134 else { 135 if (!(ctlr->chip = ata_match_chip(dev, new_ids))) 136 return ENXIO; 137 } 138 139 ata_set_desc(dev); 140 ctlr->chipinit = ata_via_chipinit; 141 return (BUS_PROBE_LOW_PRIORITY); 142 } 143 144 static int 145 ata_via_chipinit(device_t dev) 146 { 147 struct ata_pci_controller *ctlr = device_get_softc(dev); 148 149 if (ata_setup_interrupt(dev, ata_generic_intr)) 150 return ENXIO; 151 152 /* 2 SATA with "SATA registers" at PCI config space + PATA on secondary */ 153 if (ctlr->chip->cfg2 & VIASATA) { 154 ctlr->ch_attach = ata_via_sata_ch_attach; 155 ctlr->setmode = ata_via_sata_setmode; 156 ctlr->getrev = ata_via_sata_getrev; 157 ctlr->reset = ata_via_sata_reset; 158 return 0; 159 } 160 /* Legacy SATA/SATA+PATA with SATA registers in BAR(5). */ 161 if (ctlr->chip->max_dma >= ATA_SA150) { 162 ctlr->r_type2 = SYS_RES_IOPORT; 163 ctlr->r_rid2 = PCIR_BAR(5); 164 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 165 &ctlr->r_rid2, RF_ACTIVE))) { 166 ctlr->ch_attach = ata_via_ch_attach; 167 ctlr->ch_detach = ata_via_ch_detach; 168 ctlr->reset = ata_via_reset; 169 } 170 if (ctlr->chip->cfg2 & VIABAR) { 171 ctlr->channels = 3; 172 ctlr->setmode = ata_via_new_setmode; 173 } else 174 ctlr->setmode = ata_sata_setmode; 175 ctlr->getrev = ata_sata_getrev; 176 return 0; 177 } 178 179 /* prepare for ATA-66 on the 82C686a and 82C596b */ 180 if (ctlr->chip->cfg2 & VIACLK) 181 pci_write_config(dev, 0x50, 0x030b030b, 4); 182 183 /* the southbridge might need the data corruption fix */ 184 if (ctlr->chip->cfg2 & VIABUG) 185 ata_via_southbridge_fixup(dev); 186 187 /* set fifo configuration half'n'half */ 188 pci_write_config(dev, 0x43, 189 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1); 190 191 /* set status register read retry */ 192 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1); 193 194 /* set DMA read & end-of-sector fifo flush */ 195 pci_write_config(dev, 0x46, 196 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1); 197 198 /* set sector size */ 199 pci_write_config(dev, 0x60, DEV_BSIZE, 2); 200 pci_write_config(dev, 0x68, DEV_BSIZE, 2); 201 202 ctlr->setmode = ata_via_old_setmode; 203 return 0; 204 } 205 206 static int 207 ata_via_ch_attach(device_t dev) 208 { 209 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 210 struct ata_channel *ch = device_get_softc(dev); 211 212 /* newer SATA chips has resources in one BAR for each channel */ 213 if (ctlr->chip->cfg2 & VIABAR) { 214 struct resource *r_io; 215 int i, rid; 216 217 ata_pci_dmainit(dev); 218 219 rid = PCIR_BAR(ch->unit); 220 if (!(r_io = bus_alloc_resource_any(device_get_parent(dev), 221 SYS_RES_IOPORT, 222 &rid, RF_ACTIVE))) 223 return ENXIO; 224 225 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) { 226 ch->r_io[i].res = r_io; 227 ch->r_io[i].offset = i; 228 } 229 ch->r_io[ATA_CONTROL].res = r_io; 230 ch->r_io[ATA_CONTROL].offset = 2 + ATA_IOSIZE; 231 ch->r_io[ATA_IDX_ADDR].res = r_io; 232 ata_default_registers(dev); 233 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) { 234 ch->r_io[i].res = ctlr->r_res1; 235 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE); 236 } 237 ata_pci_hw(dev); 238 if (ch->unit >= 2) 239 return 0; 240 } 241 else { 242 /* setup the usual register normal pci style */ 243 if (ata_pci_ch_attach(dev)) 244 return ENXIO; 245 } 246 247 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 248 ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1); 249 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 250 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1); 251 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 252 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1); 253 ch->hw.status = ata_via_status; 254 ch->flags |= ATA_NO_SLAVE; 255 ch->flags |= ATA_SATA; 256 ch->flags |= ATA_PERIODIC_POLL; 257 258 ata_sata_scr_write(ch, -1, ATA_SERROR, 0xffffffff); 259 260 return 0; 261 } 262 263 static int 264 ata_via_ch_detach(device_t dev) 265 { 266 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 267 struct ata_channel *ch = device_get_softc(dev); 268 269 /* newer SATA chips has resources in one BAR for each channel */ 270 if (ctlr->chip->cfg2 & VIABAR) { 271 int rid; 272 273 rid = PCIR_BAR(ch->unit); 274 bus_release_resource(device_get_parent(dev), 275 SYS_RES_IOPORT, rid, ch->r_io[ATA_CONTROL].res); 276 277 ata_pci_dmafini(dev); 278 } 279 else { 280 /* setup the usual register normal pci style */ 281 if (ata_pci_ch_detach(dev)) 282 return ENXIO; 283 } 284 285 return 0; 286 } 287 288 static void 289 ata_via_reset(device_t dev) 290 { 291 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 292 struct ata_channel *ch = device_get_softc(dev); 293 294 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) 295 ata_generic_reset(dev); 296 else { 297 if (ata_sata_phy_reset(dev, -1, 1)) 298 ata_generic_reset(dev); 299 else 300 ch->devices = 0; 301 } 302 } 303 304 static int 305 ata_via_status(device_t dev) 306 { 307 308 ata_sata_phy_check_events(dev, -1); 309 return (ata_pci_status(dev)); 310 } 311 312 static int 313 ata_via_new_setmode(device_t dev, int target, int mode) 314 { 315 device_t parent = device_get_parent(dev); 316 struct ata_pci_controller *ctlr = device_get_softc(parent); 317 struct ata_channel *ch = device_get_softc(dev); 318 319 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) { 320 int piomode; 321 static const uint8_t pio_timings[] = 322 { 0xa8, 0x65, 0x65, 0x32, 0x20 }; 323 static const uint8_t dma_timings[] = 324 { 0xee, 0xe8, 0xe6, 0xe4, 0xe2, 0xe1, 0xe0 }; 325 326 /* This chip can't do WDMA. */ 327 if (mode >= ATA_WDMA0 && mode < ATA_UDMA0) 328 mode = ATA_PIO4; 329 if (mode >= ATA_UDMA0) { 330 pci_write_config(parent, 0xb3, 331 dma_timings[mode & ATA_MODE_MASK], 1); 332 piomode = ATA_PIO4; 333 } else 334 piomode = mode; 335 pci_write_config(parent, 0xab, pio_timings[ata_mode2idx(piomode)], 1); 336 } else 337 mode = ata_sata_setmode(dev, target, mode); 338 return (mode); 339 } 340 341 static int 342 ata_via_old_setmode(device_t dev, int target, int mode) 343 { 344 device_t parent = device_get_parent(dev); 345 struct ata_pci_controller *ctlr = device_get_softc(parent); 346 struct ata_channel *ch = device_get_softc(dev); 347 int devno = (ch->unit << 1) + target; 348 int reg = 0x53 - devno; 349 int piomode; 350 static const uint8_t timings[] = 351 { 0xa8, 0x65, 0x42, 0x22, 0x20, 0xa8, 0x22, 0x20 }; 352 static const uint8_t modes[][7] = { 353 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */ 354 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */ 355 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */ 356 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 } }; /* VIA ATA133 */ 357 358 mode = min(mode, ctlr->chip->max_dma); 359 /* Set UDMA timings */ 360 if (mode >= ATA_UDMA0) { 361 pci_write_config(parent, reg, 362 modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1); 363 piomode = ATA_PIO4; 364 } else { 365 pci_write_config(parent, reg, 0x8b, 1); 366 piomode = mode; 367 } 368 /* Set WDMA/PIO timings */ 369 pci_write_config(parent, reg - 0x08,timings[ata_mode2idx(piomode)], 1); 370 return (mode); 371 } 372 373 static void 374 ata_via_southbridge_fixup(device_t dev) 375 { 376 device_t *children; 377 int nchildren, i; 378 379 if (device_get_children(device_get_parent(dev), &children, &nchildren)) 380 return; 381 382 for (i = 0; i < nchildren; i++) { 383 if (pci_get_devid(children[i]) == ATA_VIA8363 || 384 pci_get_devid(children[i]) == ATA_VIA8371 || 385 pci_get_devid(children[i]) == ATA_VIA8662 || 386 pci_get_devid(children[i]) == ATA_VIA8361) { 387 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1); 388 389 if ((reg76 & 0xf0) != 0xd0) { 390 device_printf(dev, 391 "Correcting VIA config for southbridge data corruption bug\n"); 392 pci_write_config(children[i], 0x75, 0x80, 1); 393 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1); 394 } 395 break; 396 } 397 } 398 free(children, M_TEMP); 399 } 400 401 static int 402 ata_via_sata_ch_attach(device_t dev) 403 { 404 struct ata_channel *ch = device_get_softc(dev); 405 406 if (ata_pci_ch_attach(dev)) 407 return ENXIO; 408 if (ch->unit == 0) { 409 ch->hw.status = ata_via_sata_status; 410 ch->hw.pm_read = ata_via_sata_scr_read; 411 ch->hw.pm_write = ata_via_sata_scr_write; 412 ch->flags |= ATA_PERIODIC_POLL; 413 ch->flags |= ATA_SATA; 414 ata_sata_scr_write(ch, 0, ATA_SERROR, 0xffffffff); 415 ata_sata_scr_write(ch, 1, ATA_SERROR, 0xffffffff); 416 } 417 return (0); 418 } 419 420 static int 421 ata_via_sata_getrev(device_t dev, int target) 422 { 423 device_t parent = device_get_parent(dev); 424 struct ata_channel *ch = device_get_softc(dev); 425 426 if (ch->unit == 0) { 427 if (pci_read_config(parent, 0xa0 + target, 1) & 0x10) 428 return (2); 429 else 430 return (1); 431 } 432 return (0); 433 } 434 435 static int 436 ata_via_sata_setmode(device_t dev, int target, int mode) 437 { 438 struct ata_channel *ch = device_get_softc(dev); 439 440 if (ch->unit == 0) 441 return (mode); 442 return (ata_via_old_setmode(dev, target, mode)); 443 } 444 445 static void 446 ata_via_sata_reset(device_t dev) 447 { 448 struct ata_channel *ch = device_get_softc(dev); 449 int devs, count; 450 uint8_t status; 451 452 if (ch->unit == 0) { 453 devs = ata_sata_phy_reset(dev, 0, 0); 454 count = 0; 455 do { 456 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | 457 ATA_DEV(ATA_MASTER)); 458 DELAY(1000); 459 status = ATA_IDX_INB(ch, ATA_STATUS); 460 count++; 461 } while (status & ATA_S_BUSY && count < 100); 462 463 devs += ata_sata_phy_reset(dev, 1, 0); 464 count = 0; 465 do { 466 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | 467 ATA_DEV(ATA_SLAVE)); 468 DELAY(1000); 469 status = ATA_IDX_INB(ch, ATA_STATUS); 470 count++; 471 } while (status & ATA_S_BUSY && count < 100); 472 } else 473 devs = 1; 474 if (devs) 475 ata_generic_reset(dev); 476 else 477 ch->devices = 0; 478 } 479 480 static int 481 ata_via_sata_scr_read(device_t dev, int port, int reg, u_int32_t *result) 482 { 483 device_t parent; 484 uint32_t val; 485 486 parent = device_get_parent(dev); 487 port = (port == 1) ? 1 : 0; 488 switch (reg) { 489 case ATA_SSTATUS: 490 val = pci_read_config(parent, 0xa0 + port, 1); 491 *result = val & 0x03; 492 if (*result != ATA_SS_DET_NO_DEVICE) { 493 if (val & 0x04) 494 *result |= ATA_SS_IPM_PARTIAL; 495 else if (val & 0x08) 496 *result |= ATA_SS_IPM_SLUMBER; 497 else 498 *result |= ATA_SS_IPM_ACTIVE; 499 if (val & 0x10) 500 *result |= ATA_SS_SPD_GEN2; 501 else 502 *result |= ATA_SS_SPD_GEN1; 503 } 504 break; 505 case ATA_SERROR: 506 *result = pci_read_config(parent, 0xa8 + port * 4, 4); 507 break; 508 case ATA_SCONTROL: 509 val = pci_read_config(parent, 0xa4 + port, 1); 510 *result = 0; 511 if (val & 0x01) 512 *result |= ATA_SC_DET_RESET; 513 if (val & 0x02) 514 *result |= ATA_SC_DET_DISABLE; 515 if (val & 0x04) 516 *result |= ATA_SC_IPM_DIS_PARTIAL; 517 if (val & 0x08) 518 *result |= ATA_SC_IPM_DIS_SLUMBER; 519 break; 520 default: 521 return (EINVAL); 522 } 523 return (0); 524 } 525 526 static int 527 ata_via_sata_scr_write(device_t dev, int port, int reg, u_int32_t value) 528 { 529 device_t parent; 530 uint32_t val; 531 532 parent = device_get_parent(dev); 533 port = (port == 1) ? 1 : 0; 534 switch (reg) { 535 case ATA_SERROR: 536 pci_write_config(parent, 0xa8 + port * 4, value, 4); 537 break; 538 case ATA_SCONTROL: 539 val = 0; 540 if (value & ATA_SC_DET_RESET) 541 val |= 0x01; 542 if (value & ATA_SC_DET_DISABLE) 543 val |= 0x02; 544 if (value & ATA_SC_IPM_DIS_PARTIAL) 545 val |= 0x04; 546 if (value & ATA_SC_IPM_DIS_SLUMBER) 547 val |= 0x08; 548 pci_write_config(parent, 0xa4 + port, val, 1); 549 break; 550 default: 551 return (EINVAL); 552 } 553 return (0); 554 } 555 556 static int 557 ata_via_sata_status(device_t dev) 558 { 559 560 ata_sata_phy_check_events(dev, 0); 561 ata_sata_phy_check_events(dev, 1); 562 return (ata_pci_status(dev)); 563 } 564 565 ATA_DECLARE_DRIVER(ata_via); 566