xref: /freebsd/sys/dev/ata/chipsets/ata-sis.c (revision 8655c70597b0e0918c82114b1186df5669b83eb6)
1 /*-
2  * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer,
10  *    without modification, immediately at the beginning of the file.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25  */
26 
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29 
30 #include "opt_ata.h"
31 #include <sys/param.h>
32 #include <sys/module.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
35 #include <sys/ata.h>
36 #include <sys/bus.h>
37 #include <sys/endian.h>
38 #include <sys/malloc.h>
39 #include <sys/lock.h>
40 #include <sys/mutex.h>
41 #include <sys/sema.h>
42 #include <sys/taskqueue.h>
43 #include <vm/uma.h>
44 #include <machine/stdarg.h>
45 #include <machine/resource.h>
46 #include <machine/bus.h>
47 #include <sys/rman.h>
48 #include <dev/pci/pcivar.h>
49 #include <dev/pci/pcireg.h>
50 #include <dev/ata/ata-all.h>
51 #include <dev/ata/ata-pci.h>
52 #include <ata_if.h>
53 
54 /* local prototypes */
55 static int ata_sis_chipinit(device_t dev);
56 static int ata_sis_ch_attach(device_t dev);
57 static void ata_sis_reset(device_t dev);
58 static void ata_sis_setmode(device_t dev, int mode);
59 
60 /* misc defines */
61 #define SIS_33		1
62 #define SIS_66		2
63 #define SIS_100NEW	3
64 #define SIS_100OLD	4
65 #define SIS_133NEW	5
66 #define SIS_133OLD	6
67 #define SIS_SATA	7
68 
69 
70 /*
71  * Silicon Integrated Systems Corp. (SiS) chipset support functions
72  */
73 static int
74 ata_sis_probe(device_t dev)
75 {
76     struct ata_pci_controller *ctlr = device_get_softc(dev);
77     struct ata_chip_id *idx;
78     static struct ata_chip_id ids[] =
79     {{ ATA_SIS182,  0x00, SIS_SATA,   0, ATA_SA150, "182" }, /* south */
80      { ATA_SIS181,  0x00, SIS_SATA,   0, ATA_SA150, "181" }, /* south */
81      { ATA_SIS180,  0x00, SIS_SATA,   0, ATA_SA150, "180" }, /* south */
82      { ATA_SIS965,  0x00, SIS_133NEW, 0, ATA_UDMA6, "965" }, /* south */
83      { ATA_SIS964,  0x00, SIS_133NEW, 0, ATA_UDMA6, "964" }, /* south */
84      { ATA_SIS963,  0x00, SIS_133NEW, 0, ATA_UDMA6, "963" }, /* south */
85      { ATA_SIS962,  0x00, SIS_133NEW, 0, ATA_UDMA6, "962" }, /* south */
86 
87      { ATA_SIS745,  0x00, SIS_100NEW, 0, ATA_UDMA5, "745" }, /* 1chip */
88      { ATA_SIS735,  0x00, SIS_100NEW, 0, ATA_UDMA5, "735" }, /* 1chip */
89      { ATA_SIS733,  0x00, SIS_100NEW, 0, ATA_UDMA5, "733" }, /* 1chip */
90      { ATA_SIS730,  0x00, SIS_100OLD, 0, ATA_UDMA5, "730" }, /* 1chip */
91 
92      { ATA_SIS635,  0x00, SIS_100NEW, 0, ATA_UDMA5, "635" }, /* 1chip */
93      { ATA_SIS633,  0x00, SIS_100NEW, 0, ATA_UDMA5, "633" }, /* unknown */
94      { ATA_SIS630,  0x30, SIS_100OLD, 0, ATA_UDMA5, "630S"}, /* 1chip */
95      { ATA_SIS630,  0x00, SIS_66,     0, ATA_UDMA4, "630" }, /* 1chip */
96      { ATA_SIS620,  0x00, SIS_66,     0, ATA_UDMA4, "620" }, /* 1chip */
97 
98      { ATA_SIS550,  0x00, SIS_66,     0, ATA_UDMA5, "550" },
99      { ATA_SIS540,  0x00, SIS_66,     0, ATA_UDMA4, "540" },
100      { ATA_SIS530,  0x00, SIS_66,     0, ATA_UDMA4, "530" },
101 
102      { ATA_SIS5513, 0xc2, SIS_33,     1, ATA_UDMA2, "5513" },
103      { ATA_SIS5513, 0x00, SIS_33,     1, ATA_WDMA2, "5513" },
104      { 0, 0, 0, 0, 0, 0 }};
105     char buffer[64];
106     int found = 0;
107 
108     if (pci_get_class(dev) != PCIC_STORAGE)
109 	return (ENXIO);
110 
111     if (pci_get_vendor(dev) != ATA_SIS_ID)
112 	return ENXIO;
113 
114     if (!(idx = ata_find_chip(dev, ids, -pci_get_slot(dev))))
115 	return ENXIO;
116 
117     if (idx->cfg2 && !found) {
118 	u_int8_t reg57 = pci_read_config(dev, 0x57, 1);
119 
120 	pci_write_config(dev, 0x57, (reg57 & 0x7f), 1);
121 	if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5518) {
122 	    found = 1;
123 	    idx->cfg1 = SIS_133NEW;
124 	    idx->max_dma = ATA_UDMA6;
125 	    sprintf(buffer, "SiS 962/963 %s controller",
126 		    ata_mode2str(idx->max_dma));
127 	}
128 	pci_write_config(dev, 0x57, reg57, 1);
129     }
130     if (idx->cfg2 && !found) {
131 	u_int8_t reg4a = pci_read_config(dev, 0x4a, 1);
132 
133 	pci_write_config(dev, 0x4a, (reg4a | 0x10), 1);
134 	if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5517) {
135 	    struct ata_chip_id id[] =
136 		{{ ATA_SISSOUTH, 0x10, 0, 0, 0, "" }, { 0, 0, 0, 0, 0, 0 }};
137 
138 	    found = 1;
139 	    if (ata_find_chip(dev, id, pci_get_slot(dev))) {
140 		idx->cfg1 = SIS_133OLD;
141 		idx->max_dma = ATA_UDMA6;
142 	    }
143 	    else {
144 		idx->cfg1 = SIS_100NEW;
145 		idx->max_dma = ATA_UDMA5;
146 	    }
147 	    sprintf(buffer, "SiS 961 %s controller",ata_mode2str(idx->max_dma));
148 	}
149 	pci_write_config(dev, 0x4a, reg4a, 1);
150     }
151     if (!found)
152 	sprintf(buffer,"SiS %s %s controller",
153 		idx->text, ata_mode2str(idx->max_dma));
154 
155     device_set_desc_copy(dev, buffer);
156     ctlr->chip = idx;
157     ctlr->chipinit = ata_sis_chipinit;
158     return 0;
159 }
160 
161 static int
162 ata_sis_chipinit(device_t dev)
163 {
164     struct ata_pci_controller *ctlr = device_get_softc(dev);
165 
166     if (ata_setup_interrupt(dev, ata_generic_intr))
167 	return ENXIO;
168 
169     switch (ctlr->chip->cfg1) {
170     case SIS_33:
171 	break;
172     case SIS_66:
173     case SIS_100OLD:
174 	pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 1) & ~0x04, 1);
175 	break;
176     case SIS_100NEW:
177     case SIS_133OLD:
178 	pci_write_config(dev, 0x49, pci_read_config(dev, 0x49, 1) & ~0x01, 1);
179 	break;
180     case SIS_133NEW:
181 	pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 2) | 0x0008, 2);
182 	pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 2) | 0x0008, 2);
183 	break;
184     case SIS_SATA:
185 	ctlr->r_type2 = SYS_RES_IOPORT;
186 	ctlr->r_rid2 = PCIR_BAR(5);
187 	if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
188 						   &ctlr->r_rid2, RF_ACTIVE))) {
189 	    ctlr->ch_attach = ata_sis_ch_attach;
190 	    ctlr->ch_detach = ata_pci_ch_detach;
191 	    ctlr->reset = ata_sis_reset;
192 	}
193 	ctlr->setmode = ata_sata_setmode;
194 	return 0;
195     default:
196 	return ENXIO;
197     }
198     ctlr->setmode = ata_sis_setmode;
199     return 0;
200 }
201 
202 static int
203 ata_sis_ch_attach(device_t dev)
204 {
205     struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
206     struct ata_channel *ch = device_get_softc(dev);
207     int offset = ch->unit << ((ctlr->chip->chipid == ATA_SIS182) ? 5 : 6);
208 
209     /* setup the usual register normal pci style */
210     if (ata_pci_ch_attach(dev))
211 	return ENXIO;
212 
213     ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
214     ch->r_io[ATA_SSTATUS].offset = 0x00 + offset;
215     ch->r_io[ATA_SERROR].res = ctlr->r_res2;
216     ch->r_io[ATA_SERROR].offset = 0x04 + offset;
217     ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
218     ch->r_io[ATA_SCONTROL].offset = 0x08 + offset;
219     ch->flags |= ATA_NO_SLAVE;
220 
221     /* XXX SOS PHY hotplug handling missing in SiS chip ?? */
222     /* XXX SOS unknown how to enable PHY state change interrupt */
223     return 0;
224 }
225 
226 static void
227 ata_sis_reset(device_t dev)
228 {
229     if (ata_sata_phy_reset(dev))
230 	ata_generic_reset(dev);
231 }
232 
233 static void
234 ata_sis_setmode(device_t dev, int mode)
235 {
236     device_t gparent = GRANDPARENT(dev);
237     struct ata_pci_controller *ctlr = device_get_softc(gparent);
238     struct ata_channel *ch = device_get_softc(device_get_parent(dev));
239     struct ata_device *atadev = device_get_softc(dev);
240     int devno = (ch->unit << 1) + atadev->unit;
241     int error;
242 
243     mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
244 
245     if (ctlr->chip->cfg1 == SIS_133NEW) {
246 	if (mode > ATA_UDMA2 &&
247 	    pci_read_config(gparent, ch->unit ? 0x52 : 0x50,2) & 0x8000) {
248 	    ata_print_cable(dev, "controller");
249 	    mode = ATA_UDMA2;
250 	}
251     }
252     else {
253 	if (mode > ATA_UDMA2 &&
254 	    pci_read_config(gparent, 0x48, 1)&(ch->unit ? 0x20 : 0x10)) {
255 	    ata_print_cable(dev, "controller");
256 	    mode = ATA_UDMA2;
257 	}
258     }
259 
260     error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
261 
262     if (bootverbose)
263 	device_printf(dev, "%ssetting %s on %s chip\n",
264 		      (error) ? "FAILURE " : "",
265 		      ata_mode2str(mode), ctlr->chip->text);
266     if (!error) {
267 	switch (ctlr->chip->cfg1) {
268 	case SIS_133NEW: {
269 	    u_int32_t timings[] =
270 		{ 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008,
271 		  0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac,
272 		  0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c};
273 	    u_int32_t reg;
274 
275 	    reg = (pci_read_config(gparent, 0x57, 1)&0x40?0x70:0x40)+(devno<<2);
276 	    pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 4);
277 	    break;
278 	    }
279 	case SIS_133OLD: {
280 	    u_int16_t timings[] =
281 	     { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031,
282 	       0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 };
283 
284 	    u_int16_t reg = 0x40 + (devno << 1);
285 
286 	    pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2);
287 	    break;
288 	    }
289 	case SIS_100NEW: {
290 	    u_int16_t timings[] =
291 		{ 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033,
292 		  0x0031, 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 };
293 	    u_int16_t reg = 0x40 + (devno << 1);
294 
295 	    pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2);
296 	    break;
297 	    }
298 	case SIS_100OLD:
299 	case SIS_66:
300 	case SIS_33: {
301 	    u_int16_t timings[] =
302 		{ 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303,
303 		  0x0301, 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 };
304 	    u_int16_t reg = 0x40 + (devno << 1);
305 
306 	    pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2);
307 	    break;
308 	    }
309 	}
310 	atadev->mode = mode;
311     }
312 }
313 
314 ATA_DECLARE_DRIVER(ata_sis);
315