1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification, immediately at the beginning of the file. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/param.h> 30 #include <sys/module.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/ata.h> 34 #include <sys/bus.h> 35 #include <sys/endian.h> 36 #include <sys/malloc.h> 37 #include <sys/lock.h> 38 #include <sys/mutex.h> 39 #include <sys/sema.h> 40 #include <sys/taskqueue.h> 41 #include <vm/uma.h> 42 #include <machine/stdarg.h> 43 #include <machine/resource.h> 44 #include <machine/bus.h> 45 #include <sys/rman.h> 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcireg.h> 48 #include <dev/ata/ata-all.h> 49 #include <dev/ata/ata-pci.h> 50 #include <ata_if.h> 51 52 /* local prototypes */ 53 static int ata_sis_chipinit(device_t dev); 54 static int ata_sis_ch_attach(device_t dev); 55 static void ata_sis_reset(device_t dev); 56 static int ata_sis_setmode(device_t dev, int target, int mode); 57 58 /* misc defines */ 59 #define SIS_33 1 60 #define SIS_66 2 61 #define SIS_100NEW 3 62 #define SIS_100OLD 4 63 #define SIS_133NEW 5 64 #define SIS_133OLD 6 65 #define SIS_SATA 7 66 67 /* 68 * Silicon Integrated Systems Corp. (SiS) chipset support functions 69 */ 70 static int 71 ata_sis_probe(device_t dev) 72 { 73 struct ata_pci_controller *ctlr = device_get_softc(dev); 74 const struct ata_chip_id *idx; 75 static const struct ata_chip_id ids[] = 76 {{ ATA_SIS182, 0x00, SIS_SATA, 0, ATA_SA150, "182" }, /* south */ 77 { ATA_SIS181, 0x00, SIS_SATA, 0, ATA_SA150, "181" }, /* south */ 78 { ATA_SIS180, 0x00, SIS_SATA, 0, ATA_SA150, "180" }, /* south */ 79 { ATA_SIS965, 0x00, SIS_133NEW, 0, ATA_UDMA6, "965" }, /* south */ 80 { ATA_SIS964, 0x00, SIS_133NEW, 0, ATA_UDMA6, "964" }, /* south */ 81 { ATA_SIS963, 0x00, SIS_133NEW, 0, ATA_UDMA6, "963" }, /* south */ 82 { ATA_SIS962, 0x00, SIS_133NEW, 0, ATA_UDMA6, "962" }, /* south */ 83 84 { ATA_SIS745, 0x00, SIS_100NEW, 0, ATA_UDMA5, "745" }, /* 1chip */ 85 { ATA_SIS735, 0x00, SIS_100NEW, 0, ATA_UDMA5, "735" }, /* 1chip */ 86 { ATA_SIS733, 0x00, SIS_100NEW, 0, ATA_UDMA5, "733" }, /* 1chip */ 87 { ATA_SIS730, 0x00, SIS_100OLD, 0, ATA_UDMA5, "730" }, /* 1chip */ 88 89 { ATA_SIS635, 0x00, SIS_100NEW, 0, ATA_UDMA5, "635" }, /* 1chip */ 90 { ATA_SIS633, 0x00, SIS_100NEW, 0, ATA_UDMA5, "633" }, /* unknown */ 91 { ATA_SIS630, 0x30, SIS_100OLD, 0, ATA_UDMA5, "630S"}, /* 1chip */ 92 { ATA_SIS630, 0x00, SIS_66, 0, ATA_UDMA4, "630" }, /* 1chip */ 93 { ATA_SIS620, 0x00, SIS_66, 0, ATA_UDMA4, "620" }, /* 1chip */ 94 95 { ATA_SIS550, 0x00, SIS_66, 0, ATA_UDMA5, "550" }, 96 { ATA_SIS540, 0x00, SIS_66, 0, ATA_UDMA4, "540" }, 97 { ATA_SIS530, 0x00, SIS_66, 0, ATA_UDMA4, "530" }, 98 99 { ATA_SIS5513, 0xc2, SIS_33, 1, ATA_UDMA2, "5513" }, 100 { ATA_SIS5513, 0x00, SIS_33, 1, ATA_WDMA2, "5513" }, 101 { 0, 0, 0, 0, 0, 0 }}; 102 static struct ata_chip_id id[] = 103 {{ ATA_SISSOUTH, 0x10, 0, 0, 0, "" }, { 0, 0, 0, 0, 0, 0 }}; 104 char buffer[64]; 105 int found = 0; 106 107 if (pci_get_class(dev) != PCIC_STORAGE) 108 return (ENXIO); 109 110 if (pci_get_vendor(dev) != ATA_SIS_ID) 111 return ENXIO; 112 113 if (!(idx = ata_find_chip(dev, ids, -pci_get_slot(dev)))) 114 return ENXIO; 115 116 if (idx->cfg2) { 117 u_int8_t reg57 = pci_read_config(dev, 0x57, 1); 118 119 pci_write_config(dev, 0x57, (reg57 & 0x7f), 1); 120 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5518) { 121 found = 1; 122 memcpy(&id[0], idx, sizeof(id[0])); 123 id[0].cfg1 = SIS_133NEW; 124 id[0].max_dma = ATA_UDMA6; 125 sprintf(buffer, "SiS 962/963 %s controller", 126 ata_mode2str(idx->max_dma)); 127 } 128 pci_write_config(dev, 0x57, reg57, 1); 129 } 130 if (idx->cfg2 && !found) { 131 u_int8_t reg4a = pci_read_config(dev, 0x4a, 1); 132 133 pci_write_config(dev, 0x4a, (reg4a | 0x10), 1); 134 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5517) { 135 found = 1; 136 if (ata_find_chip(dev, id, pci_get_slot(dev))) { 137 id[0].cfg1 = SIS_133OLD; 138 id[0].max_dma = ATA_UDMA6; 139 } else { 140 id[0].cfg1 = SIS_100NEW; 141 id[0].max_dma = ATA_UDMA5; 142 } 143 sprintf(buffer, "SiS 961 %s controller",ata_mode2str(idx->max_dma)); 144 } 145 pci_write_config(dev, 0x4a, reg4a, 1); 146 } 147 if (!found) 148 sprintf(buffer,"SiS %s %s controller", 149 idx->text, ata_mode2str(idx->max_dma)); 150 else 151 idx = &id[0]; 152 153 device_set_desc_copy(dev, buffer); 154 ctlr->chip = idx; 155 ctlr->chipinit = ata_sis_chipinit; 156 return (BUS_PROBE_LOW_PRIORITY); 157 } 158 159 static int 160 ata_sis_chipinit(device_t dev) 161 { 162 struct ata_pci_controller *ctlr = device_get_softc(dev); 163 164 if (ata_setup_interrupt(dev, ata_generic_intr)) 165 return ENXIO; 166 167 switch (ctlr->chip->cfg1) { 168 case SIS_33: 169 break; 170 case SIS_66: 171 case SIS_100OLD: 172 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 1) & ~0x04, 1); 173 break; 174 case SIS_100NEW: 175 case SIS_133OLD: 176 pci_write_config(dev, 0x49, pci_read_config(dev, 0x49, 1) & ~0x01, 1); 177 break; 178 case SIS_133NEW: 179 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 2) | 0x0008, 2); 180 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 2) | 0x0008, 2); 181 break; 182 case SIS_SATA: 183 ctlr->r_type2 = SYS_RES_IOPORT; 184 ctlr->r_rid2 = PCIR_BAR(5); 185 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 186 &ctlr->r_rid2, RF_ACTIVE))) { 187 ctlr->ch_attach = ata_sis_ch_attach; 188 ctlr->ch_detach = ata_pci_ch_detach; 189 ctlr->reset = ata_sis_reset; 190 } 191 ctlr->setmode = ata_sata_setmode; 192 ctlr->getrev = ata_sata_getrev; 193 return 0; 194 default: 195 return ENXIO; 196 } 197 ctlr->setmode = ata_sis_setmode; 198 return 0; 199 } 200 201 static int 202 ata_sis_ch_attach(device_t dev) 203 { 204 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 205 struct ata_channel *ch = device_get_softc(dev); 206 int offset = ch->unit << ((ctlr->chip->chipid == ATA_SIS182) ? 5 : 6); 207 208 /* setup the usual register normal pci style */ 209 if (ata_pci_ch_attach(dev)) 210 return ENXIO; 211 212 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 213 ch->r_io[ATA_SSTATUS].offset = 0x00 + offset; 214 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 215 ch->r_io[ATA_SERROR].offset = 0x04 + offset; 216 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 217 ch->r_io[ATA_SCONTROL].offset = 0x08 + offset; 218 ch->flags |= ATA_NO_SLAVE; 219 ch->flags |= ATA_SATA; 220 221 /* XXX SOS PHY hotplug handling missing in SiS chip ?? */ 222 /* XXX SOS unknown how to enable PHY state change interrupt */ 223 return 0; 224 } 225 226 static void 227 ata_sis_reset(device_t dev) 228 { 229 struct ata_channel *ch = device_get_softc(dev); 230 231 if (ata_sata_phy_reset(dev, -1, 1)) 232 ata_generic_reset(dev); 233 else 234 ch->devices = 0; 235 } 236 237 static int 238 ata_sis_setmode(device_t dev, int target, int mode) 239 { 240 device_t parent = device_get_parent(dev); 241 struct ata_pci_controller *ctlr = device_get_softc(parent); 242 struct ata_channel *ch = device_get_softc(dev); 243 int devno = (ch->unit << 1) + target; 244 245 mode = min(mode, ctlr->chip->max_dma); 246 247 if (ctlr->chip->cfg1 == SIS_133NEW) { 248 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 249 pci_read_config(parent, ch->unit ? 0x52 : 0x50,2) & 0x8000) { 250 ata_print_cable(dev, "controller"); 251 mode = ATA_UDMA2; 252 } 253 } else { 254 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 255 pci_read_config(parent, 0x48, 1)&(ch->unit ? 0x20 : 0x10)) { 256 ata_print_cable(dev, "controller"); 257 mode = ATA_UDMA2; 258 } 259 } 260 261 switch (ctlr->chip->cfg1) { 262 case SIS_133NEW: { 263 static const uint32_t timings[] = 264 { 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008, 265 0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac, 266 0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c}; 267 u_int32_t reg; 268 269 reg = (pci_read_config(parent, 0x57, 1)&0x40?0x70:0x40)+(devno<<2); 270 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 4); 271 break; 272 } 273 case SIS_133OLD: { 274 static const uint16_t timings[] = 275 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031, 276 0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 }; 277 278 u_int16_t reg = 0x40 + (devno << 1); 279 280 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2); 281 break; 282 } 283 case SIS_100NEW: { 284 static const uint16_t timings[] = 285 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 286 0x0031, 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 }; 287 u_int16_t reg = 0x40 + (devno << 1); 288 289 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2); 290 break; 291 } 292 case SIS_100OLD: 293 case SIS_66: 294 case SIS_33: { 295 static const uint16_t timings[] = 296 { 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303, 297 0x0301, 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 }; 298 u_int16_t reg = 0x40 + (devno << 1); 299 300 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2); 301 break; 302 } 303 } 304 return (mode); 305 } 306 307 ATA_DECLARE_DRIVER(ata_sis); 308