1 /*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ata.h" 31 #include <sys/param.h> 32 #include <sys/module.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/ata.h> 36 #include <sys/bus.h> 37 #include <sys/endian.h> 38 #include <sys/malloc.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/sema.h> 42 #include <sys/taskqueue.h> 43 #include <vm/uma.h> 44 #include <machine/stdarg.h> 45 #include <machine/resource.h> 46 #include <machine/bus.h> 47 #include <sys/rman.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/ata/ata-all.h> 51 #include <dev/ata/ata-pci.h> 52 #include <ata_if.h> 53 54 /* local prototypes */ 55 static int ata_cmd_ch_attach(device_t dev); 56 static int ata_cmd_status(device_t dev); 57 static int ata_cmd_setmode(device_t dev, int target, int mode); 58 static int ata_sii_ch_attach(device_t dev); 59 static int ata_sii_ch_detach(device_t dev); 60 static int ata_sii_status(device_t dev); 61 static void ata_sii_reset(device_t dev); 62 static int ata_sii_setmode(device_t dev, int target, int mode); 63 static int ata_siiprb_ch_attach(device_t dev); 64 static int ata_siiprb_ch_detach(device_t dev); 65 static int ata_siiprb_status(device_t dev); 66 static int ata_siiprb_begin_transaction(struct ata_request *request); 67 static int ata_siiprb_end_transaction(struct ata_request *request); 68 static int ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result); 69 static int ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t result); 70 static u_int32_t ata_siiprb_softreset(device_t dev, int port); 71 static void ata_siiprb_reset(device_t dev); 72 static void ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 73 static void ata_siiprb_dmainit(device_t dev); 74 75 /* misc defines */ 76 #define SII_MEMIO 1 77 #define SII_PRBIO 2 78 #define SII_INTR 0x01 79 #define SII_SETCLK 0x02 80 #define SII_BUG 0x04 81 #define SII_4CH 0x08 82 83 84 /* 85 * Silicon Image Inc. (SiI) (former CMD) chipset support functions 86 */ 87 static int 88 ata_sii_probe(device_t dev) 89 { 90 struct ata_pci_controller *ctlr = device_get_softc(dev); 91 static struct ata_chip_id ids[] = 92 {{ ATA_SII3114, 0x00, SII_MEMIO, SII_4CH, ATA_SA150, "3114" }, 93 { ATA_SII3512, 0x02, SII_MEMIO, 0, ATA_SA150, "3512" }, 94 { ATA_SII3112, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" }, 95 { ATA_SII3112_1, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" }, 96 { ATA_SII3512, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3512" }, 97 { ATA_SII3112, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" }, 98 { ATA_SII3112_1, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" }, 99 { ATA_SII3124, 0x00, SII_PRBIO, SII_4CH, ATA_SA300, "3124" }, 100 { ATA_SII3132, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" }, 101 { ATA_SII3132_1, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" }, 102 { ATA_SII3132_2, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" }, 103 { ATA_SII0680, 0x00, SII_MEMIO, SII_SETCLK, ATA_UDMA6, "680" }, 104 { ATA_CMD649, 0x00, 0, SII_INTR, ATA_UDMA5, "(CMD) 649" }, 105 { ATA_CMD648, 0x00, 0, SII_INTR, ATA_UDMA4, "(CMD) 648" }, 106 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "(CMD) 646U2" }, 107 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "(CMD) 646" }, 108 { 0, 0, 0, 0, 0, 0}}; 109 110 if (pci_get_vendor(dev) != ATA_SILICON_IMAGE_ID) 111 return ENXIO; 112 113 if (!(ctlr->chip = ata_match_chip(dev, ids))) 114 return ENXIO; 115 116 ata_set_desc(dev); 117 ctlr->chipinit = ata_sii_chipinit; 118 return (BUS_PROBE_DEFAULT); 119 } 120 121 int 122 ata_sii_chipinit(device_t dev) 123 { 124 struct ata_pci_controller *ctlr = device_get_softc(dev); 125 126 if (ata_setup_interrupt(dev, ata_generic_intr)) 127 return ENXIO; 128 129 switch (ctlr->chip->cfg1) { 130 case SII_PRBIO: 131 ctlr->r_type1 = SYS_RES_MEMORY; 132 ctlr->r_rid1 = PCIR_BAR(0); 133 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 134 &ctlr->r_rid1, RF_ACTIVE))) 135 return ENXIO; 136 137 ctlr->r_rid2 = PCIR_BAR(2); 138 ctlr->r_type2 = SYS_RES_MEMORY; 139 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 140 &ctlr->r_rid2, RF_ACTIVE))){ 141 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1); 142 return ENXIO; 143 } 144 ctlr->ch_attach = ata_siiprb_ch_attach; 145 ctlr->ch_detach = ata_siiprb_ch_detach; 146 ctlr->reset = ata_siiprb_reset; 147 ctlr->setmode = ata_sata_setmode; 148 ctlr->getrev = ata_sata_getrev; 149 ctlr->channels = (ctlr->chip->cfg2 == SII_4CH) ? 4 : 2; 150 151 /* reset controller */ 152 ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000); 153 DELAY(10000); 154 ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f); 155 break; 156 157 case SII_MEMIO: 158 ctlr->r_type2 = SYS_RES_MEMORY; 159 ctlr->r_rid2 = PCIR_BAR(5); 160 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 161 &ctlr->r_rid2, RF_ACTIVE))){ 162 if (ctlr->chip->chipid != ATA_SII0680 || 163 (pci_read_config(dev, 0x8a, 1) & 1)) 164 return ENXIO; 165 } 166 167 if (ctlr->chip->cfg2 & SII_SETCLK) { 168 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 169 pci_write_config(dev, 0x8a, 170 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1); 171 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 172 device_printf(dev, "%s could not set ATA133 clock\n", 173 ctlr->chip->text); 174 } 175 176 /* if we have 4 channels enable the second set */ 177 if (ctlr->chip->cfg2 & SII_4CH) { 178 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002); 179 ctlr->channels = 4; 180 } 181 182 /* dont block interrupts from any channel */ 183 pci_write_config(dev, 0x48, 184 (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4); 185 186 /* enable PCI interrupt as BIOS might not */ 187 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1); 188 189 if (ctlr->r_res2) { 190 ctlr->ch_attach = ata_sii_ch_attach; 191 ctlr->ch_detach = ata_sii_ch_detach; 192 } 193 194 if (ctlr->chip->max_dma >= ATA_SA150) { 195 ctlr->reset = ata_sii_reset; 196 ctlr->setmode = ata_sata_setmode; 197 ctlr->getrev = ata_sata_getrev; 198 } 199 else 200 ctlr->setmode = ata_sii_setmode; 201 break; 202 203 default: 204 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) { 205 device_printf(dev, "HW has secondary channel disabled\n"); 206 ctlr->channels = 1; 207 } 208 209 /* enable interrupt as BIOS might not */ 210 pci_write_config(dev, 0x71, 0x01, 1); 211 212 ctlr->ch_attach = ata_cmd_ch_attach; 213 ctlr->ch_detach = ata_pci_ch_detach; 214 ctlr->setmode = ata_cmd_setmode; 215 break; 216 } 217 return 0; 218 } 219 220 static int 221 ata_cmd_ch_attach(device_t dev) 222 { 223 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 224 struct ata_channel *ch = device_get_softc(dev); 225 226 /* setup the usual register normal pci style */ 227 if (ata_pci_ch_attach(dev)) 228 return ENXIO; 229 230 if (ctlr->chip->cfg2 & SII_INTR) 231 ch->hw.status = ata_cmd_status; 232 233 return 0; 234 } 235 236 static int 237 ata_cmd_status(device_t dev) 238 { 239 struct ata_channel *ch = device_get_softc(dev); 240 u_int8_t reg71; 241 242 if (((reg71 = pci_read_config(device_get_parent(dev), 0x71, 1)) & 243 (ch->unit ? 0x08 : 0x04))) { 244 pci_write_config(device_get_parent(dev), 0x71, 245 reg71 & ~(ch->unit ? 0x04 : 0x08), 1); 246 return ata_pci_status(dev); 247 } 248 return 0; 249 } 250 251 static int 252 ata_cmd_setmode(device_t dev, int target, int mode) 253 { 254 device_t parent = device_get_parent(dev); 255 struct ata_pci_controller *ctlr = device_get_softc(parent); 256 struct ata_channel *ch = device_get_softc(dev); 257 int devno = (ch->unit << 1) + target; 258 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7); 259 int ureg = ch->unit ? 0x7b : 0x73; 260 int piomode; 261 uint8_t piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f, 0x87, 0x32, 0x3f }; 262 uint8_t udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 }, 263 { 0x11, 0x42 }, { 0x25, 0x8a }, 264 { 0x15, 0x4a }, { 0x05, 0x0a } }; 265 266 mode = min(mode, ctlr->chip->max_dma); 267 if (mode >= ATA_UDMA0) { 268 u_int8_t umode = pci_read_config(parent, ureg, 1); 269 270 umode &= ~(target == 0 ? 0x35 : 0xca); 271 umode |= udmatimings[mode & ATA_MODE_MASK][target]; 272 pci_write_config(parent, ureg, umode, 1); 273 piomode = ATA_PIO4; 274 } else { 275 pci_write_config(parent, ureg, 276 pci_read_config(parent, ureg, 1) & 277 ~(target == 0 ? 0x35 : 0xca), 1); 278 piomode = mode; 279 } 280 pci_write_config(parent, treg, piotimings[ata_mode2idx(piomode)], 1); 281 return (mode); 282 } 283 284 static int 285 ata_sii_ch_attach(device_t dev) 286 { 287 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 288 struct ata_channel *ch = device_get_softc(dev); 289 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2); 290 int i; 291 292 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 293 ch->r_io[i].res = ctlr->r_res2; 294 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8); 295 } 296 ch->r_io[ATA_CONTROL].res = ctlr->r_res2; 297 ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8); 298 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 299 ata_default_registers(dev); 300 301 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2; 302 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8); 303 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2; 304 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8); 305 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2; 306 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8); 307 308 if (ctlr->chip->max_dma >= ATA_SA150) { 309 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 310 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8); 311 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 312 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8); 313 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 314 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8); 315 ch->flags |= ATA_NO_SLAVE; 316 ch->flags |= ATA_SATA; 317 ch->flags |= ATA_KNOWN_PRESENCE; 318 319 /* enable PHY state change interrupt */ 320 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16)); 321 } 322 323 if (ctlr->chip->cfg2 & SII_BUG) { 324 /* work around errata in early chips */ 325 ch->dma.boundary = 8192; 326 ch->dma.segsize = 15 * DEV_BSIZE; 327 } 328 329 ata_pci_hw(dev); 330 ch->hw.status = ata_sii_status; 331 if (ctlr->chip->cfg2 & SII_SETCLK) 332 ch->flags |= ATA_CHECKS_CABLE; 333 334 ata_pci_dmainit(dev); 335 336 return 0; 337 } 338 339 static int 340 ata_sii_ch_detach(device_t dev) 341 { 342 343 ata_pci_dmafini(dev); 344 return (0); 345 } 346 347 static int 348 ata_sii_status(device_t dev) 349 { 350 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 351 struct ata_channel *ch = device_get_softc(dev); 352 int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8); 353 int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8); 354 355 /* do we have any PHY events ? */ 356 if (ctlr->chip->max_dma >= ATA_SA150 && 357 (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010)) 358 ata_sata_phy_check_events(dev, -1); 359 360 if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800) 361 return ata_pci_status(dev); 362 else 363 return 0; 364 } 365 366 static void 367 ata_sii_reset(device_t dev) 368 { 369 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 370 struct ata_channel *ch = device_get_softc(dev); 371 int offset = ((ch->unit & 1) << 7) + ((ch->unit & 2) << 8); 372 uint32_t val; 373 374 /* Apply R_ERR on DMA activate FIS errata workaround. */ 375 val = ATA_INL(ctlr->r_res2, 0x14c + offset); 376 if ((val & 0x3) == 0x1) 377 ATA_OUTL(ctlr->r_res2, 0x14c + offset, val & ~0x3); 378 379 if (ata_sata_phy_reset(dev, -1, 1)) 380 ata_generic_reset(dev); 381 else 382 ch->devices = 0; 383 } 384 385 static int 386 ata_sii_setmode(device_t dev, int target, int mode) 387 { 388 device_t parent = device_get_parent(dev); 389 struct ata_pci_controller *ctlr = device_get_softc(parent); 390 struct ata_channel *ch = device_get_softc(dev); 391 int rego = (ch->unit << 4) + (target << 1); 392 int mreg = ch->unit ? 0x84 : 0x80; 393 int mask = 0x03 << (target << 2); 394 int mval = pci_read_config(parent, mreg, 1) & ~mask; 395 int piomode; 396 u_int8_t preg = 0xa4 + rego; 397 u_int8_t dreg = 0xa8 + rego; 398 u_int8_t ureg = 0xac + rego; 399 u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 400 u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 }; 401 u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 }; 402 403 mode = min(mode, ctlr->chip->max_dma); 404 405 if (ctlr->chip->cfg2 & SII_SETCLK) { 406 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 407 (pci_read_config(parent, 0x79, 1) & 408 (ch->unit ? 0x02 : 0x01))) { 409 ata_print_cable(dev, "controller"); 410 mode = ATA_UDMA2; 411 } 412 } 413 if (mode >= ATA_UDMA0) { 414 pci_write_config(parent, mreg, 415 mval | (0x03 << (target << 2)), 1); 416 pci_write_config(parent, ureg, 417 (pci_read_config(parent, ureg, 1) & ~0x3f) | 418 udmatimings[mode & ATA_MODE_MASK], 1); 419 piomode = ATA_PIO4; 420 } else if (mode >= ATA_WDMA0) { 421 pci_write_config(parent, mreg, 422 mval | (0x02 << (target << 2)), 1); 423 pci_write_config(parent, dreg, dmatimings[mode & ATA_MODE_MASK], 2); 424 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 : 425 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4; 426 } else { 427 pci_write_config(parent, mreg, 428 mval | (0x01 << (target << 2)), 1); 429 piomode = mode; 430 } 431 pci_write_config(parent, preg, piotimings[ata_mode2idx(piomode)], 2); 432 return (mode); 433 } 434 435 436 struct ata_siiprb_dma_prdentry { 437 u_int64_t addr; 438 u_int32_t count; 439 u_int32_t control; 440 } __packed; 441 442 #define ATA_SIIPRB_DMA_ENTRIES 129 443 struct ata_siiprb_ata_command { 444 struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES]; 445 } __packed; 446 447 struct ata_siiprb_atapi_command { 448 u_int8_t ccb[16]; 449 struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES]; 450 } __packed; 451 452 struct ata_siiprb_command { 453 u_int16_t control; 454 u_int16_t protocol_override; 455 u_int32_t transfer_count; 456 u_int8_t fis[24]; 457 union { 458 struct ata_siiprb_ata_command ata; 459 struct ata_siiprb_atapi_command atapi; 460 } u; 461 } __packed; 462 463 static int 464 ata_siiprb_ch_attach(device_t dev) 465 { 466 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 467 struct ata_channel *ch = device_get_softc(dev); 468 int offset = ch->unit * 0x2000; 469 470 ata_siiprb_dmainit(dev); 471 472 /* set the SATA resources */ 473 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 474 ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset; 475 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 476 ch->r_io[ATA_SERROR].offset = 0x1f08 + offset; 477 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 478 ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset; 479 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2; 480 ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset; 481 482 ch->hw.status = ata_siiprb_status; 483 ch->hw.begin_transaction = ata_siiprb_begin_transaction; 484 ch->hw.end_transaction = ata_siiprb_end_transaction; 485 ch->hw.command = NULL; /* not used here */ 486 ch->hw.softreset = ata_siiprb_softreset; 487 ch->hw.pm_read = ata_siiprb_pm_read; 488 ch->hw.pm_write = ata_siiprb_pm_write; 489 ch->flags |= ATA_NO_SLAVE; 490 ch->flags |= ATA_SATA; 491 return 0; 492 } 493 494 static int 495 ata_siiprb_ch_detach(device_t dev) 496 { 497 struct ata_channel *ch = device_get_softc(dev); 498 499 if (ch->dma.work_tag && ch->dma.work_map) 500 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 501 BUS_DMASYNC_POSTWRITE); 502 ata_dmafini(dev); 503 return 0; 504 } 505 506 static int 507 ata_siiprb_status(device_t dev) 508 { 509 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 510 struct ata_channel *ch = device_get_softc(dev); 511 u_int32_t action = ATA_INL(ctlr->r_res1, 0x0044); 512 int offset = ch->unit * 0x2000; 513 514 if (action & (1 << ch->unit)) { 515 u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset); 516 517 /* do we have any PHY events ? */ 518 ata_sata_phy_check_events(dev, -1); 519 520 /* clear interrupt(s) */ 521 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus); 522 523 /* do we have any device action ? */ 524 return (istatus & 0x00000003); 525 } 526 return 0; 527 } 528 529 static int 530 ata_siiprb_begin_transaction(struct ata_request *request) 531 { 532 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 533 struct ata_channel *ch = device_get_softc(request->parent); 534 struct ata_siiprb_command *prb; 535 struct ata_siiprb_dma_prdentry *prd; 536 int offset = ch->unit * 0x2000; 537 u_int64_t prb_bus; 538 539 /* SOS XXX */ 540 if (request->u.ata.command == ATA_DEVICE_RESET) { 541 request->result = 0; 542 return ATA_OP_FINISHED; 543 } 544 545 /* get a piece of the workspace for this request */ 546 prb = (struct ata_siiprb_command *)ch->dma.work; 547 548 /* clear the prb structure */ 549 bzero(prb, sizeof(struct ata_siiprb_command)); 550 551 /* setup the FIS for this request */ 552 if (!ata_request2fis_h2d(request, &prb->fis[0])) { 553 device_printf(request->parent, "setting up SATA FIS failed\n"); 554 request->result = EIO; 555 return ATA_OP_FINISHED; 556 } 557 558 /* setup transfer type */ 559 if (request->flags & ATA_R_ATAPI) { 560 bcopy(request->u.atapi.ccb, prb->u.atapi.ccb, 16); 561 if (request->flags & ATA_R_ATAPI16) 562 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000020); 563 else 564 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000020); 565 if (request->flags & ATA_R_READ) 566 prb->control = htole16(0x0010); 567 if (request->flags & ATA_R_WRITE) 568 prb->control = htole16(0x0020); 569 prd = &prb->u.atapi.prd[0]; 570 } 571 else 572 prd = &prb->u.ata.prd[0]; 573 574 /* if request moves data setup and load SG list */ 575 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 576 if (ch->dma.load(request, prd, NULL)) { 577 device_printf(request->parent, "setting up DMA failed\n"); 578 request->result = EIO; 579 return ATA_OP_FINISHED; 580 } 581 } 582 583 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_PREWRITE); 584 585 /* activate the prb */ 586 prb_bus = ch->dma.work_bus; 587 ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus); 588 ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus>>32); 589 590 /* start the timeout */ 591 callout_reset(&request->callout, request->timeout * hz, 592 (timeout_t*)ata_timeout, request); 593 return ATA_OP_CONTINUES; 594 } 595 596 static int 597 ata_siiprb_end_transaction(struct ata_request *request) 598 { 599 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 600 struct ata_channel *ch = device_get_softc(request->parent); 601 struct ata_siiprb_command *prb; 602 int offset = ch->unit * 0x2000; 603 int error, timeout; 604 605 /* kill the timeout */ 606 callout_stop(&request->callout); 607 608 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_POSTWRITE); 609 610 prb = (struct ata_siiprb_command *) 611 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 612 613 /* any controller errors flagged ? */ 614 if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) { 615 if (bootverbose) 616 printf("ata_siiprb_end_transaction %s error=%08x\n", 617 ata_cmd2str(request), error); 618 619 /* if device error status get details */ 620 if (error == 1 || error == 2) { 621 request->status = prb->fis[2]; 622 if (request->status & ATA_S_ERROR) 623 request->error = prb->fis[3]; 624 } 625 626 /* SOS XXX handle other controller errors here */ 627 628 /* initialize port */ 629 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000004); 630 631 /* poll for port ready */ 632 for (timeout = 0; timeout < 1000; timeout++) { 633 DELAY(1000); 634 if (ATA_INL(ctlr->r_res2, 0x1008 + offset) & 0x00040000) 635 break; 636 } 637 if (bootverbose) { 638 if (timeout >= 1000) 639 device_printf(ch->dev, "port initialize timeout\n"); 640 else 641 device_printf(ch->dev, "port initialize time=%dms\n", timeout); 642 } 643 } 644 645 /* on control commands read back registers to the request struct */ 646 if (request->flags & ATA_R_CONTROL) { 647 request->u.ata.count = prb->fis[12] | ((u_int16_t)prb->fis[13] << 8); 648 request->u.ata.lba = prb->fis[4] | ((u_int64_t)prb->fis[5] << 8) | 649 ((u_int64_t)prb->fis[6] << 16); 650 if (request->flags & ATA_R_48BIT) 651 request->u.ata.lba |= ((u_int64_t)prb->fis[8] << 24) | 652 ((u_int64_t)prb->fis[9] << 32) | 653 ((u_int64_t)prb->fis[10] << 40); 654 else 655 request->u.ata.lba |= ((u_int64_t)(prb->fis[7] & 0x0f) << 24); 656 } 657 658 /* update progress */ 659 if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) { 660 if (request->flags & ATA_R_READ) 661 request->donecount = le32toh(prb->transfer_count); 662 else 663 request->donecount = request->bytecount; 664 } 665 666 /* release SG list etc */ 667 ch->dma.unload(request); 668 669 return ATA_OP_FINISHED; 670 } 671 672 static int 673 ata_siiprb_issue_cmd(device_t dev) 674 { 675 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 676 struct ata_channel *ch = device_get_softc(dev); 677 u_int64_t prb_bus = ch->dma.work_bus; 678 u_int32_t status; 679 int offset = ch->unit * 0x2000; 680 int timeout; 681 682 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_PREWRITE); 683 684 /* issue command to chip */ 685 ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus); 686 ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus >> 32); 687 688 /* poll for command finished */ 689 for (timeout = 0; timeout < 10000; timeout++) { 690 DELAY(1000); 691 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000) 692 break; 693 } 694 695 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_POSTWRITE); 696 697 // SOS XXX ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x00010000); 698 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x08ff08ff); 699 700 if (timeout >= 1000) 701 return EIO; 702 703 if (bootverbose) 704 device_printf(dev, "siiprb_issue_cmd time=%dms status=%08x\n", 705 timeout, status); 706 return 0; 707 } 708 709 static int 710 ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result) 711 { 712 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 713 struct ata_channel *ch = device_get_softc(dev); 714 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work; 715 int offset = ch->unit * 0x2000; 716 717 if (port < 0) { 718 *result = ATA_IDX_INL(ch, reg); 719 return (0); 720 } 721 if (port < ATA_PM) { 722 switch (reg) { 723 case ATA_SSTATUS: 724 reg = 0; 725 break; 726 case ATA_SERROR: 727 reg = 1; 728 break; 729 case ATA_SCONTROL: 730 reg = 2; 731 break; 732 default: 733 return (EINVAL); 734 } 735 } 736 bzero(prb, sizeof(struct ata_siiprb_command)); 737 prb->fis[0] = 0x27; /* host to device */ 738 prb->fis[1] = 0x8f; /* command FIS to PM port */ 739 prb->fis[2] = ATA_READ_PM; 740 prb->fis[3] = reg; 741 prb->fis[7] = port; 742 if (ata_siiprb_issue_cmd(dev)) { 743 device_printf(dev, "error reading PM port\n"); 744 return EIO; 745 } 746 prb = (struct ata_siiprb_command *) 747 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 748 *result = prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24); 749 return 0; 750 } 751 752 static int 753 ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t value) 754 { 755 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 756 struct ata_channel *ch = device_get_softc(dev); 757 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work; 758 int offset = ch->unit * 0x2000; 759 760 if (port < 0) { 761 ATA_IDX_OUTL(ch, reg, value); 762 return (0); 763 } 764 if (port < ATA_PM) { 765 switch (reg) { 766 case ATA_SSTATUS: 767 reg = 0; 768 break; 769 case ATA_SERROR: 770 reg = 1; 771 break; 772 case ATA_SCONTROL: 773 reg = 2; 774 break; 775 default: 776 return (EINVAL); 777 } 778 } 779 bzero(prb, sizeof(struct ata_siiprb_command)); 780 prb->fis[0] = 0x27; /* host to device */ 781 prb->fis[1] = 0x8f; /* command FIS to PM port */ 782 prb->fis[2] = ATA_WRITE_PM; 783 prb->fis[3] = reg; 784 prb->fis[7] = port; 785 prb->fis[12] = value & 0xff; 786 prb->fis[4] = (value >> 8) & 0xff; 787 prb->fis[5] = (value >> 16) & 0xff; 788 prb->fis[6] = (value >> 24) & 0xff; 789 if (ata_siiprb_issue_cmd(dev)) { 790 device_printf(dev, "error writing PM port\n"); 791 return ATA_E_ABORT; 792 } 793 prb = (struct ata_siiprb_command *) 794 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 795 return prb->fis[3]; 796 } 797 798 static u_int32_t 799 ata_siiprb_softreset(device_t dev, int port) 800 { 801 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 802 struct ata_channel *ch = device_get_softc(dev); 803 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work; 804 u_int32_t signature; 805 int offset = ch->unit * 0x2000; 806 807 /* setup the workspace for a soft reset command */ 808 bzero(prb, sizeof(struct ata_siiprb_command)); 809 prb->control = htole16(0x0080); 810 prb->fis[1] = port & 0x0f; 811 812 /* issue soft reset */ 813 if (ata_siiprb_issue_cmd(dev)) 814 return -1; 815 816 ata_udelay(150000); 817 818 /* get possible signature */ 819 prb = (struct ata_siiprb_command *) 820 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 821 signature=prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24); 822 823 /* clear error bits/interrupt */ 824 ATA_IDX_OUTL(ch, ATA_SERROR, 0xffffffff); 825 826 return signature; 827 } 828 829 static void 830 ata_siiprb_reset(device_t dev) 831 { 832 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 833 struct ata_channel *ch = device_get_softc(dev); 834 int offset = ch->unit * 0x2000; 835 u_int32_t status, signature; 836 int timeout; 837 838 /* disable interrupts */ 839 ATA_OUTL(ctlr->r_res2, 0x1014 + offset, 0x000000ff); 840 841 /* reset channel HW */ 842 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001); 843 DELAY(1000); 844 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001); 845 DELAY(10000); 846 847 /* poll for channel ready */ 848 for (timeout = 0; timeout < 1000; timeout++) { 849 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00040000) 850 break; 851 DELAY(1000); 852 } 853 854 if (bootverbose) { 855 if (timeout >= 1000) 856 device_printf(dev, "channel HW reset timeout\n"); 857 else 858 device_printf(dev, "channel HW reset time=%dms\n", timeout); 859 } 860 861 /* reset phy */ 862 if (!ata_sata_phy_reset(dev, -1, 1)) { 863 if (bootverbose) 864 device_printf(dev, "phy reset found no device\n"); 865 ch->devices = 0; 866 goto finish; 867 } 868 869 /* issue soft reset */ 870 signature = ata_siiprb_softreset(dev, ATA_PM); 871 if (bootverbose) 872 device_printf(dev, "SIGNATURE=%08x\n", signature); 873 874 /* figure out whats there */ 875 switch (signature >> 16) { 876 case 0x0000: 877 ch->devices = ATA_ATA_MASTER; 878 break; 879 case 0x9669: 880 ch->devices = ATA_PORTMULTIPLIER; 881 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x2000); /* enable PM support */ 882 //SOS XXX need to clear all PM status and interrupts!!!! 883 ata_pm_identify(dev); 884 break; 885 case 0xeb14: 886 ch->devices = ATA_ATAPI_MASTER; 887 break; 888 default: 889 ch->devices = 0; 890 } 891 if (bootverbose) 892 device_printf(dev, "siiprb_reset devices=%08x\n", ch->devices); 893 894 finish: 895 /* clear interrupt(s) */ 896 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff); 897 898 /* require explicit interrupt ack */ 899 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008); 900 901 /* 64bit mode */ 902 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400); 903 904 /* enable interrupts wanted */ 905 ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff); 906 } 907 908 static void 909 ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 910 { 911 struct ata_dmasetprd_args *args = xsc; 912 struct ata_siiprb_dma_prdentry *prd = args->dmatab; 913 int i; 914 915 if ((args->error = error)) 916 return; 917 918 for (i = 0; i < nsegs; i++) { 919 prd[i].addr = htole64(segs[i].ds_addr); 920 prd[i].count = htole32(segs[i].ds_len); 921 } 922 prd[i - 1].control = htole32(ATA_DMA_EOT); 923 KASSERT(nsegs <= ATA_SIIPRB_DMA_ENTRIES,("too many DMA segment entries\n")); 924 args->nsegs = nsegs; 925 } 926 927 static void 928 ata_siiprb_dmainit(device_t dev) 929 { 930 struct ata_channel *ch = device_get_softc(dev); 931 932 /* note start and stop are not used here */ 933 ch->dma.setprd = ata_siiprb_dmasetprd; 934 ch->dma.max_address = BUS_SPACE_MAXADDR; 935 ch->dma.max_iosize = (ATA_SIIPRB_DMA_ENTRIES - 1) * PAGE_SIZE; 936 ata_dmainit(dev); 937 } 938 939 ATA_DECLARE_DRIVER(ata_sii); 940