1 /*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ata.h" 31 #include <sys/param.h> 32 #include <sys/module.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/ata.h> 36 #include <sys/bus.h> 37 #include <sys/endian.h> 38 #include <sys/malloc.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/sema.h> 42 #include <sys/taskqueue.h> 43 #include <vm/uma.h> 44 #include <machine/stdarg.h> 45 #include <machine/resource.h> 46 #include <machine/bus.h> 47 #include <sys/rman.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/ata/ata-all.h> 51 #include <dev/ata/ata-pci.h> 52 #include <ata_if.h> 53 54 /* local prototypes */ 55 static int ata_cmd_ch_attach(device_t dev); 56 static int ata_cmd_status(device_t dev); 57 static void ata_cmd_setmode(device_t dev, int mode); 58 static int ata_sii_ch_attach(device_t dev); 59 static int ata_sii_ch_detach(device_t dev); 60 static int ata_sii_status(device_t dev); 61 static void ata_sii_reset(device_t dev); 62 static void ata_sii_setmode(device_t dev, int mode); 63 static int ata_siiprb_ch_attach(device_t dev); 64 static int ata_siiprb_ch_detach(device_t dev); 65 static int ata_siiprb_status(device_t dev); 66 static int ata_siiprb_begin_transaction(struct ata_request *request); 67 static int ata_siiprb_end_transaction(struct ata_request *request); 68 static int ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result); 69 static int ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t result); 70 static u_int32_t ata_siiprb_softreset(device_t dev, int port); 71 static void ata_siiprb_reset(device_t dev); 72 static void ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 73 static void ata_siiprb_dmainit(device_t dev); 74 75 /* misc defines */ 76 #define SII_MEMIO 1 77 #define SII_PRBIO 2 78 #define SII_INTR 0x01 79 #define SII_SETCLK 0x02 80 #define SII_BUG 0x04 81 #define SII_4CH 0x08 82 83 84 /* 85 * Silicon Image Inc. (SiI) (former CMD) chipset support functions 86 */ 87 static int 88 ata_sii_probe(device_t dev) 89 { 90 struct ata_pci_controller *ctlr = device_get_softc(dev); 91 static struct ata_chip_id ids[] = 92 {{ ATA_SII3114, 0x00, SII_MEMIO, SII_4CH, ATA_SA150, "3114" }, 93 { ATA_SII3512, 0x02, SII_MEMIO, 0, ATA_SA150, "3512" }, 94 { ATA_SII3112, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" }, 95 { ATA_SII3112_1, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" }, 96 { ATA_SII3512, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3512" }, 97 { ATA_SII3112, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" }, 98 { ATA_SII3112_1, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" }, 99 { ATA_SII3124, 0x00, SII_PRBIO, SII_4CH, ATA_SA300, "3124" }, 100 { ATA_SII3132, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" }, 101 { ATA_SII3132_1, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" }, 102 { ATA_SII3132_2, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" }, 103 { ATA_SII0680, 0x00, SII_MEMIO, SII_SETCLK, ATA_UDMA6, "680" }, 104 { ATA_CMD649, 0x00, 0, SII_INTR, ATA_UDMA5, "(CMD) 649" }, 105 { ATA_CMD648, 0x00, 0, SII_INTR, ATA_UDMA4, "(CMD) 648" }, 106 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "(CMD) 646U2" }, 107 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "(CMD) 646" }, 108 { 0, 0, 0, 0, 0, 0}}; 109 110 if (pci_get_vendor(dev) != ATA_SILICON_IMAGE_ID) 111 return ENXIO; 112 113 if (!(ctlr->chip = ata_match_chip(dev, ids))) 114 return ENXIO; 115 116 ata_set_desc(dev); 117 ctlr->chipinit = ata_sii_chipinit; 118 return (BUS_PROBE_DEFAULT); 119 } 120 121 int 122 ata_sii_chipinit(device_t dev) 123 { 124 struct ata_pci_controller *ctlr = device_get_softc(dev); 125 126 if (ata_setup_interrupt(dev, ata_generic_intr)) 127 return ENXIO; 128 129 switch (ctlr->chip->cfg1) { 130 case SII_PRBIO: 131 ctlr->r_type1 = SYS_RES_MEMORY; 132 ctlr->r_rid1 = PCIR_BAR(0); 133 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 134 &ctlr->r_rid1, RF_ACTIVE))) 135 return ENXIO; 136 137 ctlr->r_rid2 = PCIR_BAR(2); 138 ctlr->r_type2 = SYS_RES_MEMORY; 139 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 140 &ctlr->r_rid2, RF_ACTIVE))){ 141 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1); 142 return ENXIO; 143 } 144 ctlr->ch_attach = ata_siiprb_ch_attach; 145 ctlr->ch_detach = ata_siiprb_ch_detach; 146 ctlr->reset = ata_siiprb_reset; 147 ctlr->setmode = ata_sata_setmode; 148 ctlr->channels = (ctlr->chip->cfg2 == SII_4CH) ? 4 : 2; 149 150 /* reset controller */ 151 ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000); 152 DELAY(10000); 153 ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f); 154 break; 155 156 case SII_MEMIO: 157 ctlr->r_type2 = SYS_RES_MEMORY; 158 ctlr->r_rid2 = PCIR_BAR(5); 159 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 160 &ctlr->r_rid2, RF_ACTIVE))){ 161 if (ctlr->chip->chipid != ATA_SII0680 || 162 (pci_read_config(dev, 0x8a, 1) & 1)) 163 return ENXIO; 164 } 165 166 if (ctlr->chip->cfg2 & SII_SETCLK) { 167 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 168 pci_write_config(dev, 0x8a, 169 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1); 170 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 171 device_printf(dev, "%s could not set ATA133 clock\n", 172 ctlr->chip->text); 173 } 174 175 /* if we have 4 channels enable the second set */ 176 if (ctlr->chip->cfg2 & SII_4CH) { 177 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002); 178 ctlr->channels = 4; 179 } 180 181 /* dont block interrupts from any channel */ 182 pci_write_config(dev, 0x48, 183 (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4); 184 185 /* enable PCI interrupt as BIOS might not */ 186 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1); 187 188 if (ctlr->r_res2) { 189 ctlr->ch_attach = ata_sii_ch_attach; 190 ctlr->ch_detach = ata_sii_ch_detach; 191 } 192 193 if (ctlr->chip->max_dma >= ATA_SA150) { 194 ctlr->reset = ata_sii_reset; 195 ctlr->setmode = ata_sata_setmode; 196 } 197 else 198 ctlr->setmode = ata_sii_setmode; 199 break; 200 201 default: 202 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) { 203 device_printf(dev, "HW has secondary channel disabled\n"); 204 ctlr->channels = 1; 205 } 206 207 /* enable interrupt as BIOS might not */ 208 pci_write_config(dev, 0x71, 0x01, 1); 209 210 ctlr->ch_attach = ata_cmd_ch_attach; 211 ctlr->ch_detach = ata_pci_ch_detach; 212 ctlr->setmode = ata_cmd_setmode; 213 break; 214 } 215 return 0; 216 } 217 218 static int 219 ata_cmd_ch_attach(device_t dev) 220 { 221 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 222 struct ata_channel *ch = device_get_softc(dev); 223 224 /* setup the usual register normal pci style */ 225 if (ata_pci_ch_attach(dev)) 226 return ENXIO; 227 228 if (ctlr->chip->cfg2 & SII_INTR) 229 ch->hw.status = ata_cmd_status; 230 231 return 0; 232 } 233 234 static int 235 ata_cmd_status(device_t dev) 236 { 237 struct ata_channel *ch = device_get_softc(dev); 238 u_int8_t reg71; 239 240 if (((reg71 = pci_read_config(device_get_parent(dev), 0x71, 1)) & 241 (ch->unit ? 0x08 : 0x04))) { 242 pci_write_config(device_get_parent(dev), 0x71, 243 reg71 & ~(ch->unit ? 0x04 : 0x08), 1); 244 return ata_pci_status(dev); 245 } 246 return 0; 247 } 248 249 static void 250 ata_cmd_setmode(device_t dev, int mode) 251 { 252 device_t gparent = GRANDPARENT(dev); 253 struct ata_pci_controller *ctlr = device_get_softc(gparent); 254 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 255 struct ata_device *atadev = device_get_softc(dev); 256 int devno = (ch->unit << 1) + atadev->unit; 257 int error; 258 259 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 260 261 mode = ata_check_80pin(dev, mode); 262 263 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 264 265 if (bootverbose) 266 device_printf(dev, "%ssetting %s on %s chip\n", 267 (error) ? "FAILURE " : "", 268 ata_mode2str(mode), ctlr->chip->text); 269 if (!error) { 270 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7); 271 int ureg = ch->unit ? 0x7b : 0x73; 272 273 if (mode >= ATA_UDMA0) { 274 int udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 }, 275 { 0x11, 0x42 }, { 0x25, 0x8a }, 276 { 0x15, 0x4a }, { 0x05, 0x0a } }; 277 278 u_int8_t umode = pci_read_config(gparent, ureg, 1); 279 280 umode &= ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca); 281 umode |= udmatimings[mode & ATA_MODE_MASK][atadev->unit]; 282 pci_write_config(gparent, ureg, umode, 1); 283 } 284 else if (mode >= ATA_WDMA0) { 285 int dmatimings[] = { 0x87, 0x32, 0x3f }; 286 287 pci_write_config(gparent, treg, dmatimings[mode & ATA_MODE_MASK],1); 288 pci_write_config(gparent, ureg, 289 pci_read_config(gparent, ureg, 1) & 290 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1); 291 } 292 else { 293 int piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f }; 294 pci_write_config(gparent, treg, 295 piotimings[(mode & ATA_MODE_MASK) - ATA_PIO0], 1); 296 pci_write_config(gparent, ureg, 297 pci_read_config(gparent, ureg, 1) & 298 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1); 299 } 300 atadev->mode = mode; 301 } 302 } 303 304 static int 305 ata_sii_ch_attach(device_t dev) 306 { 307 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 308 struct ata_channel *ch = device_get_softc(dev); 309 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2); 310 int i; 311 312 ata_pci_dmainit(dev); 313 314 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 315 ch->r_io[i].res = ctlr->r_res2; 316 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8); 317 } 318 ch->r_io[ATA_CONTROL].res = ctlr->r_res2; 319 ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8); 320 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 321 ata_default_registers(dev); 322 323 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2; 324 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8); 325 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2; 326 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8); 327 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2; 328 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8); 329 330 if (ctlr->chip->max_dma >= ATA_SA150) { 331 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 332 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8); 333 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 334 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8); 335 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 336 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8); 337 ch->flags |= ATA_NO_SLAVE; 338 339 /* enable PHY state change interrupt */ 340 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16)); 341 } 342 343 ch->dma.max_iosize = (ATA_DMA_ENTRIES - 1) * PAGE_SIZE; 344 if (ctlr->chip->cfg2 & SII_BUG) { 345 /* work around errata in early chips */ 346 ch->dma.boundary = 8192; 347 ch->dma.segsize = 15 * DEV_BSIZE; 348 } 349 350 ata_pci_hw(dev); 351 ch->hw.status = ata_sii_status; 352 return 0; 353 } 354 355 static int 356 ata_sii_ch_detach(device_t dev) 357 { 358 359 ata_pci_dmafini(dev); 360 return (0); 361 } 362 363 static int 364 ata_sii_status(device_t dev) 365 { 366 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 367 struct ata_channel *ch = device_get_softc(dev); 368 int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8); 369 int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8); 370 371 /* do we have any PHY events ? */ 372 if (ctlr->chip->max_dma >= ATA_SA150 && 373 (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010)) 374 ata_sata_phy_check_events(dev); 375 376 if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800) 377 return ata_pci_status(dev); 378 else 379 return 0; 380 } 381 382 static void 383 ata_sii_reset(device_t dev) 384 { 385 if (ata_sata_phy_reset(dev, -1, 1)) 386 ata_generic_reset(dev); 387 } 388 389 static void 390 ata_sii_setmode(device_t dev, int mode) 391 { 392 device_t gparent = GRANDPARENT(dev); 393 struct ata_pci_controller *ctlr = device_get_softc(gparent); 394 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 395 struct ata_device *atadev = device_get_softc(dev); 396 int rego = (ch->unit << 4) + (atadev->unit << 1); 397 int mreg = ch->unit ? 0x84 : 0x80; 398 int mask = 0x03 << (atadev->unit << 2); 399 int mval = pci_read_config(gparent, mreg, 1) & ~mask; 400 int error; 401 402 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 403 404 if (ctlr->chip->cfg2 & SII_SETCLK) { 405 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x79, 1) & 406 (ch->unit ? 0x02 : 0x01))) { 407 ata_print_cable(dev, "controller"); 408 mode = ATA_UDMA2; 409 } 410 } 411 else 412 mode = ata_check_80pin(dev, mode); 413 414 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 415 416 if (bootverbose) 417 device_printf(dev, "%ssetting %s on %s chip\n", 418 (error) ? "FAILURE " : "", 419 ata_mode2str(mode), ctlr->chip->text); 420 if (error) 421 return; 422 423 if (mode >= ATA_UDMA0) { 424 u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 }; 425 u_int8_t ureg = 0xac + rego; 426 427 pci_write_config(gparent, mreg, 428 mval | (0x03 << (atadev->unit << 2)), 1); 429 pci_write_config(gparent, ureg, 430 (pci_read_config(gparent, ureg, 1) & ~0x3f) | 431 udmatimings[mode & ATA_MODE_MASK], 1); 432 433 } 434 else if (mode >= ATA_WDMA0) { 435 u_int8_t dreg = 0xa8 + rego; 436 u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 }; 437 438 pci_write_config(gparent, mreg, 439 mval | (0x02 << (atadev->unit << 2)), 1); 440 pci_write_config(gparent, dreg, dmatimings[mode & ATA_MODE_MASK], 2); 441 442 } 443 else { 444 u_int8_t preg = 0xa4 + rego; 445 u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 446 447 pci_write_config(gparent, mreg, 448 mval | (0x01 << (atadev->unit << 2)), 1); 449 pci_write_config(gparent, preg, piotimings[mode & ATA_MODE_MASK], 2); 450 } 451 atadev->mode = mode; 452 } 453 454 455 struct ata_siiprb_dma_prdentry { 456 u_int64_t addr; 457 u_int32_t count; 458 u_int32_t control; 459 } __packed; 460 461 #define ATA_SIIPRB_DMA_ENTRIES 129 462 struct ata_siiprb_ata_command { 463 struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES]; 464 } __packed; 465 466 struct ata_siiprb_atapi_command { 467 u_int8_t ccb[16]; 468 struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES]; 469 } __packed; 470 471 struct ata_siiprb_command { 472 u_int16_t control; 473 u_int16_t protocol_override; 474 u_int32_t transfer_count; 475 u_int8_t fis[24]; 476 union { 477 struct ata_siiprb_ata_command ata; 478 struct ata_siiprb_atapi_command atapi; 479 } u; 480 } __packed; 481 482 static int 483 ata_siiprb_ch_attach(device_t dev) 484 { 485 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 486 struct ata_channel *ch = device_get_softc(dev); 487 int offset = ch->unit * 0x2000; 488 489 ata_siiprb_dmainit(dev); 490 491 /* set the SATA resources */ 492 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 493 ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset; 494 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 495 ch->r_io[ATA_SERROR].offset = 0x1f08 + offset; 496 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 497 ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset; 498 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2; 499 ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset; 500 501 ch->hw.status = ata_siiprb_status; 502 ch->hw.begin_transaction = ata_siiprb_begin_transaction; 503 ch->hw.end_transaction = ata_siiprb_end_transaction; 504 ch->hw.command = NULL; /* not used here */ 505 ch->hw.softreset = ata_siiprb_softreset; 506 ch->hw.pm_read = ata_siiprb_pm_read; 507 ch->hw.pm_write = ata_siiprb_pm_write; 508 509 return 0; 510 } 511 512 static int 513 ata_siiprb_ch_detach(device_t dev) 514 { 515 516 ata_dmafini(dev); 517 return 0; 518 } 519 520 static int 521 ata_siiprb_status(device_t dev) 522 { 523 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 524 struct ata_channel *ch = device_get_softc(dev); 525 u_int32_t action = ATA_INL(ctlr->r_res1, 0x0044); 526 int offset = ch->unit * 0x2000; 527 528 if (action & (1 << ch->unit)) { 529 u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset); 530 531 /* do we have any PHY events ? */ 532 ata_sata_phy_check_events(dev); 533 534 /* clear interrupt(s) */ 535 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus); 536 537 /* do we have any device action ? */ 538 return (istatus & 0x00000003); 539 } 540 return 0; 541 } 542 543 static int 544 ata_siiprb_begin_transaction(struct ata_request *request) 545 { 546 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 547 struct ata_channel *ch = device_get_softc(request->parent); 548 struct ata_siiprb_command *prb; 549 struct ata_siiprb_dma_prdentry *prd; 550 int offset = ch->unit * 0x2000; 551 u_int64_t prb_bus; 552 553 /* SOS XXX */ 554 if (request->u.ata.command == ATA_DEVICE_RESET) { 555 request->result = 0; 556 return ATA_OP_FINISHED; 557 } 558 559 /* get a piece of the workspace for this request */ 560 prb = (struct ata_siiprb_command *)ch->dma.work; 561 562 /* clear the prb structure */ 563 bzero(prb, sizeof(struct ata_siiprb_command)); 564 565 /* setup the FIS for this request */ 566 if (!ata_request2fis_h2d(request, &prb->fis[0])) { 567 device_printf(request->parent, "setting up SATA FIS failed\n"); 568 request->result = EIO; 569 return ATA_OP_FINISHED; 570 } 571 572 /* setup transfer type */ 573 if (request->flags & ATA_R_ATAPI) { 574 bcopy(request->u.atapi.ccb, prb->u.atapi.ccb, 16); 575 if (request->flags & ATA_R_ATAPI16) 576 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000020); 577 else 578 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000020); 579 if (request->flags & ATA_R_READ) 580 prb->control = htole16(0x0010); 581 if (request->flags & ATA_R_WRITE) 582 prb->control = htole16(0x0020); 583 prd = &prb->u.atapi.prd[0]; 584 } 585 else 586 prd = &prb->u.ata.prd[0]; 587 588 /* if request moves data setup and load SG list */ 589 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 590 if (ch->dma.load(request, prd, NULL)) { 591 device_printf(request->parent, "setting up DMA failed\n"); 592 request->result = EIO; 593 return ATA_OP_FINISHED; 594 } 595 } 596 597 /* activate the prb */ 598 prb_bus = ch->dma.work_bus; 599 ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus); 600 ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus>>32); 601 602 /* start the timeout */ 603 callout_reset(&request->callout, request->timeout * hz, 604 (timeout_t*)ata_timeout, request); 605 return ATA_OP_CONTINUES; 606 } 607 608 static int 609 ata_siiprb_end_transaction(struct ata_request *request) 610 { 611 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 612 struct ata_channel *ch = device_get_softc(request->parent); 613 struct ata_siiprb_command *prb; 614 int offset = ch->unit * 0x2000; 615 int error, timeout; 616 617 /* kill the timeout */ 618 callout_stop(&request->callout); 619 620 prb = (struct ata_siiprb_command *) 621 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 622 623 /* any controller errors flagged ? */ 624 if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) { 625 if (bootverbose) 626 printf("ata_siiprb_end_transaction %s error=%08x\n", 627 ata_cmd2str(request), error); 628 629 /* if device error status get details */ 630 if (error == 1 || error == 2) { 631 request->status = prb->fis[2]; 632 if (request->status & ATA_S_ERROR) 633 request->error = prb->fis[3]; 634 } 635 636 /* SOS XXX handle other controller errors here */ 637 638 /* initialize port */ 639 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000004); 640 641 /* poll for port ready */ 642 for (timeout = 0; timeout < 1000; timeout++) { 643 DELAY(1000); 644 if (ATA_INL(ctlr->r_res2, 0x1008 + offset) & 0x00040000) 645 break; 646 } 647 if (bootverbose) { 648 if (timeout >= 1000) 649 device_printf(ch->dev, "port initialize timeout\n"); 650 else 651 device_printf(ch->dev, "port initialize time=%dms\n", timeout); 652 } 653 } 654 655 /* on control commands read back registers to the request struct */ 656 if (request->flags & ATA_R_CONTROL) { 657 request->u.ata.count = prb->fis[12] | ((u_int16_t)prb->fis[13] << 8); 658 request->u.ata.lba = prb->fis[4] | ((u_int64_t)prb->fis[5] << 8) | 659 ((u_int64_t)prb->fis[6] << 16); 660 if (request->flags & ATA_R_48BIT) 661 request->u.ata.lba |= ((u_int64_t)prb->fis[8] << 24) | 662 ((u_int64_t)prb->fis[9] << 32) | 663 ((u_int64_t)prb->fis[10] << 40); 664 else 665 request->u.ata.lba |= ((u_int64_t)(prb->fis[7] & 0x0f) << 24); 666 } 667 668 /* update progress */ 669 if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) { 670 if (request->flags & ATA_R_READ) 671 request->donecount = prb->transfer_count; 672 else 673 request->donecount = request->bytecount; 674 } 675 676 /* release SG list etc */ 677 ch->dma.unload(request); 678 679 return ATA_OP_FINISHED; 680 } 681 682 static int 683 ata_siiprb_issue_cmd(device_t dev) 684 { 685 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 686 struct ata_channel *ch = device_get_softc(dev); 687 u_int64_t prb_bus = ch->dma.work_bus; 688 u_int32_t status; 689 int offset = ch->unit * 0x2000; 690 int timeout; 691 692 /* issue command to chip */ 693 ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus); 694 ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus >> 32); 695 696 /* poll for command finished */ 697 for (timeout = 0; timeout < 10000; timeout++) { 698 DELAY(1000); 699 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000) 700 break; 701 } 702 // SOS XXX ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x00010000); 703 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x08ff08ff); 704 705 if (timeout >= 1000) 706 return EIO; 707 708 if (bootverbose) 709 device_printf(dev, "siiprb_issue_cmd time=%dms status=%08x\n", 710 timeout, status); 711 return 0; 712 } 713 714 static int 715 ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result) 716 { 717 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 718 struct ata_channel *ch = device_get_softc(dev); 719 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work; 720 int offset = ch->unit * 0x2000; 721 722 bzero(prb, sizeof(struct ata_siiprb_command)); 723 prb->fis[0] = 0x27; /* host to device */ 724 prb->fis[1] = 0x8f; /* command FIS to PM port */ 725 prb->fis[2] = ATA_READ_PM; 726 prb->fis[3] = reg; 727 prb->fis[7] = port; 728 if (ata_siiprb_issue_cmd(dev)) { 729 device_printf(dev, "error reading PM port\n"); 730 return EIO; 731 } 732 prb = (struct ata_siiprb_command *) 733 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 734 *result = prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24); 735 return 0; 736 } 737 738 static int 739 ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t value) 740 { 741 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 742 struct ata_channel *ch = device_get_softc(dev); 743 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work; 744 int offset = ch->unit * 0x2000; 745 746 bzero(prb, sizeof(struct ata_siiprb_command)); 747 prb->fis[0] = 0x27; /* host to device */ 748 prb->fis[1] = 0x8f; /* command FIS to PM port */ 749 prb->fis[2] = ATA_WRITE_PM; 750 prb->fis[3] = reg; 751 prb->fis[7] = port; 752 prb->fis[12] = value & 0xff; 753 prb->fis[4] = (value >> 8) & 0xff;; 754 prb->fis[5] = (value >> 16) & 0xff;; 755 prb->fis[6] = (value >> 24) & 0xff;; 756 if (ata_siiprb_issue_cmd(dev)) { 757 device_printf(dev, "error writing PM port\n"); 758 return ATA_E_ABORT; 759 } 760 prb = (struct ata_siiprb_command *) 761 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 762 return prb->fis[3]; 763 } 764 765 static u_int32_t 766 ata_siiprb_softreset(device_t dev, int port) 767 { 768 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 769 struct ata_channel *ch = device_get_softc(dev); 770 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work; 771 u_int32_t signature; 772 int offset = ch->unit * 0x2000; 773 774 /* setup the workspace for a soft reset command */ 775 bzero(prb, sizeof(struct ata_siiprb_command)); 776 prb->control = htole16(0x0080); 777 prb->fis[1] = port & 0x0f; 778 779 /* issue soft reset */ 780 if (ata_siiprb_issue_cmd(dev)) 781 return -1; 782 783 ata_udelay(150000); 784 785 /* get possible signature */ 786 prb = (struct ata_siiprb_command *) 787 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 788 signature=prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24); 789 790 /* clear error bits/interrupt */ 791 ATA_IDX_OUTL(ch, ATA_SERROR, 0xffffffff); 792 793 return signature; 794 } 795 796 static void 797 ata_siiprb_reset(device_t dev) 798 { 799 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 800 struct ata_channel *ch = device_get_softc(dev); 801 int offset = ch->unit * 0x2000; 802 u_int32_t status, signature; 803 int timeout; 804 805 /* disable interrupts */ 806 ATA_OUTL(ctlr->r_res2, 0x1014 + offset, 0x000000ff); 807 808 /* reset channel HW */ 809 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001); 810 DELAY(1000); 811 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001); 812 DELAY(10000); 813 814 /* poll for channel ready */ 815 for (timeout = 0; timeout < 1000; timeout++) { 816 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00040000) 817 break; 818 DELAY(1000); 819 } 820 821 if (bootverbose) { 822 if (timeout >= 1000) 823 device_printf(dev, "channel HW reset timeout\n"); 824 else 825 device_printf(dev, "channel HW reset time=%dms\n", timeout); 826 } 827 828 /* reset phy */ 829 if (!ata_sata_phy_reset(dev, -1, 1)) { 830 if (bootverbose) 831 device_printf(dev, "phy reset found no device\n"); 832 ch->devices = 0; 833 goto finish; 834 } 835 836 /* issue soft reset */ 837 signature = ata_siiprb_softreset(dev, ATA_PM); 838 if (bootverbose) 839 device_printf(dev, "SIGNATURE=%08x\n", signature); 840 841 /* figure out whats there */ 842 switch (signature >> 16) { 843 case 0x0000: 844 ch->devices = ATA_ATA_MASTER; 845 break; 846 case 0x9669: 847 ch->devices = ATA_PORTMULTIPLIER; 848 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x2000); /* enable PM support */ 849 //SOS XXX need to clear all PM status and interrupts!!!! 850 ata_pm_identify(dev); 851 break; 852 case 0xeb14: 853 ch->devices = ATA_ATAPI_MASTER; 854 break; 855 default: 856 ch->devices = 0; 857 } 858 if (bootverbose) 859 device_printf(dev, "siiprb_reset devices=%08x\n", ch->devices); 860 861 finish: 862 /* clear interrupt(s) */ 863 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff); 864 865 /* require explicit interrupt ack */ 866 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008); 867 868 /* 64bit mode */ 869 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400); 870 871 /* enable interrupts wanted */ 872 ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff); 873 } 874 875 static void 876 ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 877 { 878 struct ata_dmasetprd_args *args = xsc; 879 struct ata_siiprb_dma_prdentry *prd = args->dmatab; 880 int i; 881 882 if ((args->error = error)) 883 return; 884 885 for (i = 0; i < nsegs; i++) { 886 prd[i].addr = htole64(segs[i].ds_addr); 887 prd[i].count = htole32(segs[i].ds_len); 888 } 889 prd[i - 1].control = htole32(ATA_DMA_EOT); 890 KASSERT(nsegs <= ATA_SIIPRB_DMA_ENTRIES,("too many DMA segment entries\n")); 891 args->nsegs = nsegs; 892 } 893 894 static void 895 ata_siiprb_dmainit(device_t dev) 896 { 897 struct ata_channel *ch = device_get_softc(dev); 898 899 ata_dmainit(dev); 900 /* note start and stop are not used here */ 901 ch->dma.setprd = ata_siiprb_dmasetprd; 902 ch->dma.max_address = BUS_SPACE_MAXADDR; 903 ch->dma.max_iosize = (ATA_SIIPRB_DMA_ENTRIES - 1) * PAGE_SIZE; 904 } 905 906 ATA_DECLARE_DRIVER(ata_sii); 907