1 /*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ata.h" 31 #include <sys/param.h> 32 #include <sys/module.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/ata.h> 36 #include <sys/bus.h> 37 #include <sys/endian.h> 38 #include <sys/malloc.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/sema.h> 42 #include <sys/taskqueue.h> 43 #include <vm/uma.h> 44 #include <machine/stdarg.h> 45 #include <machine/resource.h> 46 #include <machine/bus.h> 47 #include <sys/rman.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/ata/ata-all.h> 51 #include <dev/ata/ata-pci.h> 52 #include <ata_if.h> 53 54 /* local prototypes */ 55 static int ata_cmd_ch_attach(device_t dev); 56 static int ata_cmd_status(device_t dev); 57 static void ata_cmd_setmode(device_t dev, int mode); 58 static int ata_sii_ch_attach(device_t dev); 59 static int ata_sii_ch_detach(device_t dev); 60 static int ata_sii_status(device_t dev); 61 static void ata_sii_reset(device_t dev); 62 static void ata_sii_setmode(device_t dev, int mode); 63 static int ata_siiprb_ch_attach(device_t dev); 64 static int ata_siiprb_ch_detach(device_t dev); 65 static int ata_siiprb_status(device_t dev); 66 static int ata_siiprb_begin_transaction(struct ata_request *request); 67 static int ata_siiprb_end_transaction(struct ata_request *request); 68 static int ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result); 69 static int ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t result); 70 static u_int32_t ata_siiprb_softreset(device_t dev, int port); 71 static void ata_siiprb_reset(device_t dev); 72 static void ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 73 static void ata_siiprb_dmainit(device_t dev); 74 75 /* misc defines */ 76 #define SII_MEMIO 1 77 #define SII_PRBIO 2 78 #define SII_INTR 0x01 79 #define SII_SETCLK 0x02 80 #define SII_BUG 0x04 81 #define SII_4CH 0x08 82 83 84 /* 85 * Silicon Image Inc. (SiI) (former CMD) chipset support functions 86 */ 87 static int 88 ata_sii_probe(device_t dev) 89 { 90 struct ata_pci_controller *ctlr = device_get_softc(dev); 91 static struct ata_chip_id ids[] = 92 {{ ATA_SII3114, 0x00, SII_MEMIO, SII_4CH, ATA_SA150, "3114" }, 93 { ATA_SII3512, 0x02, SII_MEMIO, 0, ATA_SA150, "3512" }, 94 { ATA_SII3112, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" }, 95 { ATA_SII3112_1, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" }, 96 { ATA_SII3512, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3512" }, 97 { ATA_SII3112, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" }, 98 { ATA_SII3112_1, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" }, 99 { ATA_SII3124, 0x00, SII_PRBIO, SII_4CH, ATA_SA300, "3124" }, 100 { ATA_SII3132, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" }, 101 { ATA_SII3132_1, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" }, 102 { ATA_SII3132_2, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" }, 103 { ATA_SII0680, 0x00, SII_MEMIO, SII_SETCLK, ATA_UDMA6, "680" }, 104 { ATA_CMD649, 0x00, 0, SII_INTR, ATA_UDMA5, "(CMD) 649" }, 105 { ATA_CMD648, 0x00, 0, SII_INTR, ATA_UDMA4, "(CMD) 648" }, 106 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "(CMD) 646U2" }, 107 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "(CMD) 646" }, 108 { 0, 0, 0, 0, 0, 0}}; 109 110 if (pci_get_vendor(dev) != ATA_SILICON_IMAGE_ID) 111 return ENXIO; 112 113 if (!(ctlr->chip = ata_match_chip(dev, ids))) 114 return ENXIO; 115 116 ata_set_desc(dev); 117 ctlr->chipinit = ata_sii_chipinit; 118 return (BUS_PROBE_DEFAULT); 119 } 120 121 int 122 ata_sii_chipinit(device_t dev) 123 { 124 struct ata_pci_controller *ctlr = device_get_softc(dev); 125 126 if (ata_setup_interrupt(dev, ata_generic_intr)) 127 return ENXIO; 128 129 switch (ctlr->chip->cfg1) { 130 case SII_PRBIO: 131 ctlr->r_type1 = SYS_RES_MEMORY; 132 ctlr->r_rid1 = PCIR_BAR(0); 133 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 134 &ctlr->r_rid1, RF_ACTIVE))) 135 return ENXIO; 136 137 ctlr->r_rid2 = PCIR_BAR(2); 138 ctlr->r_type2 = SYS_RES_MEMORY; 139 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 140 &ctlr->r_rid2, RF_ACTIVE))){ 141 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1); 142 return ENXIO; 143 } 144 ctlr->ch_attach = ata_siiprb_ch_attach; 145 ctlr->ch_detach = ata_siiprb_ch_detach; 146 ctlr->reset = ata_siiprb_reset; 147 ctlr->setmode = ata_sata_setmode; 148 ctlr->channels = (ctlr->chip->cfg2 == SII_4CH) ? 4 : 2; 149 150 /* reset controller */ 151 ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000); 152 DELAY(10000); 153 ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f); 154 break; 155 156 case SII_MEMIO: 157 ctlr->r_type2 = SYS_RES_MEMORY; 158 ctlr->r_rid2 = PCIR_BAR(5); 159 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 160 &ctlr->r_rid2, RF_ACTIVE))){ 161 if (ctlr->chip->chipid != ATA_SII0680 || 162 (pci_read_config(dev, 0x8a, 1) & 1)) 163 return ENXIO; 164 } 165 166 if (ctlr->chip->cfg2 & SII_SETCLK) { 167 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 168 pci_write_config(dev, 0x8a, 169 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1); 170 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 171 device_printf(dev, "%s could not set ATA133 clock\n", 172 ctlr->chip->text); 173 } 174 175 /* if we have 4 channels enable the second set */ 176 if (ctlr->chip->cfg2 & SII_4CH) { 177 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002); 178 ctlr->channels = 4; 179 } 180 181 /* dont block interrupts from any channel */ 182 pci_write_config(dev, 0x48, 183 (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4); 184 185 /* enable PCI interrupt as BIOS might not */ 186 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1); 187 188 if (ctlr->r_res2) { 189 ctlr->ch_attach = ata_sii_ch_attach; 190 ctlr->ch_detach = ata_sii_ch_detach; 191 } 192 193 if (ctlr->chip->max_dma >= ATA_SA150) { 194 ctlr->reset = ata_sii_reset; 195 ctlr->setmode = ata_sata_setmode; 196 } 197 else 198 ctlr->setmode = ata_sii_setmode; 199 break; 200 201 default: 202 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) { 203 device_printf(dev, "HW has secondary channel disabled\n"); 204 ctlr->channels = 1; 205 } 206 207 /* enable interrupt as BIOS might not */ 208 pci_write_config(dev, 0x71, 0x01, 1); 209 210 ctlr->ch_attach = ata_cmd_ch_attach; 211 ctlr->ch_detach = ata_pci_ch_detach; 212 ctlr->setmode = ata_cmd_setmode; 213 break; 214 } 215 return 0; 216 } 217 218 static int 219 ata_cmd_ch_attach(device_t dev) 220 { 221 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 222 struct ata_channel *ch = device_get_softc(dev); 223 224 /* setup the usual register normal pci style */ 225 if (ata_pci_ch_attach(dev)) 226 return ENXIO; 227 228 if (ctlr->chip->cfg2 & SII_INTR) 229 ch->hw.status = ata_cmd_status; 230 231 return 0; 232 } 233 234 static int 235 ata_cmd_status(device_t dev) 236 { 237 struct ata_channel *ch = device_get_softc(dev); 238 u_int8_t reg71; 239 240 if (((reg71 = pci_read_config(device_get_parent(dev), 0x71, 1)) & 241 (ch->unit ? 0x08 : 0x04))) { 242 pci_write_config(device_get_parent(dev), 0x71, 243 reg71 & ~(ch->unit ? 0x04 : 0x08), 1); 244 return ata_pci_status(dev); 245 } 246 return 0; 247 } 248 249 static void 250 ata_cmd_setmode(device_t dev, int mode) 251 { 252 device_t gparent = GRANDPARENT(dev); 253 struct ata_pci_controller *ctlr = device_get_softc(gparent); 254 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 255 struct ata_device *atadev = device_get_softc(dev); 256 int devno = (ch->unit << 1) + atadev->unit; 257 int error; 258 259 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 260 261 mode = ata_check_80pin(dev, mode); 262 263 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 264 265 if (bootverbose) 266 device_printf(dev, "%ssetting %s on %s chip\n", 267 (error) ? "FAILURE " : "", 268 ata_mode2str(mode), ctlr->chip->text); 269 if (!error) { 270 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7); 271 int ureg = ch->unit ? 0x7b : 0x73; 272 273 if (mode >= ATA_UDMA0) { 274 int udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 }, 275 { 0x11, 0x42 }, { 0x25, 0x8a }, 276 { 0x15, 0x4a }, { 0x05, 0x0a } }; 277 278 u_int8_t umode = pci_read_config(gparent, ureg, 1); 279 280 umode &= ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca); 281 umode |= udmatimings[mode & ATA_MODE_MASK][atadev->unit]; 282 pci_write_config(gparent, ureg, umode, 1); 283 } 284 else if (mode >= ATA_WDMA0) { 285 int dmatimings[] = { 0x87, 0x32, 0x3f }; 286 287 pci_write_config(gparent, treg, dmatimings[mode & ATA_MODE_MASK],1); 288 pci_write_config(gparent, ureg, 289 pci_read_config(gparent, ureg, 1) & 290 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1); 291 } 292 else { 293 int piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f }; 294 pci_write_config(gparent, treg, 295 piotimings[(mode & ATA_MODE_MASK) - ATA_PIO0], 1); 296 pci_write_config(gparent, ureg, 297 pci_read_config(gparent, ureg, 1) & 298 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1); 299 } 300 atadev->mode = mode; 301 } 302 } 303 304 static int 305 ata_sii_ch_attach(device_t dev) 306 { 307 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 308 struct ata_channel *ch = device_get_softc(dev); 309 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2); 310 int i; 311 312 ata_pci_dmainit(dev); 313 314 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 315 ch->r_io[i].res = ctlr->r_res2; 316 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8); 317 } 318 ch->r_io[ATA_CONTROL].res = ctlr->r_res2; 319 ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8); 320 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 321 ata_default_registers(dev); 322 323 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2; 324 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8); 325 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2; 326 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8); 327 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2; 328 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8); 329 330 if (ctlr->chip->max_dma >= ATA_SA150) { 331 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 332 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8); 333 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 334 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8); 335 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 336 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8); 337 ch->flags |= ATA_NO_SLAVE; 338 339 /* enable PHY state change interrupt */ 340 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16)); 341 } 342 343 if (ctlr->chip->cfg2 & SII_BUG) { 344 /* work around errata in early chips */ 345 ch->dma.boundary = 8192; 346 ch->dma.segsize = 15 * DEV_BSIZE; 347 } 348 349 ata_pci_hw(dev); 350 ch->hw.status = ata_sii_status; 351 return 0; 352 } 353 354 static int 355 ata_sii_ch_detach(device_t dev) 356 { 357 358 ata_pci_dmafini(dev); 359 return (0); 360 } 361 362 static int 363 ata_sii_status(device_t dev) 364 { 365 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 366 struct ata_channel *ch = device_get_softc(dev); 367 int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8); 368 int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8); 369 370 /* do we have any PHY events ? */ 371 if (ctlr->chip->max_dma >= ATA_SA150 && 372 (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010)) 373 ata_sata_phy_check_events(dev); 374 375 if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800) 376 return ata_pci_status(dev); 377 else 378 return 0; 379 } 380 381 static void 382 ata_sii_reset(device_t dev) 383 { 384 if (ata_sata_phy_reset(dev, -1, 1)) 385 ata_generic_reset(dev); 386 } 387 388 static void 389 ata_sii_setmode(device_t dev, int mode) 390 { 391 device_t gparent = GRANDPARENT(dev); 392 struct ata_pci_controller *ctlr = device_get_softc(gparent); 393 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 394 struct ata_device *atadev = device_get_softc(dev); 395 int rego = (ch->unit << 4) + (atadev->unit << 1); 396 int mreg = ch->unit ? 0x84 : 0x80; 397 int mask = 0x03 << (atadev->unit << 2); 398 int mval = pci_read_config(gparent, mreg, 1) & ~mask; 399 int error; 400 401 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 402 403 if (ctlr->chip->cfg2 & SII_SETCLK) { 404 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x79, 1) & 405 (ch->unit ? 0x02 : 0x01))) { 406 ata_print_cable(dev, "controller"); 407 mode = ATA_UDMA2; 408 } 409 } 410 else 411 mode = ata_check_80pin(dev, mode); 412 413 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 414 415 if (bootverbose) 416 device_printf(dev, "%ssetting %s on %s chip\n", 417 (error) ? "FAILURE " : "", 418 ata_mode2str(mode), ctlr->chip->text); 419 if (error) 420 return; 421 422 if (mode >= ATA_UDMA0) { 423 u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 }; 424 u_int8_t ureg = 0xac + rego; 425 426 pci_write_config(gparent, mreg, 427 mval | (0x03 << (atadev->unit << 2)), 1); 428 pci_write_config(gparent, ureg, 429 (pci_read_config(gparent, ureg, 1) & ~0x3f) | 430 udmatimings[mode & ATA_MODE_MASK], 1); 431 432 } 433 else if (mode >= ATA_WDMA0) { 434 u_int8_t dreg = 0xa8 + rego; 435 u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 }; 436 437 pci_write_config(gparent, mreg, 438 mval | (0x02 << (atadev->unit << 2)), 1); 439 pci_write_config(gparent, dreg, dmatimings[mode & ATA_MODE_MASK], 2); 440 441 } 442 else { 443 u_int8_t preg = 0xa4 + rego; 444 u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 445 446 pci_write_config(gparent, mreg, 447 mval | (0x01 << (atadev->unit << 2)), 1); 448 pci_write_config(gparent, preg, piotimings[mode & ATA_MODE_MASK], 2); 449 } 450 atadev->mode = mode; 451 } 452 453 454 struct ata_siiprb_dma_prdentry { 455 u_int64_t addr; 456 u_int32_t count; 457 u_int32_t control; 458 } __packed; 459 460 #define ATA_SIIPRB_DMA_ENTRIES 125 461 struct ata_siiprb_ata_command { 462 struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES]; 463 } __packed; 464 465 struct ata_siiprb_atapi_command { 466 u_int8_t ccb[16]; 467 struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES]; 468 } __packed; 469 470 struct ata_siiprb_command { 471 u_int16_t control; 472 u_int16_t protocol_override; 473 u_int32_t transfer_count; 474 u_int8_t fis[24]; 475 union { 476 struct ata_siiprb_ata_command ata; 477 struct ata_siiprb_atapi_command atapi; 478 } u; 479 } __packed; 480 481 static int 482 ata_siiprb_ch_attach(device_t dev) 483 { 484 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 485 struct ata_channel *ch = device_get_softc(dev); 486 int offset = ch->unit * 0x2000; 487 488 ata_siiprb_dmainit(dev); 489 490 /* set the SATA resources */ 491 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 492 ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset; 493 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 494 ch->r_io[ATA_SERROR].offset = 0x1f08 + offset; 495 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 496 ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset; 497 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2; 498 ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset; 499 500 ch->hw.status = ata_siiprb_status; 501 ch->hw.begin_transaction = ata_siiprb_begin_transaction; 502 ch->hw.end_transaction = ata_siiprb_end_transaction; 503 ch->hw.command = NULL; /* not used here */ 504 ch->hw.softreset = ata_siiprb_softreset; 505 ch->hw.pm_read = ata_siiprb_pm_read; 506 ch->hw.pm_write = ata_siiprb_pm_write; 507 508 return 0; 509 } 510 511 static int 512 ata_siiprb_ch_detach(device_t dev) 513 { 514 515 ata_dmafini(dev); 516 return 0; 517 } 518 519 static int 520 ata_siiprb_status(device_t dev) 521 { 522 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 523 struct ata_channel *ch = device_get_softc(dev); 524 u_int32_t action = ATA_INL(ctlr->r_res1, 0x0044); 525 int offset = ch->unit * 0x2000; 526 527 if (action & (1 << ch->unit)) { 528 u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset); 529 530 /* do we have any PHY events ? */ 531 ata_sata_phy_check_events(dev); 532 533 /* clear interrupt(s) */ 534 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus); 535 536 /* do we have any device action ? */ 537 return (istatus & 0x00000003); 538 } 539 return 0; 540 } 541 542 static int 543 ata_siiprb_begin_transaction(struct ata_request *request) 544 { 545 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 546 struct ata_channel *ch = device_get_softc(request->parent); 547 struct ata_siiprb_command *prb; 548 struct ata_siiprb_dma_prdentry *prd; 549 int offset = ch->unit * 0x2000; 550 u_int64_t prb_bus; 551 552 /* SOS XXX */ 553 if (request->u.ata.command == ATA_DEVICE_RESET) { 554 request->result = 0; 555 return ATA_OP_FINISHED; 556 } 557 558 /* get a piece of the workspace for this request */ 559 prb = (struct ata_siiprb_command *) 560 (ch->dma.work + (sizeof(struct ata_siiprb_command) * request->tag)); 561 562 /* clear the prb structure */ 563 bzero(prb, sizeof(struct ata_siiprb_command)); 564 565 /* setup the FIS for this request */ 566 if (!ata_request2fis_h2d(request, &prb->fis[0])) { 567 device_printf(request->dev, "setting up SATA FIS failed\n"); 568 request->result = EIO; 569 return ATA_OP_FINISHED; 570 } 571 572 /* setup transfer type */ 573 if (request->flags & ATA_R_ATAPI) { 574 struct ata_device *atadev = device_get_softc(request->dev); 575 576 bcopy(request->u.atapi.ccb, prb->u.atapi.ccb, 16); 577 if ((atadev->param.config & ATA_PROTO_MASK) == ATA_PROTO_ATAPI_12) 578 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000020); 579 else 580 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000020); 581 if (request->flags & ATA_R_READ) 582 prb->control = htole16(0x0010); 583 if (request->flags & ATA_R_WRITE) 584 prb->control = htole16(0x0020); 585 prd = &prb->u.atapi.prd[0]; 586 } 587 else 588 prd = &prb->u.ata.prd[0]; 589 590 /* if request moves data setup and load SG list */ 591 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 592 if (ch->dma.load(request, prd, NULL)) { 593 device_printf(request->dev, "setting up DMA failed\n"); 594 request->result = EIO; 595 return ATA_OP_FINISHED; 596 } 597 } 598 599 /* activate the prb */ 600 prb_bus = ch->dma.work_bus + 601 (sizeof(struct ata_siiprb_command) * request->tag); 602 ATA_OUTL(ctlr->r_res2, 603 0x1c00 + offset + (request->tag * sizeof(u_int64_t)), prb_bus); 604 ATA_OUTL(ctlr->r_res2, 605 0x1c04 + offset + (request->tag * sizeof(u_int64_t)), prb_bus>>32); 606 607 /* start the timeout */ 608 callout_reset(&request->callout, request->timeout * hz, 609 (timeout_t*)ata_timeout, request); 610 return ATA_OP_CONTINUES; 611 } 612 613 static int 614 ata_siiprb_end_transaction(struct ata_request *request) 615 { 616 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 617 struct ata_channel *ch = device_get_softc(request->parent); 618 struct ata_siiprb_command *prb; 619 int offset = ch->unit * 0x2000; 620 int error, timeout; 621 622 /* kill the timeout */ 623 callout_stop(&request->callout); 624 625 prb = (struct ata_siiprb_command *) 626 ((u_int8_t *)rman_get_virtual(ctlr->r_res2)+(request->tag << 7)+offset); 627 628 /* any controller errors flagged ? */ 629 if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) { 630 if (bootverbose) 631 printf("ata_siiprb_end_transaction %s error=%08x\n", 632 ata_cmd2str(request), error); 633 634 /* if device error status get details */ 635 if (error == 1 || error == 2) { 636 request->status = prb->fis[2]; 637 if (request->status & ATA_S_ERROR) 638 request->error = prb->fis[3]; 639 } 640 641 /* SOS XXX handle other controller errors here */ 642 643 /* initialize port */ 644 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000004); 645 646 /* poll for port ready */ 647 for (timeout = 0; timeout < 1000; timeout++) { 648 DELAY(1000); 649 if (ATA_INL(ctlr->r_res2, 0x1008 + offset) & 0x00040000) 650 break; 651 } 652 if (bootverbose) { 653 if (timeout >= 1000) 654 device_printf(ch->dev, "port initialize timeout\n"); 655 else 656 device_printf(ch->dev, "port initialize time=%dms\n", timeout); 657 } 658 } 659 660 /* on control commands read back registers to the request struct */ 661 if (request->flags & ATA_R_CONTROL) { 662 struct ata_device *atadev = device_get_softc(request->dev); 663 664 request->u.ata.count = prb->fis[12] | ((u_int16_t)prb->fis[13] << 8); 665 request->u.ata.lba = prb->fis[4] | ((u_int64_t)prb->fis[5] << 8) | 666 ((u_int64_t)prb->fis[6] << 16); 667 if (atadev->flags & ATA_D_48BIT_ACTIVE) 668 request->u.ata.lba |= ((u_int64_t)prb->fis[8] << 24) | 669 ((u_int64_t)prb->fis[9] << 32) | 670 ((u_int64_t)prb->fis[10] << 40); 671 else 672 request->u.ata.lba |= ((u_int64_t)(prb->fis[7] & 0x0f) << 24); 673 } 674 675 /* update progress */ 676 if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) { 677 if (request->flags & ATA_R_READ) 678 request->donecount = prb->transfer_count; 679 else 680 request->donecount = request->bytecount; 681 } 682 683 /* release SG list etc */ 684 ch->dma.unload(request); 685 686 return ATA_OP_FINISHED; 687 } 688 689 static int 690 ata_siiprb_issue_cmd(device_t dev) 691 { 692 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 693 struct ata_channel *ch = device_get_softc(dev); 694 u_int64_t prb_bus = ch->dma.work_bus; 695 u_int32_t status; 696 int offset = ch->unit * 0x2000; 697 int timeout; 698 699 /* issue command to chip */ 700 ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus); 701 ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus >> 32); 702 703 /* poll for command finished */ 704 for (timeout = 0; timeout < 10000; timeout++) { 705 DELAY(1000); 706 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000) 707 break; 708 } 709 // SOS XXX ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x00010000); 710 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x08ff08ff); 711 712 if (timeout >= 1000) 713 return EIO; 714 715 if (bootverbose) 716 device_printf(dev, "siiprb_issue_cmd time=%dms status=%08x\n", 717 timeout, status); 718 return 0; 719 } 720 721 static int 722 ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result) 723 { 724 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 725 struct ata_channel *ch = device_get_softc(dev); 726 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work; 727 int offset = ch->unit * 0x2000; 728 729 bzero(prb, sizeof(struct ata_siiprb_command)); 730 prb->fis[0] = 0x27; /* host to device */ 731 prb->fis[1] = 0x8f; /* command FIS to PM port */ 732 prb->fis[2] = ATA_READ_PM; 733 prb->fis[3] = reg; 734 prb->fis[7] = port; 735 if (ata_siiprb_issue_cmd(dev)) { 736 device_printf(dev, "error reading PM port\n"); 737 return EIO; 738 } 739 prb = (struct ata_siiprb_command *) 740 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 741 *result = prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24); 742 return 0; 743 } 744 745 static int 746 ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t value) 747 { 748 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 749 struct ata_channel *ch = device_get_softc(dev); 750 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work; 751 int offset = ch->unit * 0x2000; 752 753 bzero(prb, sizeof(struct ata_siiprb_command)); 754 prb->fis[0] = 0x27; /* host to device */ 755 prb->fis[1] = 0x8f; /* command FIS to PM port */ 756 prb->fis[2] = ATA_WRITE_PM; 757 prb->fis[3] = reg; 758 prb->fis[7] = port; 759 prb->fis[12] = value & 0xff; 760 prb->fis[4] = (value >> 8) & 0xff;; 761 prb->fis[5] = (value >> 16) & 0xff;; 762 prb->fis[6] = (value >> 24) & 0xff;; 763 if (ata_siiprb_issue_cmd(dev)) { 764 device_printf(dev, "error writing PM port\n"); 765 return ATA_E_ABORT; 766 } 767 prb = (struct ata_siiprb_command *) 768 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 769 return prb->fis[3]; 770 } 771 772 static u_int32_t 773 ata_siiprb_softreset(device_t dev, int port) 774 { 775 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 776 struct ata_channel *ch = device_get_softc(dev); 777 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work; 778 u_int32_t signature; 779 int offset = ch->unit * 0x2000; 780 781 /* setup the workspace for a soft reset command */ 782 bzero(prb, sizeof(struct ata_siiprb_command)); 783 prb->control = htole16(0x0080); 784 prb->fis[1] = port & 0x0f; 785 786 /* issue soft reset */ 787 if (ata_siiprb_issue_cmd(dev)) 788 return -1; 789 790 ata_udelay(150000); 791 792 /* get possible signature */ 793 prb = (struct ata_siiprb_command *) 794 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 795 signature=prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24); 796 797 /* clear error bits/interrupt */ 798 ATA_IDX_OUTL(ch, ATA_SERROR, 0xffffffff); 799 800 return signature; 801 } 802 803 static void 804 ata_siiprb_reset(device_t dev) 805 { 806 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 807 struct ata_channel *ch = device_get_softc(dev); 808 int offset = ch->unit * 0x2000; 809 u_int32_t status, signature; 810 int timeout; 811 812 /* disable interrupts */ 813 ATA_OUTL(ctlr->r_res2, 0x1014 + offset, 0x000000ff); 814 815 /* reset channel HW */ 816 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001); 817 DELAY(1000); 818 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001); 819 DELAY(10000); 820 821 /* poll for channel ready */ 822 for (timeout = 0; timeout < 1000; timeout++) { 823 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00040000) 824 break; 825 DELAY(1000); 826 } 827 828 if (bootverbose) { 829 if (timeout >= 1000) 830 device_printf(dev, "channel HW reset timeout\n"); 831 else 832 device_printf(dev, "channel HW reset time=%dms\n", timeout); 833 } 834 835 /* reset phy */ 836 if (!ata_sata_phy_reset(dev, -1, 1)) { 837 if (bootverbose) 838 device_printf(dev, "phy reset found no device\n"); 839 ch->devices = 0; 840 goto finish; 841 } 842 843 /* issue soft reset */ 844 signature = ata_siiprb_softreset(dev, ATA_PM); 845 if (bootverbose) 846 device_printf(dev, "SIGNATURE=%08x\n", signature); 847 848 /* figure out whats there */ 849 switch (signature >> 16) { 850 case 0x0000: 851 ch->devices = ATA_ATA_MASTER; 852 break; 853 case 0x9669: 854 ch->devices = ATA_PORTMULTIPLIER; 855 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x2000); /* enable PM support */ 856 //SOS XXX need to clear all PM status and interrupts!!!! 857 ata_pm_identify(dev); 858 break; 859 case 0xeb14: 860 ch->devices = ATA_ATAPI_MASTER; 861 break; 862 default: 863 ch->devices = 0; 864 } 865 if (bootverbose) 866 device_printf(dev, "siiprb_reset devices=%08x\n", ch->devices); 867 868 finish: 869 /* clear interrupt(s) */ 870 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff); 871 872 /* require explicit interrupt ack */ 873 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008); 874 875 /* 64bit mode */ 876 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400); 877 878 /* enable interrupts wanted */ 879 ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff); 880 } 881 882 static void 883 ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 884 { 885 struct ata_dmasetprd_args *args = xsc; 886 struct ata_siiprb_dma_prdentry *prd = args->dmatab; 887 int i; 888 889 if ((args->error = error)) 890 return; 891 892 for (i = 0; i < nsegs; i++) { 893 prd[i].addr = htole64(segs[i].ds_addr); 894 prd[i].count = htole32(segs[i].ds_len); 895 } 896 prd[i - 1].control = htole32(ATA_DMA_EOT); 897 KASSERT(nsegs <= ATA_SIIPRB_DMA_ENTRIES,("too many DMA segment entries\n")); 898 args->nsegs = nsegs; 899 } 900 901 static void 902 ata_siiprb_dmainit(device_t dev) 903 { 904 struct ata_channel *ch = device_get_softc(dev); 905 906 ata_dmainit(dev); 907 /* note start and stop are not used here */ 908 ch->dma.setprd = ata_siiprb_dmasetprd; 909 ch->dma.max_address = BUS_SPACE_MAXADDR; 910 } 911 912 ATA_DECLARE_DRIVER(ata_sii); 913