1 /*- 2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/module.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/ata.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/malloc.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 #include <sys/sema.h> 41 #include <sys/taskqueue.h> 42 #include <vm/uma.h> 43 #include <machine/stdarg.h> 44 #include <machine/resource.h> 45 #include <machine/bus.h> 46 #include <sys/rman.h> 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcireg.h> 49 #include <dev/ata/ata-all.h> 50 #include <dev/ata/ata-pci.h> 51 #include <ata_if.h> 52 53 /* local prototypes */ 54 static int ata_cmd_ch_attach(device_t dev); 55 static int ata_cmd_status(device_t dev); 56 static int ata_cmd_setmode(device_t dev, int target, int mode); 57 static int ata_sii_ch_attach(device_t dev); 58 static int ata_sii_ch_detach(device_t dev); 59 static int ata_sii_status(device_t dev); 60 static void ata_sii_reset(device_t dev); 61 static int ata_sii_setmode(device_t dev, int target, int mode); 62 63 /* misc defines */ 64 #define SII_MEMIO 1 65 #define SII_INTR 0x01 66 #define SII_SETCLK 0x02 67 #define SII_BUG 0x04 68 #define SII_4CH 0x08 69 70 /* 71 * Silicon Image Inc. (SiI) (former CMD) chipset support functions 72 */ 73 static int 74 ata_sii_probe(device_t dev) 75 { 76 struct ata_pci_controller *ctlr = device_get_softc(dev); 77 static const struct ata_chip_id ids[] = 78 {{ ATA_SII3114, 0x00, SII_MEMIO, SII_4CH, ATA_SA150, "3114" }, 79 { ATA_SII3512, 0x02, SII_MEMIO, 0, ATA_SA150, "3512" }, 80 { ATA_SII3112, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" }, 81 { ATA_SII3112_1, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" }, 82 { ATA_SII3512, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3512" }, 83 { ATA_SII3112, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" }, 84 { ATA_SII3112_1, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" }, 85 { ATA_SII0680, 0x00, SII_MEMIO, SII_SETCLK, ATA_UDMA6, "680" }, 86 { ATA_CMD649, 0x00, 0, SII_INTR, ATA_UDMA5, "(CMD) 649" }, 87 { ATA_CMD648, 0x00, 0, SII_INTR, ATA_UDMA4, "(CMD) 648" }, 88 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "(CMD) 646U2" }, 89 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "(CMD) 646" }, 90 { 0, 0, 0, 0, 0, 0}}; 91 92 if (pci_get_vendor(dev) != ATA_SILICON_IMAGE_ID) 93 return ENXIO; 94 95 if (!(ctlr->chip = ata_match_chip(dev, ids))) 96 return ENXIO; 97 98 ata_set_desc(dev); 99 ctlr->chipinit = ata_sii_chipinit; 100 return (BUS_PROBE_LOW_PRIORITY); 101 } 102 103 int 104 ata_sii_chipinit(device_t dev) 105 { 106 struct ata_pci_controller *ctlr = device_get_softc(dev); 107 108 if (ata_setup_interrupt(dev, ata_generic_intr)) 109 return ENXIO; 110 111 switch (ctlr->chip->cfg1) { 112 case SII_MEMIO: 113 ctlr->r_type2 = SYS_RES_MEMORY; 114 ctlr->r_rid2 = PCIR_BAR(5); 115 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 116 &ctlr->r_rid2, RF_ACTIVE))){ 117 if (ctlr->chip->chipid != ATA_SII0680 || 118 (pci_read_config(dev, 0x8a, 1) & 1)) 119 return ENXIO; 120 } 121 122 if (ctlr->chip->cfg2 & SII_SETCLK) { 123 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 124 pci_write_config(dev, 0x8a, 125 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1); 126 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 127 device_printf(dev, "%s could not set ATA133 clock\n", 128 ctlr->chip->text); 129 } 130 131 /* if we have 4 channels enable the second set */ 132 if (ctlr->chip->cfg2 & SII_4CH) { 133 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002); 134 ctlr->channels = 4; 135 } 136 137 /* dont block interrupts from any channel */ 138 pci_write_config(dev, 0x48, 139 (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4); 140 141 /* enable PCI interrupt as BIOS might not */ 142 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1); 143 144 if (ctlr->r_res2) { 145 ctlr->ch_attach = ata_sii_ch_attach; 146 ctlr->ch_detach = ata_sii_ch_detach; 147 } 148 149 if (ctlr->chip->max_dma >= ATA_SA150) { 150 ctlr->reset = ata_sii_reset; 151 ctlr->setmode = ata_sata_setmode; 152 ctlr->getrev = ata_sata_getrev; 153 } 154 else 155 ctlr->setmode = ata_sii_setmode; 156 break; 157 158 default: 159 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) { 160 device_printf(dev, "HW has secondary channel disabled\n"); 161 ctlr->channels = 1; 162 } 163 164 /* enable interrupt as BIOS might not */ 165 pci_write_config(dev, 0x71, 0x01, 1); 166 167 ctlr->ch_attach = ata_cmd_ch_attach; 168 ctlr->ch_detach = ata_pci_ch_detach; 169 ctlr->setmode = ata_cmd_setmode; 170 break; 171 } 172 return 0; 173 } 174 175 static int 176 ata_cmd_ch_attach(device_t dev) 177 { 178 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 179 struct ata_channel *ch = device_get_softc(dev); 180 181 /* setup the usual register normal pci style */ 182 if (ata_pci_ch_attach(dev)) 183 return ENXIO; 184 185 if (ctlr->chip->cfg2 & SII_INTR) 186 ch->hw.status = ata_cmd_status; 187 188 ch->flags |= ATA_NO_ATAPI_DMA; 189 190 return 0; 191 } 192 193 static int 194 ata_cmd_status(device_t dev) 195 { 196 struct ata_channel *ch = device_get_softc(dev); 197 u_int8_t reg71; 198 199 if (((reg71 = pci_read_config(device_get_parent(dev), 0x71, 1)) & 200 (ch->unit ? 0x08 : 0x04))) { 201 pci_write_config(device_get_parent(dev), 0x71, 202 reg71 & ~(ch->unit ? 0x04 : 0x08), 1); 203 return ata_pci_status(dev); 204 } 205 return 0; 206 } 207 208 static int 209 ata_cmd_setmode(device_t dev, int target, int mode) 210 { 211 device_t parent = device_get_parent(dev); 212 struct ata_pci_controller *ctlr = device_get_softc(parent); 213 struct ata_channel *ch = device_get_softc(dev); 214 int devno = (ch->unit << 1) + target; 215 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7); 216 int ureg = ch->unit ? 0x7b : 0x73; 217 int piomode; 218 static const uint8_t piotimings[] = 219 { 0xa9, 0x57, 0x44, 0x32, 0x3f, 0x87, 0x32, 0x3f }; 220 static const uint8_t udmatimings[][2] = 221 { { 0x31, 0xc2 }, { 0x21, 0x82 }, { 0x11, 0x42 }, 222 { 0x25, 0x8a }, { 0x15, 0x4a }, { 0x05, 0x0a } }; 223 224 mode = min(mode, ctlr->chip->max_dma); 225 if (mode >= ATA_UDMA0) { 226 u_int8_t umode = pci_read_config(parent, ureg, 1); 227 228 umode &= ~(target == 0 ? 0x35 : 0xca); 229 umode |= udmatimings[mode & ATA_MODE_MASK][target]; 230 pci_write_config(parent, ureg, umode, 1); 231 piomode = ATA_PIO4; 232 } else { 233 pci_write_config(parent, ureg, 234 pci_read_config(parent, ureg, 1) & 235 ~(target == 0 ? 0x35 : 0xca), 1); 236 piomode = mode; 237 } 238 pci_write_config(parent, treg, piotimings[ata_mode2idx(piomode)], 1); 239 return (mode); 240 } 241 242 static int 243 ata_sii_ch_attach(device_t dev) 244 { 245 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 246 struct ata_channel *ch = device_get_softc(dev); 247 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2); 248 int i; 249 250 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 251 ch->r_io[i].res = ctlr->r_res2; 252 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8); 253 } 254 ch->r_io[ATA_CONTROL].res = ctlr->r_res2; 255 ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8); 256 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 257 ata_default_registers(dev); 258 259 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2; 260 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8); 261 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2; 262 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8); 263 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2; 264 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8); 265 266 if (ctlr->chip->max_dma >= ATA_SA150) { 267 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 268 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8); 269 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 270 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8); 271 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 272 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8); 273 ch->flags |= ATA_NO_SLAVE; 274 ch->flags |= ATA_SATA; 275 ch->flags |= ATA_KNOWN_PRESENCE; 276 277 /* enable PHY state change interrupt */ 278 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16)); 279 } 280 281 if (ctlr->chip->cfg2 & SII_BUG) { 282 /* work around errata in early chips */ 283 ch->dma.boundary = 8192; 284 ch->dma.segsize = 15 * DEV_BSIZE; 285 } 286 287 ata_pci_hw(dev); 288 ch->hw.status = ata_sii_status; 289 if (ctlr->chip->cfg2 & SII_SETCLK) 290 ch->flags |= ATA_CHECKS_CABLE; 291 292 ata_pci_dmainit(dev); 293 294 return 0; 295 } 296 297 static int 298 ata_sii_ch_detach(device_t dev) 299 { 300 301 ata_pci_dmafini(dev); 302 return (0); 303 } 304 305 static int 306 ata_sii_status(device_t dev) 307 { 308 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 309 struct ata_channel *ch = device_get_softc(dev); 310 int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8); 311 int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8); 312 313 /* do we have any PHY events ? */ 314 if (ctlr->chip->max_dma >= ATA_SA150 && 315 (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010)) 316 ata_sata_phy_check_events(dev, -1); 317 318 if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800) 319 return ata_pci_status(dev); 320 else 321 return 0; 322 } 323 324 static void 325 ata_sii_reset(device_t dev) 326 { 327 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 328 struct ata_channel *ch = device_get_softc(dev); 329 int offset = ((ch->unit & 1) << 7) + ((ch->unit & 2) << 8); 330 uint32_t val; 331 332 /* Apply R_ERR on DMA activate FIS errata workaround. */ 333 val = ATA_INL(ctlr->r_res2, 0x14c + offset); 334 if ((val & 0x3) == 0x1) 335 ATA_OUTL(ctlr->r_res2, 0x14c + offset, val & ~0x3); 336 337 if (ata_sata_phy_reset(dev, -1, 1)) 338 ata_generic_reset(dev); 339 else 340 ch->devices = 0; 341 } 342 343 static int 344 ata_sii_setmode(device_t dev, int target, int mode) 345 { 346 device_t parent = device_get_parent(dev); 347 struct ata_pci_controller *ctlr = device_get_softc(parent); 348 struct ata_channel *ch = device_get_softc(dev); 349 int rego = (ch->unit << 4) + (target << 1); 350 int mreg = ch->unit ? 0x84 : 0x80; 351 int mask = 0x03 << (target << 2); 352 int mval = pci_read_config(parent, mreg, 1) & ~mask; 353 int piomode; 354 u_int8_t preg = 0xa4 + rego; 355 u_int8_t dreg = 0xa8 + rego; 356 u_int8_t ureg = 0xac + rego; 357 static const uint16_t piotimings[] = 358 { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 359 static const uint16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 }; 360 static const uint8_t udmatimings[] = 361 { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 }; 362 363 mode = min(mode, ctlr->chip->max_dma); 364 365 if (ctlr->chip->cfg2 & SII_SETCLK) { 366 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 367 (pci_read_config(parent, 0x79, 1) & 368 (ch->unit ? 0x02 : 0x01))) { 369 ata_print_cable(dev, "controller"); 370 mode = ATA_UDMA2; 371 } 372 } 373 if (mode >= ATA_UDMA0) { 374 pci_write_config(parent, mreg, 375 mval | (0x03 << (target << 2)), 1); 376 pci_write_config(parent, ureg, 377 (pci_read_config(parent, ureg, 1) & ~0x3f) | 378 udmatimings[mode & ATA_MODE_MASK], 1); 379 piomode = ATA_PIO4; 380 } else if (mode >= ATA_WDMA0) { 381 pci_write_config(parent, mreg, 382 mval | (0x02 << (target << 2)), 1); 383 pci_write_config(parent, dreg, dmatimings[mode & ATA_MODE_MASK], 2); 384 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 : 385 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4; 386 } else { 387 pci_write_config(parent, mreg, 388 mval | (0x01 << (target << 2)), 1); 389 piomode = mode; 390 } 391 pci_write_config(parent, preg, piotimings[ata_mode2idx(piomode)], 2); 392 return (mode); 393 } 394 395 ATA_DECLARE_DRIVER(ata_sii); 396