1 /*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ata.h" 31 #include <sys/param.h> 32 #include <sys/module.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/ata.h> 36 #include <sys/bus.h> 37 #include <sys/endian.h> 38 #include <sys/malloc.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/sema.h> 42 #include <sys/taskqueue.h> 43 #include <vm/uma.h> 44 #include <machine/stdarg.h> 45 #include <machine/resource.h> 46 #include <machine/bus.h> 47 #include <sys/rman.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/ata/ata-all.h> 51 #include <dev/ata/ata-pci.h> 52 #include <ata_if.h> 53 54 /* local prototypes */ 55 static int ata_cmd_ch_attach(device_t dev); 56 static int ata_cmd_status(device_t dev); 57 static int ata_cmd_setmode(device_t dev, int target, int mode); 58 static int ata_sii_ch_attach(device_t dev); 59 static int ata_sii_ch_detach(device_t dev); 60 static int ata_sii_status(device_t dev); 61 static void ata_sii_reset(device_t dev); 62 static int ata_sii_setmode(device_t dev, int target, int mode); 63 static int ata_siiprb_ch_attach(device_t dev); 64 static int ata_siiprb_ch_detach(device_t dev); 65 static int ata_siiprb_status(device_t dev); 66 static int ata_siiprb_begin_transaction(struct ata_request *request); 67 static int ata_siiprb_end_transaction(struct ata_request *request); 68 static int ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result); 69 static int ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t result); 70 static u_int32_t ata_siiprb_softreset(device_t dev, int port); 71 static void ata_siiprb_reset(device_t dev); 72 static void ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 73 static void ata_siiprb_dmainit(device_t dev); 74 75 /* misc defines */ 76 #define SII_MEMIO 1 77 #define SII_PRBIO 2 78 #define SII_INTR 0x01 79 #define SII_SETCLK 0x02 80 #define SII_BUG 0x04 81 #define SII_4CH 0x08 82 83 84 /* 85 * Silicon Image Inc. (SiI) (former CMD) chipset support functions 86 */ 87 static int 88 ata_sii_probe(device_t dev) 89 { 90 struct ata_pci_controller *ctlr = device_get_softc(dev); 91 static struct ata_chip_id ids[] = 92 {{ ATA_SII3114, 0x00, SII_MEMIO, SII_4CH, ATA_SA150, "3114" }, 93 { ATA_SII3512, 0x02, SII_MEMIO, 0, ATA_SA150, "3512" }, 94 { ATA_SII3112, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" }, 95 { ATA_SII3112_1, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" }, 96 { ATA_SII3512, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3512" }, 97 { ATA_SII3112, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" }, 98 { ATA_SII3112_1, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" }, 99 { ATA_SII3124, 0x00, SII_PRBIO, SII_4CH, ATA_SA300, "3124" }, 100 { ATA_SII3132, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" }, 101 { ATA_SII3132_1, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" }, 102 { ATA_SII3132_2, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" }, 103 { ATA_SII0680, 0x00, SII_MEMIO, SII_SETCLK, ATA_UDMA6, "680" }, 104 { ATA_CMD649, 0x00, 0, SII_INTR, ATA_UDMA5, "(CMD) 649" }, 105 { ATA_CMD648, 0x00, 0, SII_INTR, ATA_UDMA4, "(CMD) 648" }, 106 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "(CMD) 646U2" }, 107 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "(CMD) 646" }, 108 { 0, 0, 0, 0, 0, 0}}; 109 110 if (pci_get_vendor(dev) != ATA_SILICON_IMAGE_ID) 111 return ENXIO; 112 113 if (!(ctlr->chip = ata_match_chip(dev, ids))) 114 return ENXIO; 115 116 ata_set_desc(dev); 117 ctlr->chipinit = ata_sii_chipinit; 118 return (BUS_PROBE_DEFAULT); 119 } 120 121 int 122 ata_sii_chipinit(device_t dev) 123 { 124 struct ata_pci_controller *ctlr = device_get_softc(dev); 125 126 if (ata_setup_interrupt(dev, ata_generic_intr)) 127 return ENXIO; 128 129 switch (ctlr->chip->cfg1) { 130 case SII_PRBIO: 131 ctlr->r_type1 = SYS_RES_MEMORY; 132 ctlr->r_rid1 = PCIR_BAR(0); 133 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 134 &ctlr->r_rid1, RF_ACTIVE))) 135 return ENXIO; 136 137 ctlr->r_rid2 = PCIR_BAR(2); 138 ctlr->r_type2 = SYS_RES_MEMORY; 139 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 140 &ctlr->r_rid2, RF_ACTIVE))){ 141 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1); 142 return ENXIO; 143 } 144 ctlr->ch_attach = ata_siiprb_ch_attach; 145 ctlr->ch_detach = ata_siiprb_ch_detach; 146 ctlr->reset = ata_siiprb_reset; 147 ctlr->setmode = ata_sata_setmode; 148 ctlr->getrev = ata_sata_getrev; 149 ctlr->channels = (ctlr->chip->cfg2 == SII_4CH) ? 4 : 2; 150 151 /* reset controller */ 152 ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000); 153 DELAY(10000); 154 ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f); 155 break; 156 157 case SII_MEMIO: 158 ctlr->r_type2 = SYS_RES_MEMORY; 159 ctlr->r_rid2 = PCIR_BAR(5); 160 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 161 &ctlr->r_rid2, RF_ACTIVE))){ 162 if (ctlr->chip->chipid != ATA_SII0680 || 163 (pci_read_config(dev, 0x8a, 1) & 1)) 164 return ENXIO; 165 } 166 167 if (ctlr->chip->cfg2 & SII_SETCLK) { 168 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 169 pci_write_config(dev, 0x8a, 170 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1); 171 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 172 device_printf(dev, "%s could not set ATA133 clock\n", 173 ctlr->chip->text); 174 } 175 176 /* if we have 4 channels enable the second set */ 177 if (ctlr->chip->cfg2 & SII_4CH) { 178 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002); 179 ctlr->channels = 4; 180 } 181 182 /* dont block interrupts from any channel */ 183 pci_write_config(dev, 0x48, 184 (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4); 185 186 /* enable PCI interrupt as BIOS might not */ 187 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1); 188 189 if (ctlr->r_res2) { 190 ctlr->ch_attach = ata_sii_ch_attach; 191 ctlr->ch_detach = ata_sii_ch_detach; 192 } 193 194 if (ctlr->chip->max_dma >= ATA_SA150) { 195 ctlr->reset = ata_sii_reset; 196 ctlr->setmode = ata_sata_setmode; 197 ctlr->getrev = ata_sata_getrev; 198 } 199 else 200 ctlr->setmode = ata_sii_setmode; 201 break; 202 203 default: 204 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) { 205 device_printf(dev, "HW has secondary channel disabled\n"); 206 ctlr->channels = 1; 207 } 208 209 /* enable interrupt as BIOS might not */ 210 pci_write_config(dev, 0x71, 0x01, 1); 211 212 ctlr->ch_attach = ata_cmd_ch_attach; 213 ctlr->ch_detach = ata_pci_ch_detach; 214 ctlr->setmode = ata_cmd_setmode; 215 break; 216 } 217 return 0; 218 } 219 220 static int 221 ata_cmd_ch_attach(device_t dev) 222 { 223 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 224 struct ata_channel *ch = device_get_softc(dev); 225 226 /* setup the usual register normal pci style */ 227 if (ata_pci_ch_attach(dev)) 228 return ENXIO; 229 230 if (ctlr->chip->cfg2 & SII_INTR) 231 ch->hw.status = ata_cmd_status; 232 233 return 0; 234 } 235 236 static int 237 ata_cmd_status(device_t dev) 238 { 239 struct ata_channel *ch = device_get_softc(dev); 240 u_int8_t reg71; 241 242 if (((reg71 = pci_read_config(device_get_parent(dev), 0x71, 1)) & 243 (ch->unit ? 0x08 : 0x04))) { 244 pci_write_config(device_get_parent(dev), 0x71, 245 reg71 & ~(ch->unit ? 0x04 : 0x08), 1); 246 return ata_pci_status(dev); 247 } 248 return 0; 249 } 250 251 static int 252 ata_cmd_setmode(device_t dev, int target, int mode) 253 { 254 device_t parent = device_get_parent(dev); 255 struct ata_pci_controller *ctlr = device_get_softc(parent); 256 struct ata_channel *ch = device_get_softc(dev); 257 int devno = (ch->unit << 1) + target; 258 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7); 259 int ureg = ch->unit ? 0x7b : 0x73; 260 int piomode; 261 uint8_t piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f, 0x87, 0x32, 0x3f }; 262 uint8_t udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 }, 263 { 0x11, 0x42 }, { 0x25, 0x8a }, 264 { 0x15, 0x4a }, { 0x05, 0x0a } }; 265 266 mode = min(mode, ctlr->chip->max_dma); 267 if (mode >= ATA_UDMA0) { 268 u_int8_t umode = pci_read_config(parent, ureg, 1); 269 270 umode &= ~(target == 0 ? 0x35 : 0xca); 271 umode |= udmatimings[mode & ATA_MODE_MASK][target]; 272 pci_write_config(parent, ureg, umode, 1); 273 piomode = ATA_PIO4; 274 } else { 275 pci_write_config(parent, ureg, 276 pci_read_config(parent, ureg, 1) & 277 ~(target == 0 ? 0x35 : 0xca), 1); 278 piomode = mode; 279 } 280 pci_write_config(parent, treg, piotimings[ata_mode2idx(piomode)], 1); 281 return (mode); 282 } 283 284 static int 285 ata_sii_ch_attach(device_t dev) 286 { 287 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 288 struct ata_channel *ch = device_get_softc(dev); 289 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2); 290 int i; 291 292 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 293 ch->r_io[i].res = ctlr->r_res2; 294 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8); 295 } 296 ch->r_io[ATA_CONTROL].res = ctlr->r_res2; 297 ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8); 298 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 299 ata_default_registers(dev); 300 301 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2; 302 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8); 303 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2; 304 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8); 305 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2; 306 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8); 307 308 if (ctlr->chip->max_dma >= ATA_SA150) { 309 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 310 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8); 311 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 312 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8); 313 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 314 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8); 315 ch->flags |= ATA_NO_SLAVE; 316 ch->flags |= ATA_SATA; 317 ch->flags |= ATA_KNOWN_PRESENCE; 318 319 /* enable PHY state change interrupt */ 320 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16)); 321 } 322 323 if (ctlr->chip->cfg2 & SII_BUG) { 324 /* work around errata in early chips */ 325 ch->dma.boundary = 8192; 326 ch->dma.segsize = 15 * DEV_BSIZE; 327 } 328 329 ata_pci_hw(dev); 330 ch->hw.status = ata_sii_status; 331 if (ctlr->chip->cfg2 & SII_SETCLK) 332 ch->flags |= ATA_CHECKS_CABLE; 333 334 ata_pci_dmainit(dev); 335 336 return 0; 337 } 338 339 static int 340 ata_sii_ch_detach(device_t dev) 341 { 342 343 ata_pci_dmafini(dev); 344 return (0); 345 } 346 347 static int 348 ata_sii_status(device_t dev) 349 { 350 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 351 struct ata_channel *ch = device_get_softc(dev); 352 int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8); 353 int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8); 354 355 /* do we have any PHY events ? */ 356 if (ctlr->chip->max_dma >= ATA_SA150 && 357 (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010)) 358 ata_sata_phy_check_events(dev, -1); 359 360 if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800) 361 return ata_pci_status(dev); 362 else 363 return 0; 364 } 365 366 static void 367 ata_sii_reset(device_t dev) 368 { 369 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 370 struct ata_channel *ch = device_get_softc(dev); 371 int offset = ((ch->unit & 1) << 7) + ((ch->unit & 2) << 8); 372 uint32_t val; 373 374 /* Apply R_ERR on DMA activate FIS errata workaround. */ 375 val = ATA_INL(ctlr->r_res2, 0x14c + offset); 376 if ((val & 0x3) == 0x1) 377 ATA_OUTL(ctlr->r_res2, 0x14c + offset, val & ~0x3); 378 379 if (ata_sata_phy_reset(dev, -1, 1)) 380 ata_generic_reset(dev); 381 else 382 ch->devices = 0; 383 } 384 385 static int 386 ata_sii_setmode(device_t dev, int target, int mode) 387 { 388 device_t parent = device_get_parent(dev); 389 struct ata_pci_controller *ctlr = device_get_softc(parent); 390 struct ata_channel *ch = device_get_softc(dev); 391 int rego = (ch->unit << 4) + (target << 1); 392 int mreg = ch->unit ? 0x84 : 0x80; 393 int mask = 0x03 << (target << 2); 394 int mval = pci_read_config(parent, mreg, 1) & ~mask; 395 int piomode; 396 u_int8_t preg = 0xa4 + rego; 397 u_int8_t dreg = 0xa8 + rego; 398 u_int8_t ureg = 0xac + rego; 399 u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 400 u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 }; 401 u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 }; 402 403 mode = min(mode, ctlr->chip->max_dma); 404 405 if (ctlr->chip->cfg2 & SII_SETCLK) { 406 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 407 (pci_read_config(parent, 0x79, 1) & 408 (ch->unit ? 0x02 : 0x01))) { 409 ata_print_cable(dev, "controller"); 410 mode = ATA_UDMA2; 411 } 412 } 413 if (mode >= ATA_UDMA0) { 414 pci_write_config(parent, mreg, 415 mval | (0x03 << (target << 2)), 1); 416 pci_write_config(parent, ureg, 417 (pci_read_config(parent, ureg, 1) & ~0x3f) | 418 udmatimings[mode & ATA_MODE_MASK], 1); 419 piomode = ATA_PIO4; 420 } else if (mode >= ATA_WDMA0) { 421 pci_write_config(parent, mreg, 422 mval | (0x02 << (target << 2)), 1); 423 pci_write_config(parent, dreg, dmatimings[mode & ATA_MODE_MASK], 2); 424 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 : 425 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4; 426 } else { 427 pci_write_config(parent, mreg, 428 mval | (0x01 << (target << 2)), 1); 429 piomode = mode; 430 } 431 pci_write_config(parent, preg, piotimings[ata_mode2idx(piomode)], 2); 432 return (mode); 433 } 434 435 436 struct ata_siiprb_dma_prdentry { 437 u_int64_t addr; 438 u_int32_t count; 439 u_int32_t control; 440 } __packed; 441 442 #define ATA_SIIPRB_DMA_ENTRIES 129 443 struct ata_siiprb_ata_command { 444 struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES]; 445 } __packed; 446 447 struct ata_siiprb_atapi_command { 448 u_int8_t ccb[16]; 449 struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES]; 450 } __packed; 451 452 struct ata_siiprb_command { 453 u_int16_t control; 454 u_int16_t protocol_override; 455 u_int32_t transfer_count; 456 u_int8_t fis[24]; 457 union { 458 struct ata_siiprb_ata_command ata; 459 struct ata_siiprb_atapi_command atapi; 460 } u; 461 } __packed; 462 463 static int 464 ata_siiprb_ch_attach(device_t dev) 465 { 466 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 467 struct ata_channel *ch = device_get_softc(dev); 468 int offset = ch->unit * 0x2000; 469 470 ata_siiprb_dmainit(dev); 471 472 /* set the SATA resources */ 473 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 474 ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset; 475 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 476 ch->r_io[ATA_SERROR].offset = 0x1f08 + offset; 477 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 478 ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset; 479 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2; 480 ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset; 481 482 ch->hw.status = ata_siiprb_status; 483 ch->hw.begin_transaction = ata_siiprb_begin_transaction; 484 ch->hw.end_transaction = ata_siiprb_end_transaction; 485 ch->hw.command = NULL; /* not used here */ 486 ch->hw.softreset = ata_siiprb_softreset; 487 ch->hw.pm_read = ata_siiprb_pm_read; 488 ch->hw.pm_write = ata_siiprb_pm_write; 489 ch->flags |= ATA_NO_SLAVE; 490 ch->flags |= ATA_SATA; 491 return 0; 492 } 493 494 static int 495 ata_siiprb_ch_detach(device_t dev) 496 { 497 498 ata_dmafini(dev); 499 return 0; 500 } 501 502 static int 503 ata_siiprb_status(device_t dev) 504 { 505 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 506 struct ata_channel *ch = device_get_softc(dev); 507 u_int32_t action = ATA_INL(ctlr->r_res1, 0x0044); 508 int offset = ch->unit * 0x2000; 509 510 if (action & (1 << ch->unit)) { 511 u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset); 512 513 /* do we have any PHY events ? */ 514 ata_sata_phy_check_events(dev, -1); 515 516 /* clear interrupt(s) */ 517 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus); 518 519 /* do we have any device action ? */ 520 return (istatus & 0x00000003); 521 } 522 return 0; 523 } 524 525 static int 526 ata_siiprb_begin_transaction(struct ata_request *request) 527 { 528 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 529 struct ata_channel *ch = device_get_softc(request->parent); 530 struct ata_siiprb_command *prb; 531 struct ata_siiprb_dma_prdentry *prd; 532 int offset = ch->unit * 0x2000; 533 u_int64_t prb_bus; 534 535 /* SOS XXX */ 536 if (request->u.ata.command == ATA_DEVICE_RESET) { 537 request->result = 0; 538 return ATA_OP_FINISHED; 539 } 540 541 /* get a piece of the workspace for this request */ 542 prb = (struct ata_siiprb_command *)ch->dma.work; 543 544 /* clear the prb structure */ 545 bzero(prb, sizeof(struct ata_siiprb_command)); 546 547 /* setup the FIS for this request */ 548 if (!ata_request2fis_h2d(request, &prb->fis[0])) { 549 device_printf(request->parent, "setting up SATA FIS failed\n"); 550 request->result = EIO; 551 return ATA_OP_FINISHED; 552 } 553 554 /* setup transfer type */ 555 if (request->flags & ATA_R_ATAPI) { 556 bcopy(request->u.atapi.ccb, prb->u.atapi.ccb, 16); 557 if (request->flags & ATA_R_ATAPI16) 558 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000020); 559 else 560 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000020); 561 if (request->flags & ATA_R_READ) 562 prb->control = htole16(0x0010); 563 if (request->flags & ATA_R_WRITE) 564 prb->control = htole16(0x0020); 565 prd = &prb->u.atapi.prd[0]; 566 } 567 else 568 prd = &prb->u.ata.prd[0]; 569 570 /* if request moves data setup and load SG list */ 571 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 572 if (ch->dma.load(request, prd, NULL)) { 573 device_printf(request->parent, "setting up DMA failed\n"); 574 request->result = EIO; 575 return ATA_OP_FINISHED; 576 } 577 } 578 579 /* activate the prb */ 580 prb_bus = ch->dma.work_bus; 581 ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus); 582 ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus>>32); 583 584 /* start the timeout */ 585 callout_reset(&request->callout, request->timeout * hz, 586 (timeout_t*)ata_timeout, request); 587 return ATA_OP_CONTINUES; 588 } 589 590 static int 591 ata_siiprb_end_transaction(struct ata_request *request) 592 { 593 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 594 struct ata_channel *ch = device_get_softc(request->parent); 595 struct ata_siiprb_command *prb; 596 int offset = ch->unit * 0x2000; 597 int error, timeout; 598 599 /* kill the timeout */ 600 callout_stop(&request->callout); 601 602 prb = (struct ata_siiprb_command *) 603 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 604 605 /* any controller errors flagged ? */ 606 if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) { 607 if (bootverbose) 608 printf("ata_siiprb_end_transaction %s error=%08x\n", 609 ata_cmd2str(request), error); 610 611 /* if device error status get details */ 612 if (error == 1 || error == 2) { 613 request->status = prb->fis[2]; 614 if (request->status & ATA_S_ERROR) 615 request->error = prb->fis[3]; 616 } 617 618 /* SOS XXX handle other controller errors here */ 619 620 /* initialize port */ 621 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000004); 622 623 /* poll for port ready */ 624 for (timeout = 0; timeout < 1000; timeout++) { 625 DELAY(1000); 626 if (ATA_INL(ctlr->r_res2, 0x1008 + offset) & 0x00040000) 627 break; 628 } 629 if (bootverbose) { 630 if (timeout >= 1000) 631 device_printf(ch->dev, "port initialize timeout\n"); 632 else 633 device_printf(ch->dev, "port initialize time=%dms\n", timeout); 634 } 635 } 636 637 /* on control commands read back registers to the request struct */ 638 if (request->flags & ATA_R_CONTROL) { 639 request->u.ata.count = prb->fis[12] | ((u_int16_t)prb->fis[13] << 8); 640 request->u.ata.lba = prb->fis[4] | ((u_int64_t)prb->fis[5] << 8) | 641 ((u_int64_t)prb->fis[6] << 16); 642 if (request->flags & ATA_R_48BIT) 643 request->u.ata.lba |= ((u_int64_t)prb->fis[8] << 24) | 644 ((u_int64_t)prb->fis[9] << 32) | 645 ((u_int64_t)prb->fis[10] << 40); 646 else 647 request->u.ata.lba |= ((u_int64_t)(prb->fis[7] & 0x0f) << 24); 648 } 649 650 /* update progress */ 651 if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) { 652 if (request->flags & ATA_R_READ) 653 request->donecount = le32toh(prb->transfer_count); 654 else 655 request->donecount = request->bytecount; 656 } 657 658 /* release SG list etc */ 659 ch->dma.unload(request); 660 661 return ATA_OP_FINISHED; 662 } 663 664 static int 665 ata_siiprb_issue_cmd(device_t dev) 666 { 667 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 668 struct ata_channel *ch = device_get_softc(dev); 669 u_int64_t prb_bus = ch->dma.work_bus; 670 u_int32_t status; 671 int offset = ch->unit * 0x2000; 672 int timeout; 673 674 /* issue command to chip */ 675 ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus); 676 ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus >> 32); 677 678 /* poll for command finished */ 679 for (timeout = 0; timeout < 10000; timeout++) { 680 DELAY(1000); 681 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000) 682 break; 683 } 684 // SOS XXX ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x00010000); 685 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x08ff08ff); 686 687 if (timeout >= 1000) 688 return EIO; 689 690 if (bootverbose) 691 device_printf(dev, "siiprb_issue_cmd time=%dms status=%08x\n", 692 timeout, status); 693 return 0; 694 } 695 696 static int 697 ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result) 698 { 699 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 700 struct ata_channel *ch = device_get_softc(dev); 701 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work; 702 int offset = ch->unit * 0x2000; 703 704 if (port < 0) { 705 *result = ATA_IDX_INL(ch, reg); 706 return (0); 707 } 708 if (port < ATA_PM) { 709 switch (reg) { 710 case ATA_SSTATUS: 711 reg = 0; 712 break; 713 case ATA_SERROR: 714 reg = 1; 715 break; 716 case ATA_SCONTROL: 717 reg = 2; 718 break; 719 default: 720 return (EINVAL); 721 } 722 } 723 bzero(prb, sizeof(struct ata_siiprb_command)); 724 prb->fis[0] = 0x27; /* host to device */ 725 prb->fis[1] = 0x8f; /* command FIS to PM port */ 726 prb->fis[2] = ATA_READ_PM; 727 prb->fis[3] = reg; 728 prb->fis[7] = port; 729 if (ata_siiprb_issue_cmd(dev)) { 730 device_printf(dev, "error reading PM port\n"); 731 return EIO; 732 } 733 prb = (struct ata_siiprb_command *) 734 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 735 *result = prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24); 736 return 0; 737 } 738 739 static int 740 ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t value) 741 { 742 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 743 struct ata_channel *ch = device_get_softc(dev); 744 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work; 745 int offset = ch->unit * 0x2000; 746 747 if (port < 0) { 748 ATA_IDX_OUTL(ch, reg, value); 749 return (0); 750 } 751 if (port < ATA_PM) { 752 switch (reg) { 753 case ATA_SSTATUS: 754 reg = 0; 755 break; 756 case ATA_SERROR: 757 reg = 1; 758 break; 759 case ATA_SCONTROL: 760 reg = 2; 761 break; 762 default: 763 return (EINVAL); 764 } 765 } 766 bzero(prb, sizeof(struct ata_siiprb_command)); 767 prb->fis[0] = 0x27; /* host to device */ 768 prb->fis[1] = 0x8f; /* command FIS to PM port */ 769 prb->fis[2] = ATA_WRITE_PM; 770 prb->fis[3] = reg; 771 prb->fis[7] = port; 772 prb->fis[12] = value & 0xff; 773 prb->fis[4] = (value >> 8) & 0xff; 774 prb->fis[5] = (value >> 16) & 0xff; 775 prb->fis[6] = (value >> 24) & 0xff; 776 if (ata_siiprb_issue_cmd(dev)) { 777 device_printf(dev, "error writing PM port\n"); 778 return ATA_E_ABORT; 779 } 780 prb = (struct ata_siiprb_command *) 781 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 782 return prb->fis[3]; 783 } 784 785 static u_int32_t 786 ata_siiprb_softreset(device_t dev, int port) 787 { 788 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 789 struct ata_channel *ch = device_get_softc(dev); 790 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work; 791 u_int32_t signature; 792 int offset = ch->unit * 0x2000; 793 794 /* setup the workspace for a soft reset command */ 795 bzero(prb, sizeof(struct ata_siiprb_command)); 796 prb->control = htole16(0x0080); 797 prb->fis[1] = port & 0x0f; 798 799 /* issue soft reset */ 800 if (ata_siiprb_issue_cmd(dev)) 801 return -1; 802 803 ata_udelay(150000); 804 805 /* get possible signature */ 806 prb = (struct ata_siiprb_command *) 807 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 808 signature=prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24); 809 810 /* clear error bits/interrupt */ 811 ATA_IDX_OUTL(ch, ATA_SERROR, 0xffffffff); 812 813 return signature; 814 } 815 816 static void 817 ata_siiprb_reset(device_t dev) 818 { 819 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 820 struct ata_channel *ch = device_get_softc(dev); 821 int offset = ch->unit * 0x2000; 822 u_int32_t status, signature; 823 int timeout; 824 825 /* disable interrupts */ 826 ATA_OUTL(ctlr->r_res2, 0x1014 + offset, 0x000000ff); 827 828 /* reset channel HW */ 829 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001); 830 DELAY(1000); 831 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001); 832 DELAY(10000); 833 834 /* poll for channel ready */ 835 for (timeout = 0; timeout < 1000; timeout++) { 836 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00040000) 837 break; 838 DELAY(1000); 839 } 840 841 if (bootverbose) { 842 if (timeout >= 1000) 843 device_printf(dev, "channel HW reset timeout\n"); 844 else 845 device_printf(dev, "channel HW reset time=%dms\n", timeout); 846 } 847 848 /* reset phy */ 849 if (!ata_sata_phy_reset(dev, -1, 1)) { 850 if (bootverbose) 851 device_printf(dev, "phy reset found no device\n"); 852 ch->devices = 0; 853 goto finish; 854 } 855 856 /* issue soft reset */ 857 signature = ata_siiprb_softreset(dev, ATA_PM); 858 if (bootverbose) 859 device_printf(dev, "SIGNATURE=%08x\n", signature); 860 861 /* figure out whats there */ 862 switch (signature >> 16) { 863 case 0x0000: 864 ch->devices = ATA_ATA_MASTER; 865 break; 866 case 0x9669: 867 ch->devices = ATA_PORTMULTIPLIER; 868 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x2000); /* enable PM support */ 869 //SOS XXX need to clear all PM status and interrupts!!!! 870 ata_pm_identify(dev); 871 break; 872 case 0xeb14: 873 ch->devices = ATA_ATAPI_MASTER; 874 break; 875 default: 876 ch->devices = 0; 877 } 878 if (bootverbose) 879 device_printf(dev, "siiprb_reset devices=%08x\n", ch->devices); 880 881 finish: 882 /* clear interrupt(s) */ 883 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff); 884 885 /* require explicit interrupt ack */ 886 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008); 887 888 /* 64bit mode */ 889 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400); 890 891 /* enable interrupts wanted */ 892 ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff); 893 } 894 895 static void 896 ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 897 { 898 struct ata_dmasetprd_args *args = xsc; 899 struct ata_siiprb_dma_prdentry *prd = args->dmatab; 900 int i; 901 902 if ((args->error = error)) 903 return; 904 905 for (i = 0; i < nsegs; i++) { 906 prd[i].addr = htole64(segs[i].ds_addr); 907 prd[i].count = htole32(segs[i].ds_len); 908 } 909 prd[i - 1].control = htole32(ATA_DMA_EOT); 910 KASSERT(nsegs <= ATA_SIIPRB_DMA_ENTRIES,("too many DMA segment entries\n")); 911 args->nsegs = nsegs; 912 } 913 914 static void 915 ata_siiprb_dmainit(device_t dev) 916 { 917 struct ata_channel *ch = device_get_softc(dev); 918 919 /* note start and stop are not used here */ 920 ch->dma.setprd = ata_siiprb_dmasetprd; 921 ch->dma.max_address = BUS_SPACE_MAXADDR; 922 ch->dma.max_iosize = (ATA_SIIPRB_DMA_ENTRIES - 1) * PAGE_SIZE; 923 ata_dmainit(dev); 924 } 925 926 ATA_DECLARE_DRIVER(ata_sii); 927