1 /*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ata.h" 31 #include <sys/param.h> 32 #include <sys/module.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/ata.h> 36 #include <sys/bus.h> 37 #include <sys/endian.h> 38 #include <sys/malloc.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/sema.h> 42 #include <sys/taskqueue.h> 43 #include <vm/uma.h> 44 #include <machine/stdarg.h> 45 #include <machine/resource.h> 46 #include <machine/bus.h> 47 #include <sys/rman.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/ata/ata-all.h> 51 #include <dev/ata/ata-pci.h> 52 #include <ata_if.h> 53 54 /* local prototypes */ 55 static int ata_cmd_ch_attach(device_t dev); 56 static int ata_cmd_status(device_t dev); 57 static int ata_cmd_setmode(device_t dev, int target, int mode); 58 static int ata_sii_ch_attach(device_t dev); 59 static int ata_sii_ch_detach(device_t dev); 60 static int ata_sii_status(device_t dev); 61 static void ata_sii_reset(device_t dev); 62 static int ata_sii_setmode(device_t dev, int target, int mode); 63 static int ata_siiprb_ch_attach(device_t dev); 64 static int ata_siiprb_ch_detach(device_t dev); 65 static int ata_siiprb_status(device_t dev); 66 static int ata_siiprb_begin_transaction(struct ata_request *request); 67 static int ata_siiprb_end_transaction(struct ata_request *request); 68 static int ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result); 69 static int ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t result); 70 static u_int32_t ata_siiprb_softreset(device_t dev, int port); 71 static void ata_siiprb_reset(device_t dev); 72 static void ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 73 static void ata_siiprb_dmainit(device_t dev); 74 75 /* misc defines */ 76 #define SII_MEMIO 1 77 #define SII_PRBIO 2 78 #define SII_INTR 0x01 79 #define SII_SETCLK 0x02 80 #define SII_BUG 0x04 81 #define SII_4CH 0x08 82 83 /* 84 * Silicon Image Inc. (SiI) (former CMD) chipset support functions 85 */ 86 static int 87 ata_sii_probe(device_t dev) 88 { 89 struct ata_pci_controller *ctlr = device_get_softc(dev); 90 static struct ata_chip_id ids[] = 91 {{ ATA_SII3114, 0x00, SII_MEMIO, SII_4CH, ATA_SA150, "3114" }, 92 { ATA_SII3512, 0x02, SII_MEMIO, 0, ATA_SA150, "3512" }, 93 { ATA_SII3112, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" }, 94 { ATA_SII3112_1, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" }, 95 { ATA_SII3512, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3512" }, 96 { ATA_SII3112, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" }, 97 { ATA_SII3112_1, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" }, 98 { ATA_SII3124, 0x00, SII_PRBIO, SII_4CH, ATA_SA300, "3124" }, 99 { ATA_SII3132, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" }, 100 { ATA_SII3132_1, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" }, 101 { ATA_SII3132_2, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" }, 102 { ATA_SII0680, 0x00, SII_MEMIO, SII_SETCLK, ATA_UDMA6, "680" }, 103 { ATA_CMD649, 0x00, 0, SII_INTR, ATA_UDMA5, "(CMD) 649" }, 104 { ATA_CMD648, 0x00, 0, SII_INTR, ATA_UDMA4, "(CMD) 648" }, 105 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "(CMD) 646U2" }, 106 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "(CMD) 646" }, 107 { 0, 0, 0, 0, 0, 0}}; 108 109 if (pci_get_vendor(dev) != ATA_SILICON_IMAGE_ID) 110 return ENXIO; 111 112 if (!(ctlr->chip = ata_match_chip(dev, ids))) 113 return ENXIO; 114 115 ata_set_desc(dev); 116 ctlr->chipinit = ata_sii_chipinit; 117 return (BUS_PROBE_DEFAULT); 118 } 119 120 int 121 ata_sii_chipinit(device_t dev) 122 { 123 struct ata_pci_controller *ctlr = device_get_softc(dev); 124 125 if (ata_setup_interrupt(dev, ata_generic_intr)) 126 return ENXIO; 127 128 switch (ctlr->chip->cfg1) { 129 case SII_PRBIO: 130 ctlr->r_type1 = SYS_RES_MEMORY; 131 ctlr->r_rid1 = PCIR_BAR(0); 132 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 133 &ctlr->r_rid1, RF_ACTIVE))) 134 return ENXIO; 135 136 ctlr->r_rid2 = PCIR_BAR(2); 137 ctlr->r_type2 = SYS_RES_MEMORY; 138 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 139 &ctlr->r_rid2, RF_ACTIVE))){ 140 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1); 141 return ENXIO; 142 } 143 #ifdef __sparc64__ 144 if (!bus_space_map(rman_get_bustag(ctlr->r_res2), 145 rman_get_bushandle(ctlr->r_res2), rman_get_size(ctlr->r_res2), 146 BUS_SPACE_MAP_LINEAR, NULL)) { 147 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1, 148 ctlr->r_res1); 149 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, 150 ctlr->r_res2); 151 return (ENXIO); 152 } 153 #endif 154 ctlr->ch_attach = ata_siiprb_ch_attach; 155 ctlr->ch_detach = ata_siiprb_ch_detach; 156 ctlr->reset = ata_siiprb_reset; 157 ctlr->setmode = ata_sata_setmode; 158 ctlr->getrev = ata_sata_getrev; 159 ctlr->channels = (ctlr->chip->cfg2 == SII_4CH) ? 4 : 2; 160 161 /* reset controller */ 162 ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000); 163 DELAY(10000); 164 ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f); 165 break; 166 167 case SII_MEMIO: 168 ctlr->r_type2 = SYS_RES_MEMORY; 169 ctlr->r_rid2 = PCIR_BAR(5); 170 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 171 &ctlr->r_rid2, RF_ACTIVE))){ 172 if (ctlr->chip->chipid != ATA_SII0680 || 173 (pci_read_config(dev, 0x8a, 1) & 1)) 174 return ENXIO; 175 } 176 177 if (ctlr->chip->cfg2 & SII_SETCLK) { 178 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 179 pci_write_config(dev, 0x8a, 180 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1); 181 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 182 device_printf(dev, "%s could not set ATA133 clock\n", 183 ctlr->chip->text); 184 } 185 186 /* if we have 4 channels enable the second set */ 187 if (ctlr->chip->cfg2 & SII_4CH) { 188 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002); 189 ctlr->channels = 4; 190 } 191 192 /* dont block interrupts from any channel */ 193 pci_write_config(dev, 0x48, 194 (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4); 195 196 /* enable PCI interrupt as BIOS might not */ 197 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1); 198 199 if (ctlr->r_res2) { 200 ctlr->ch_attach = ata_sii_ch_attach; 201 ctlr->ch_detach = ata_sii_ch_detach; 202 } 203 204 if (ctlr->chip->max_dma >= ATA_SA150) { 205 ctlr->reset = ata_sii_reset; 206 ctlr->setmode = ata_sata_setmode; 207 ctlr->getrev = ata_sata_getrev; 208 } 209 else 210 ctlr->setmode = ata_sii_setmode; 211 break; 212 213 default: 214 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) { 215 device_printf(dev, "HW has secondary channel disabled\n"); 216 ctlr->channels = 1; 217 } 218 219 /* enable interrupt as BIOS might not */ 220 pci_write_config(dev, 0x71, 0x01, 1); 221 222 ctlr->ch_attach = ata_cmd_ch_attach; 223 ctlr->ch_detach = ata_pci_ch_detach; 224 ctlr->setmode = ata_cmd_setmode; 225 break; 226 } 227 return 0; 228 } 229 230 static int 231 ata_cmd_ch_attach(device_t dev) 232 { 233 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 234 struct ata_channel *ch = device_get_softc(dev); 235 236 /* setup the usual register normal pci style */ 237 if (ata_pci_ch_attach(dev)) 238 return ENXIO; 239 240 if (ctlr->chip->cfg2 & SII_INTR) 241 ch->hw.status = ata_cmd_status; 242 243 return 0; 244 } 245 246 static int 247 ata_cmd_status(device_t dev) 248 { 249 struct ata_channel *ch = device_get_softc(dev); 250 u_int8_t reg71; 251 252 if (((reg71 = pci_read_config(device_get_parent(dev), 0x71, 1)) & 253 (ch->unit ? 0x08 : 0x04))) { 254 pci_write_config(device_get_parent(dev), 0x71, 255 reg71 & ~(ch->unit ? 0x04 : 0x08), 1); 256 return ata_pci_status(dev); 257 } 258 return 0; 259 } 260 261 static int 262 ata_cmd_setmode(device_t dev, int target, int mode) 263 { 264 device_t parent = device_get_parent(dev); 265 struct ata_pci_controller *ctlr = device_get_softc(parent); 266 struct ata_channel *ch = device_get_softc(dev); 267 int devno = (ch->unit << 1) + target; 268 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7); 269 int ureg = ch->unit ? 0x7b : 0x73; 270 int piomode; 271 uint8_t piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f, 0x87, 0x32, 0x3f }; 272 uint8_t udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 }, 273 { 0x11, 0x42 }, { 0x25, 0x8a }, 274 { 0x15, 0x4a }, { 0x05, 0x0a } }; 275 276 mode = min(mode, ctlr->chip->max_dma); 277 if (mode >= ATA_UDMA0) { 278 u_int8_t umode = pci_read_config(parent, ureg, 1); 279 280 umode &= ~(target == 0 ? 0x35 : 0xca); 281 umode |= udmatimings[mode & ATA_MODE_MASK][target]; 282 pci_write_config(parent, ureg, umode, 1); 283 piomode = ATA_PIO4; 284 } else { 285 pci_write_config(parent, ureg, 286 pci_read_config(parent, ureg, 1) & 287 ~(target == 0 ? 0x35 : 0xca), 1); 288 piomode = mode; 289 } 290 pci_write_config(parent, treg, piotimings[ata_mode2idx(piomode)], 1); 291 return (mode); 292 } 293 294 static int 295 ata_sii_ch_attach(device_t dev) 296 { 297 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 298 struct ata_channel *ch = device_get_softc(dev); 299 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2); 300 int i; 301 302 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 303 ch->r_io[i].res = ctlr->r_res2; 304 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8); 305 } 306 ch->r_io[ATA_CONTROL].res = ctlr->r_res2; 307 ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8); 308 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 309 ata_default_registers(dev); 310 311 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2; 312 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8); 313 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2; 314 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8); 315 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2; 316 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8); 317 318 if (ctlr->chip->max_dma >= ATA_SA150) { 319 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 320 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8); 321 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 322 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8); 323 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 324 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8); 325 ch->flags |= ATA_NO_SLAVE; 326 ch->flags |= ATA_SATA; 327 ch->flags |= ATA_KNOWN_PRESENCE; 328 329 /* enable PHY state change interrupt */ 330 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16)); 331 } 332 333 if (ctlr->chip->cfg2 & SII_BUG) { 334 /* work around errata in early chips */ 335 ch->dma.boundary = 8192; 336 ch->dma.segsize = 15 * DEV_BSIZE; 337 } 338 339 ata_pci_hw(dev); 340 ch->hw.status = ata_sii_status; 341 if (ctlr->chip->cfg2 & SII_SETCLK) 342 ch->flags |= ATA_CHECKS_CABLE; 343 344 ata_pci_dmainit(dev); 345 346 return 0; 347 } 348 349 static int 350 ata_sii_ch_detach(device_t dev) 351 { 352 353 ata_pci_dmafini(dev); 354 return (0); 355 } 356 357 static int 358 ata_sii_status(device_t dev) 359 { 360 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 361 struct ata_channel *ch = device_get_softc(dev); 362 int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8); 363 int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8); 364 365 /* do we have any PHY events ? */ 366 if (ctlr->chip->max_dma >= ATA_SA150 && 367 (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010)) 368 ata_sata_phy_check_events(dev, -1); 369 370 if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800) 371 return ata_pci_status(dev); 372 else 373 return 0; 374 } 375 376 static void 377 ata_sii_reset(device_t dev) 378 { 379 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 380 struct ata_channel *ch = device_get_softc(dev); 381 int offset = ((ch->unit & 1) << 7) + ((ch->unit & 2) << 8); 382 uint32_t val; 383 384 /* Apply R_ERR on DMA activate FIS errata workaround. */ 385 val = ATA_INL(ctlr->r_res2, 0x14c + offset); 386 if ((val & 0x3) == 0x1) 387 ATA_OUTL(ctlr->r_res2, 0x14c + offset, val & ~0x3); 388 389 if (ata_sata_phy_reset(dev, -1, 1)) 390 ata_generic_reset(dev); 391 else 392 ch->devices = 0; 393 } 394 395 static int 396 ata_sii_setmode(device_t dev, int target, int mode) 397 { 398 device_t parent = device_get_parent(dev); 399 struct ata_pci_controller *ctlr = device_get_softc(parent); 400 struct ata_channel *ch = device_get_softc(dev); 401 int rego = (ch->unit << 4) + (target << 1); 402 int mreg = ch->unit ? 0x84 : 0x80; 403 int mask = 0x03 << (target << 2); 404 int mval = pci_read_config(parent, mreg, 1) & ~mask; 405 int piomode; 406 u_int8_t preg = 0xa4 + rego; 407 u_int8_t dreg = 0xa8 + rego; 408 u_int8_t ureg = 0xac + rego; 409 u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 410 u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 }; 411 u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 }; 412 413 mode = min(mode, ctlr->chip->max_dma); 414 415 if (ctlr->chip->cfg2 & SII_SETCLK) { 416 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 417 (pci_read_config(parent, 0x79, 1) & 418 (ch->unit ? 0x02 : 0x01))) { 419 ata_print_cable(dev, "controller"); 420 mode = ATA_UDMA2; 421 } 422 } 423 if (mode >= ATA_UDMA0) { 424 pci_write_config(parent, mreg, 425 mval | (0x03 << (target << 2)), 1); 426 pci_write_config(parent, ureg, 427 (pci_read_config(parent, ureg, 1) & ~0x3f) | 428 udmatimings[mode & ATA_MODE_MASK], 1); 429 piomode = ATA_PIO4; 430 } else if (mode >= ATA_WDMA0) { 431 pci_write_config(parent, mreg, 432 mval | (0x02 << (target << 2)), 1); 433 pci_write_config(parent, dreg, dmatimings[mode & ATA_MODE_MASK], 2); 434 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 : 435 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4; 436 } else { 437 pci_write_config(parent, mreg, 438 mval | (0x01 << (target << 2)), 1); 439 piomode = mode; 440 } 441 pci_write_config(parent, preg, piotimings[ata_mode2idx(piomode)], 2); 442 return (mode); 443 } 444 445 struct ata_siiprb_dma_prdentry { 446 u_int64_t addr; 447 u_int32_t count; 448 u_int32_t control; 449 } __packed; 450 451 #define ATA_SIIPRB_DMA_ENTRIES 129 452 struct ata_siiprb_ata_command { 453 struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES]; 454 } __packed; 455 456 struct ata_siiprb_atapi_command { 457 u_int8_t ccb[16]; 458 struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES]; 459 } __packed; 460 461 struct ata_siiprb_command { 462 u_int16_t control; 463 u_int16_t protocol_override; 464 u_int32_t transfer_count; 465 u_int8_t fis[24]; 466 union { 467 struct ata_siiprb_ata_command ata; 468 struct ata_siiprb_atapi_command atapi; 469 } u; 470 } __packed; 471 472 static int 473 ata_siiprb_ch_attach(device_t dev) 474 { 475 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 476 struct ata_channel *ch = device_get_softc(dev); 477 int offset = ch->unit * 0x2000; 478 479 ata_siiprb_dmainit(dev); 480 481 /* set the SATA resources */ 482 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 483 ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset; 484 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 485 ch->r_io[ATA_SERROR].offset = 0x1f08 + offset; 486 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 487 ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset; 488 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2; 489 ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset; 490 491 ch->hw.status = ata_siiprb_status; 492 ch->hw.begin_transaction = ata_siiprb_begin_transaction; 493 ch->hw.end_transaction = ata_siiprb_end_transaction; 494 ch->hw.command = NULL; /* not used here */ 495 ch->hw.softreset = ata_siiprb_softreset; 496 ch->hw.pm_read = ata_siiprb_pm_read; 497 ch->hw.pm_write = ata_siiprb_pm_write; 498 ch->flags |= ATA_NO_SLAVE; 499 ch->flags |= ATA_SATA; 500 return 0; 501 } 502 503 static int 504 ata_siiprb_ch_detach(device_t dev) 505 { 506 struct ata_channel *ch = device_get_softc(dev); 507 508 if (ch->dma.work_tag && ch->dma.work_map) 509 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 510 BUS_DMASYNC_POSTWRITE); 511 ata_dmafini(dev); 512 return 0; 513 } 514 515 static int 516 ata_siiprb_status(device_t dev) 517 { 518 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 519 struct ata_channel *ch = device_get_softc(dev); 520 u_int32_t action = ATA_INL(ctlr->r_res1, 0x0044); 521 int offset = ch->unit * 0x2000; 522 523 if (action & (1 << ch->unit)) { 524 u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset); 525 526 /* do we have any PHY events ? */ 527 ata_sata_phy_check_events(dev, -1); 528 529 /* clear interrupt(s) */ 530 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus); 531 532 /* do we have any device action ? */ 533 return (istatus & 0x00000003); 534 } 535 return 0; 536 } 537 538 static int 539 ata_siiprb_begin_transaction(struct ata_request *request) 540 { 541 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 542 struct ata_channel *ch = device_get_softc(request->parent); 543 struct ata_siiprb_command *prb; 544 struct ata_siiprb_dma_prdentry *prd; 545 int offset = ch->unit * 0x2000; 546 u_int64_t prb_bus; 547 548 /* SOS XXX */ 549 if (request->u.ata.command == ATA_DEVICE_RESET) { 550 request->result = 0; 551 return ATA_OP_FINISHED; 552 } 553 554 /* get a piece of the workspace for this request */ 555 prb = (struct ata_siiprb_command *)ch->dma.work; 556 557 /* clear the prb structure */ 558 bzero(prb, sizeof(struct ata_siiprb_command)); 559 560 /* setup the FIS for this request */ 561 if (!ata_request2fis_h2d(request, &prb->fis[0])) { 562 device_printf(request->parent, "setting up SATA FIS failed\n"); 563 request->result = EIO; 564 return ATA_OP_FINISHED; 565 } 566 567 /* setup transfer type */ 568 if (request->flags & ATA_R_ATAPI) { 569 bcopy(request->u.atapi.ccb, prb->u.atapi.ccb, 16); 570 if (request->flags & ATA_R_ATAPI16) 571 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000020); 572 else 573 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000020); 574 if (request->flags & ATA_R_READ) 575 prb->control = htole16(0x0010); 576 if (request->flags & ATA_R_WRITE) 577 prb->control = htole16(0x0020); 578 prd = &prb->u.atapi.prd[0]; 579 } 580 else 581 prd = &prb->u.ata.prd[0]; 582 583 /* if request moves data setup and load SG list */ 584 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 585 if (ch->dma.load(request, prd, NULL)) { 586 device_printf(request->parent, "setting up DMA failed\n"); 587 request->result = EIO; 588 return ATA_OP_FINISHED; 589 } 590 } 591 592 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_PREWRITE); 593 594 /* activate the prb */ 595 prb_bus = ch->dma.work_bus; 596 ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus); 597 ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus>>32); 598 599 /* start the timeout */ 600 callout_reset(&request->callout, request->timeout * hz, 601 (timeout_t*)ata_timeout, request); 602 return ATA_OP_CONTINUES; 603 } 604 605 static int 606 ata_siiprb_end_transaction(struct ata_request *request) 607 { 608 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 609 struct ata_channel *ch = device_get_softc(request->parent); 610 struct ata_siiprb_command *prb; 611 int offset = ch->unit * 0x2000; 612 int error, timeout; 613 614 /* kill the timeout */ 615 callout_stop(&request->callout); 616 617 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_POSTWRITE); 618 619 prb = (struct ata_siiprb_command *) 620 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 621 622 /* any controller errors flagged ? */ 623 if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) { 624 if (bootverbose) 625 printf("ata_siiprb_end_transaction %s error=%08x\n", 626 ata_cmd2str(request), error); 627 628 /* if device error status get details */ 629 if (error == 1 || error == 2) { 630 request->status = prb->fis[2]; 631 if (request->status & ATA_S_ERROR) 632 request->error = prb->fis[3]; 633 } 634 635 /* SOS XXX handle other controller errors here */ 636 637 /* initialize port */ 638 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000004); 639 640 /* poll for port ready */ 641 for (timeout = 0; timeout < 1000; timeout++) { 642 DELAY(1000); 643 if (ATA_INL(ctlr->r_res2, 0x1008 + offset) & 0x00040000) 644 break; 645 } 646 if (bootverbose) { 647 if (timeout >= 1000) 648 device_printf(ch->dev, "port initialize timeout\n"); 649 else 650 device_printf(ch->dev, "port initialize time=%dms\n", timeout); 651 } 652 } 653 654 /* on control commands read back registers to the request struct */ 655 if (request->flags & ATA_R_CONTROL) { 656 request->u.ata.count = prb->fis[12] | ((u_int16_t)prb->fis[13] << 8); 657 request->u.ata.lba = prb->fis[4] | ((u_int64_t)prb->fis[5] << 8) | 658 ((u_int64_t)prb->fis[6] << 16); 659 if (request->flags & ATA_R_48BIT) 660 request->u.ata.lba |= ((u_int64_t)prb->fis[8] << 24) | 661 ((u_int64_t)prb->fis[9] << 32) | 662 ((u_int64_t)prb->fis[10] << 40); 663 else 664 request->u.ata.lba |= ((u_int64_t)(prb->fis[7] & 0x0f) << 24); 665 } 666 667 /* update progress */ 668 if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) { 669 if (request->flags & ATA_R_READ) 670 request->donecount = le32toh(prb->transfer_count); 671 else 672 request->donecount = request->bytecount; 673 } 674 675 /* release SG list etc */ 676 ch->dma.unload(request); 677 678 return ATA_OP_FINISHED; 679 } 680 681 static int 682 ata_siiprb_issue_cmd(device_t dev) 683 { 684 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 685 struct ata_channel *ch = device_get_softc(dev); 686 u_int64_t prb_bus = ch->dma.work_bus; 687 u_int32_t status; 688 int offset = ch->unit * 0x2000; 689 int timeout; 690 691 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_PREWRITE); 692 693 /* issue command to chip */ 694 ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus); 695 ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus >> 32); 696 697 /* poll for command finished */ 698 for (timeout = 0; timeout < 10000; timeout++) { 699 DELAY(1000); 700 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000) 701 break; 702 } 703 704 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_POSTWRITE); 705 706 // SOS XXX ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x00010000); 707 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x08ff08ff); 708 709 if (timeout >= 1000) 710 return EIO; 711 712 if (bootverbose) 713 device_printf(dev, "siiprb_issue_cmd time=%dms status=%08x\n", 714 timeout, status); 715 return 0; 716 } 717 718 static int 719 ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result) 720 { 721 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 722 struct ata_channel *ch = device_get_softc(dev); 723 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work; 724 int offset = ch->unit * 0x2000; 725 726 if (port < 0) { 727 *result = ATA_IDX_INL(ch, reg); 728 return (0); 729 } 730 if (port < ATA_PM) { 731 switch (reg) { 732 case ATA_SSTATUS: 733 reg = 0; 734 break; 735 case ATA_SERROR: 736 reg = 1; 737 break; 738 case ATA_SCONTROL: 739 reg = 2; 740 break; 741 default: 742 return (EINVAL); 743 } 744 } 745 bzero(prb, sizeof(struct ata_siiprb_command)); 746 prb->fis[0] = 0x27; /* host to device */ 747 prb->fis[1] = 0x8f; /* command FIS to PM port */ 748 prb->fis[2] = ATA_READ_PM; 749 prb->fis[3] = reg; 750 prb->fis[7] = port; 751 if (ata_siiprb_issue_cmd(dev)) { 752 device_printf(dev, "error reading PM port\n"); 753 return EIO; 754 } 755 prb = (struct ata_siiprb_command *) 756 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 757 *result = prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24); 758 return 0; 759 } 760 761 static int 762 ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t value) 763 { 764 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 765 struct ata_channel *ch = device_get_softc(dev); 766 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work; 767 int offset = ch->unit * 0x2000; 768 769 if (port < 0) { 770 ATA_IDX_OUTL(ch, reg, value); 771 return (0); 772 } 773 if (port < ATA_PM) { 774 switch (reg) { 775 case ATA_SSTATUS: 776 reg = 0; 777 break; 778 case ATA_SERROR: 779 reg = 1; 780 break; 781 case ATA_SCONTROL: 782 reg = 2; 783 break; 784 default: 785 return (EINVAL); 786 } 787 } 788 bzero(prb, sizeof(struct ata_siiprb_command)); 789 prb->fis[0] = 0x27; /* host to device */ 790 prb->fis[1] = 0x8f; /* command FIS to PM port */ 791 prb->fis[2] = ATA_WRITE_PM; 792 prb->fis[3] = reg; 793 prb->fis[7] = port; 794 prb->fis[12] = value & 0xff; 795 prb->fis[4] = (value >> 8) & 0xff; 796 prb->fis[5] = (value >> 16) & 0xff; 797 prb->fis[6] = (value >> 24) & 0xff; 798 if (ata_siiprb_issue_cmd(dev)) { 799 device_printf(dev, "error writing PM port\n"); 800 return ATA_E_ABORT; 801 } 802 prb = (struct ata_siiprb_command *) 803 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 804 return prb->fis[3]; 805 } 806 807 static u_int32_t 808 ata_siiprb_softreset(device_t dev, int port) 809 { 810 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 811 struct ata_channel *ch = device_get_softc(dev); 812 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work; 813 u_int32_t signature; 814 int offset = ch->unit * 0x2000; 815 816 /* setup the workspace for a soft reset command */ 817 bzero(prb, sizeof(struct ata_siiprb_command)); 818 prb->control = htole16(0x0080); 819 prb->fis[1] = port & 0x0f; 820 821 /* issue soft reset */ 822 if (ata_siiprb_issue_cmd(dev)) 823 return -1; 824 825 ata_udelay(150000); 826 827 /* get possible signature */ 828 prb = (struct ata_siiprb_command *) 829 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 830 signature=prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24); 831 832 /* clear error bits/interrupt */ 833 ATA_IDX_OUTL(ch, ATA_SERROR, 0xffffffff); 834 835 return signature; 836 } 837 838 static void 839 ata_siiprb_reset(device_t dev) 840 { 841 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 842 struct ata_channel *ch = device_get_softc(dev); 843 int offset = ch->unit * 0x2000; 844 u_int32_t status, signature; 845 int timeout; 846 847 /* disable interrupts */ 848 ATA_OUTL(ctlr->r_res2, 0x1014 + offset, 0x000000ff); 849 850 /* reset channel HW */ 851 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001); 852 DELAY(1000); 853 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001); 854 DELAY(10000); 855 856 /* poll for channel ready */ 857 for (timeout = 0; timeout < 1000; timeout++) { 858 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00040000) 859 break; 860 DELAY(1000); 861 } 862 863 if (bootverbose) { 864 if (timeout >= 1000) 865 device_printf(dev, "channel HW reset timeout\n"); 866 else 867 device_printf(dev, "channel HW reset time=%dms\n", timeout); 868 } 869 870 /* reset phy */ 871 if (!ata_sata_phy_reset(dev, -1, 1)) { 872 if (bootverbose) 873 device_printf(dev, "phy reset found no device\n"); 874 ch->devices = 0; 875 goto finish; 876 } 877 878 /* issue soft reset */ 879 signature = ata_siiprb_softreset(dev, ATA_PM); 880 if (bootverbose) 881 device_printf(dev, "SIGNATURE=%08x\n", signature); 882 883 /* figure out whats there */ 884 switch (signature >> 16) { 885 case 0x0000: 886 ch->devices = ATA_ATA_MASTER; 887 break; 888 case 0x9669: 889 ch->devices = ATA_PORTMULTIPLIER; 890 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x2000); /* enable PM support */ 891 //SOS XXX need to clear all PM status and interrupts!!!! 892 ata_pm_identify(dev); 893 break; 894 case 0xeb14: 895 ch->devices = ATA_ATAPI_MASTER; 896 break; 897 default: 898 ch->devices = 0; 899 } 900 if (bootverbose) 901 device_printf(dev, "siiprb_reset devices=%08x\n", ch->devices); 902 903 finish: 904 /* clear interrupt(s) */ 905 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff); 906 907 /* require explicit interrupt ack */ 908 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008); 909 910 /* 64bit mode */ 911 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400); 912 913 /* enable interrupts wanted */ 914 ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff); 915 } 916 917 static void 918 ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 919 { 920 struct ata_dmasetprd_args *args = xsc; 921 struct ata_siiprb_dma_prdentry *prd = args->dmatab; 922 int i; 923 924 if ((args->error = error)) 925 return; 926 927 for (i = 0; i < nsegs; i++) { 928 prd[i].addr = htole64(segs[i].ds_addr); 929 prd[i].count = htole32(segs[i].ds_len); 930 } 931 prd[i - 1].control = htole32(ATA_DMA_EOT); 932 KASSERT(nsegs <= ATA_SIIPRB_DMA_ENTRIES,("too many DMA segment entries\n")); 933 args->nsegs = nsegs; 934 } 935 936 static void 937 ata_siiprb_dmainit(device_t dev) 938 { 939 struct ata_channel *ch = device_get_softc(dev); 940 941 /* note start and stop are not used here */ 942 ch->dma.setprd = ata_siiprb_dmasetprd; 943 ch->dma.max_address = BUS_SPACE_MAXADDR; 944 ch->dma.max_iosize = (ATA_SIIPRB_DMA_ENTRIES - 1) * PAGE_SIZE; 945 ata_dmainit(dev); 946 } 947 948 ATA_DECLARE_DRIVER(ata_sii); 949