1 /*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ata.h" 31 #include <sys/param.h> 32 #include <sys/module.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/ata.h> 36 #include <sys/bus.h> 37 #include <sys/endian.h> 38 #include <sys/malloc.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/sema.h> 42 #include <sys/taskqueue.h> 43 #include <vm/uma.h> 44 #ifdef __powerpc__ 45 #include <machine/intr_machdep.h> 46 #endif 47 #include <machine/stdarg.h> 48 #include <machine/resource.h> 49 #include <machine/bus.h> 50 #include <sys/rman.h> 51 #include <dev/pci/pcivar.h> 52 #include <dev/pci/pcireg.h> 53 #include <dev/ata/ata-all.h> 54 #include <dev/ata/ata-pci.h> 55 #include <ata_if.h> 56 57 /* local prototypes */ 58 static int ata_serverworks_chipinit(device_t dev); 59 static int ata_serverworks_ch_attach(device_t dev); 60 static int ata_serverworks_ch_detach(device_t dev); 61 static void ata_serverworks_tf_read(struct ata_request *request); 62 static void ata_serverworks_tf_write(struct ata_request *request); 63 static int ata_serverworks_setmode(device_t dev, int target, int mode); 64 #ifdef __powerpc__ 65 static int ata_serverworks_status(device_t dev); 66 #endif 67 68 /* misc defines */ 69 #define SWKS_33 0 70 #define SWKS_66 1 71 #define SWKS_100 2 72 #define SWKS_MIO 3 73 74 75 /* 76 * ServerWorks chipset support functions 77 */ 78 static int 79 ata_serverworks_probe(device_t dev) 80 { 81 struct ata_pci_controller *ctlr = device_get_softc(dev); 82 static struct ata_chip_id ids[] = 83 {{ ATA_ROSB4, 0x00, SWKS_33, 0, ATA_UDMA2, "ROSB4" }, 84 { ATA_CSB5, 0x92, SWKS_100, 0, ATA_UDMA5, "CSB5" }, 85 { ATA_CSB5, 0x00, SWKS_66, 0, ATA_UDMA4, "CSB5" }, 86 { ATA_CSB6, 0x00, SWKS_100, 0, ATA_UDMA5, "CSB6" }, 87 { ATA_CSB6_1, 0x00, SWKS_66, 0, ATA_UDMA4, "CSB6" }, 88 { ATA_HT1000, 0x00, SWKS_100, 0, ATA_UDMA5, "HT1000" }, 89 { ATA_HT1000_S1, 0x00, SWKS_MIO, 4, ATA_SA150, "HT1000" }, 90 { ATA_HT1000_S2, 0x00, SWKS_MIO, 4, ATA_SA150, "HT1000" }, 91 { ATA_K2, 0x00, SWKS_MIO, 4, ATA_SA150, "K2" }, 92 { ATA_FRODO4, 0x00, SWKS_MIO, 4, ATA_SA150, "Frodo4" }, 93 { ATA_FRODO8, 0x00, SWKS_MIO, 8, ATA_SA150, "Frodo8" }, 94 { 0, 0, 0, 0, 0, 0}}; 95 96 if (pci_get_vendor(dev) != ATA_SERVERWORKS_ID) 97 return ENXIO; 98 99 if (!(ctlr->chip = ata_match_chip(dev, ids))) 100 return ENXIO; 101 102 ata_set_desc(dev); 103 ctlr->chipinit = ata_serverworks_chipinit; 104 return (BUS_PROBE_DEFAULT); 105 } 106 107 #ifdef __powerpc__ 108 static int 109 ata_serverworks_status(device_t dev) 110 { 111 struct ata_channel *ch = device_get_softc(dev); 112 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 113 114 /* 115 * Check if this interrupt belongs to our channel. 116 */ 117 if (!(ATA_INL(ctlr->r_res2, 0x1f80) & (1 << ch->unit))) 118 return (0); 119 120 /* 121 * We need to do a 4-byte read on the status reg before the values 122 * will report correctly 123 */ 124 125 ATA_IDX_INL(ch,ATA_STATUS); 126 127 return ata_pci_status(dev); 128 } 129 #endif 130 131 static int 132 ata_serverworks_chipinit(device_t dev) 133 { 134 struct ata_pci_controller *ctlr = device_get_softc(dev); 135 136 if (ata_setup_interrupt(dev, ata_generic_intr)) 137 return ENXIO; 138 139 if (ctlr->chip->cfg1 == SWKS_MIO) { 140 ctlr->r_type2 = SYS_RES_MEMORY; 141 ctlr->r_rid2 = PCIR_BAR(5); 142 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 143 &ctlr->r_rid2, RF_ACTIVE))) 144 return ENXIO; 145 146 ctlr->channels = ctlr->chip->cfg2; 147 ctlr->ch_attach = ata_serverworks_ch_attach; 148 ctlr->ch_detach = ata_serverworks_ch_detach; 149 ctlr->setmode = ata_sata_setmode; 150 ctlr->getrev = ata_sata_getrev; 151 return 0; 152 } 153 else if (ctlr->chip->cfg1 == SWKS_33) { 154 device_t *children; 155 int nchildren, i; 156 157 /* locate the ISA part in the southbridge and enable UDMA33 */ 158 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){ 159 for (i = 0; i < nchildren; i++) { 160 if (pci_get_devid(children[i]) == ATA_ROSB4_ISA) { 161 pci_write_config(children[i], 0x64, 162 (pci_read_config(children[i], 0x64, 4) & 163 ~0x00002000) | 0x00004000, 4); 164 break; 165 } 166 } 167 free(children, M_TEMP); 168 } 169 } 170 else { 171 pci_write_config(dev, 0x5a, 172 (pci_read_config(dev, 0x5a, 1) & ~0x40) | 173 (ctlr->chip->cfg1 == SWKS_100) ? 0x03 : 0x02, 1); 174 } 175 ctlr->setmode = ata_serverworks_setmode; 176 return 0; 177 } 178 179 static int 180 ata_serverworks_ch_attach(device_t dev) 181 { 182 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 183 struct ata_channel *ch = device_get_softc(dev); 184 int ch_offset; 185 int i; 186 187 ata_pci_dmainit(dev); 188 189 ch_offset = ch->unit * 0x100; 190 191 for (i = ATA_DATA; i < ATA_MAX_RES; i++) 192 ch->r_io[i].res = ctlr->r_res2; 193 194 /* setup ATA registers */ 195 ch->r_io[ATA_DATA].offset = ch_offset + 0x00; 196 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x04; 197 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08; 198 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c; 199 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; 200 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14; 201 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18; 202 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1c; 203 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x20; 204 ata_default_registers(dev); 205 206 /* setup DMA registers */ 207 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x30; 208 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x32; 209 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x34; 210 211 /* setup SATA registers */ 212 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x40; 213 ch->r_io[ATA_SERROR].offset = ch_offset + 0x44; 214 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x48; 215 216 ch->flags |= ATA_NO_SLAVE; 217 ch->flags |= ATA_SATA; 218 ata_pci_hw(dev); 219 ch->hw.tf_read = ata_serverworks_tf_read; 220 ch->hw.tf_write = ata_serverworks_tf_write; 221 #ifdef __powerpc__ 222 ch->hw.status = ata_serverworks_status; 223 224 /* Make sure that our interrupt is edge triggered */ 225 powerpc_config_intr(bus_get_resource_start(device_get_parent(dev), 226 SYS_RES_IRQ, 0), INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH); 227 #endif 228 229 if (ctlr->chip->chipid == ATA_K2) { 230 /* 231 * The revision 1 K2 SATA controller has interesting bugs. Patch them. 232 * These magic numbers regulate interrupt delivery in the first few 233 * cases and are pure magic in the last case. 234 * 235 * Values obtained from the Darwin driver. 236 */ 237 238 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, 0x04); 239 ATA_IDX_OUTL(ch, ATA_SERROR, 0xffffffff); 240 ATA_IDX_OUTL(ch, ATA_SCONTROL, 0x00000300); 241 ATA_OUTL(ctlr->r_res2, ch_offset + 0x88, 0); 242 ATA_OUTL(ctlr->r_res2, ch_offset + 0x80, 243 ATA_INL(ctlr->r_res2, ch_offset + 0x80) & ~0x00040000); 244 } 245 246 /* chip does not reliably do 64K DMA transfers */ 247 ch->dma.max_iosize = 64 * DEV_BSIZE; 248 249 return 0; 250 } 251 252 static int 253 ata_serverworks_ch_detach(device_t dev) 254 { 255 256 ata_pci_dmafini(dev); 257 return (0); 258 } 259 260 static void 261 ata_serverworks_tf_read(struct ata_request *request) 262 { 263 struct ata_channel *ch = device_get_softc(request->parent); 264 265 if (request->flags & ATA_R_48BIT) { 266 u_int16_t temp; 267 268 request->u.ata.count = ATA_IDX_INW(ch, ATA_COUNT); 269 temp = ATA_IDX_INW(ch, ATA_SECTOR); 270 request->u.ata.lba = (u_int64_t)(temp & 0x00ff) | 271 ((u_int64_t)(temp & 0xff00) << 24); 272 temp = ATA_IDX_INW(ch, ATA_CYL_LSB); 273 request->u.ata.lba |= ((u_int64_t)(temp & 0x00ff) << 8) | 274 ((u_int64_t)(temp & 0xff00) << 32); 275 temp = ATA_IDX_INW(ch, ATA_CYL_MSB); 276 request->u.ata.lba |= ((u_int64_t)(temp & 0x00ff) << 16) | 277 ((u_int64_t)(temp & 0xff00) << 40); 278 } 279 else { 280 request->u.ata.count = ATA_IDX_INW(ch, ATA_COUNT) & 0x00ff; 281 request->u.ata.lba = (ATA_IDX_INW(ch, ATA_SECTOR) & 0x00ff) | 282 ((ATA_IDX_INW(ch, ATA_CYL_LSB) & 0x00ff) << 8) | 283 ((ATA_IDX_INW(ch, ATA_CYL_MSB) & 0x00ff) << 16) | 284 ((ATA_IDX_INW(ch, ATA_DRIVE) & 0xf) << 24); 285 } 286 } 287 288 static void 289 ata_serverworks_tf_write(struct ata_request *request) 290 { 291 struct ata_channel *ch = device_get_softc(request->parent); 292 #ifndef ATA_CAM 293 struct ata_device *atadev = device_get_softc(request->dev); 294 #endif 295 296 if (request->flags & ATA_R_48BIT) { 297 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature); 298 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count); 299 ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) | 300 (request->u.ata.lba & 0x00ff)); 301 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) | 302 ((request->u.ata.lba >> 8) & 0x00ff)); 303 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) | 304 ((request->u.ata.lba >> 16) & 0x00ff)); 305 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit)); 306 } 307 else { 308 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature); 309 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count); 310 #ifndef ATA_CAM 311 if (atadev->flags & ATA_D_USE_CHS) { 312 int heads, sectors; 313 314 if (atadev->param.atavalid & ATA_FLAG_54_58) { 315 heads = atadev->param.current_heads; 316 sectors = atadev->param.current_sectors; 317 } 318 else { 319 heads = atadev->param.heads; 320 sectors = atadev->param.sectors; 321 } 322 ATA_IDX_OUTW(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1); 323 ATA_IDX_OUTW(ch, ATA_CYL_LSB, 324 (request->u.ata.lba / (sectors * heads))); 325 ATA_IDX_OUTW(ch, ATA_CYL_MSB, 326 (request->u.ata.lba / (sectors * heads)) >> 8); 327 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit) | 328 (((request->u.ata.lba% (sectors * heads)) / 329 sectors) & 0xf)); 330 } 331 else { 332 #endif 333 ATA_IDX_OUTW(ch, ATA_SECTOR, request->u.ata.lba); 334 ATA_IDX_OUTW(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 335 ATA_IDX_OUTW(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 336 ATA_IDX_OUTW(ch, ATA_DRIVE, 337 ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) | 338 ((request->u.ata.lba >> 24) & 0x0f)); 339 #ifndef ATA_CAM 340 } 341 #endif 342 } 343 } 344 345 static int 346 ata_serverworks_setmode(device_t dev, int target, int mode) 347 { 348 device_t parent = device_get_parent(dev); 349 struct ata_pci_controller *ctlr = device_get_softc(parent); 350 struct ata_channel *ch = device_get_softc(dev); 351 int devno = (ch->unit << 1) + target; 352 int offset = (devno ^ 0x01) << 3; 353 int piomode; 354 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 }; 355 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 }; 356 357 mode = min(mode, ctlr->chip->max_dma); 358 if (mode >= ATA_UDMA0) { 359 /* Set UDMA mode, enable UDMA, set WDMA2/PIO4 */ 360 pci_write_config(parent, 0x56, 361 (pci_read_config(parent, 0x56, 2) & 362 ~(0xf << (devno << 2))) | 363 ((mode & ATA_MODE_MASK) << (devno << 2)), 2); 364 pci_write_config(parent, 0x54, 365 pci_read_config(parent, 0x54, 1) | 366 (0x01 << devno), 1); 367 pci_write_config(parent, 0x44, 368 (pci_read_config(parent, 0x44, 4) & 369 ~(0xff << offset)) | 370 (dmatimings[2] << offset), 4); 371 piomode = ATA_PIO4; 372 } else if (mode >= ATA_WDMA0) { 373 /* Disable UDMA, set WDMA mode and timings, calculate PIO. */ 374 pci_write_config(parent, 0x54, 375 pci_read_config(parent, 0x54, 1) & 376 ~(0x01 << devno), 1); 377 pci_write_config(parent, 0x44, 378 (pci_read_config(parent, 0x44, 4) & 379 ~(0xff << offset)) | 380 (dmatimings[mode & ATA_MODE_MASK] << offset), 4); 381 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 : 382 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4; 383 } else { 384 /* Disable UDMA, set requested PIO. */ 385 pci_write_config(parent, 0x54, 386 pci_read_config(parent, 0x54, 1) & 387 ~(0x01 << devno), 1); 388 piomode = mode; 389 } 390 /* Set PIO mode and timings, calculated above. */ 391 pci_write_config(parent, 0x4a, 392 (pci_read_config(parent, 0x4a, 2) & 393 ~(0xf << (devno << 2))) | 394 ((piomode - ATA_PIO0) << (devno<<2)),2); 395 pci_write_config(parent, 0x40, 396 (pci_read_config(parent, 0x40, 4) & 397 ~(0xff << offset)) | 398 (piotimings[ata_mode2idx(piomode)] << offset), 4); 399 return (mode); 400 } 401 402 ATA_DECLARE_DRIVER(ata_serverworks); 403