1 /*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ata.h" 31 #include <sys/param.h> 32 #include <sys/module.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/ata.h> 36 #include <sys/bus.h> 37 #include <sys/endian.h> 38 #include <sys/malloc.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/sema.h> 42 #include <sys/taskqueue.h> 43 #include <vm/uma.h> 44 #include <machine/stdarg.h> 45 #include <machine/resource.h> 46 #include <machine/bus.h> 47 #include <sys/rman.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/ata/ata-all.h> 51 #include <dev/ata/ata-pci.h> 52 #include <ata_if.h> 53 54 /* local prototypes */ 55 static int ata_serverworks_chipinit(device_t dev); 56 static int ata_serverworks_ch_attach(device_t dev); 57 static int ata_serverworks_ch_detach(device_t dev); 58 static void ata_serverworks_tf_read(struct ata_request *request); 59 static void ata_serverworks_tf_write(struct ata_request *request); 60 static int ata_serverworks_setmode(device_t dev, int target, int mode); 61 #ifdef __powerpc__ 62 static int ata_serverworks_status(device_t dev); 63 #endif 64 65 /* misc defines */ 66 #define SWKS_33 0 67 #define SWKS_66 1 68 #define SWKS_100 2 69 #define SWKS_MIO 3 70 71 72 /* 73 * ServerWorks chipset support functions 74 */ 75 static int 76 ata_serverworks_probe(device_t dev) 77 { 78 struct ata_pci_controller *ctlr = device_get_softc(dev); 79 static struct ata_chip_id ids[] = 80 {{ ATA_ROSB4, 0x00, SWKS_33, 0, ATA_WDMA2, "ROSB4" }, 81 { ATA_CSB5, 0x92, SWKS_100, 0, ATA_UDMA5, "CSB5" }, 82 { ATA_CSB5, 0x00, SWKS_66, 0, ATA_UDMA4, "CSB5" }, 83 { ATA_CSB6, 0x00, SWKS_100, 0, ATA_UDMA5, "CSB6" }, 84 { ATA_CSB6_1, 0x00, SWKS_66, 0, ATA_UDMA4, "CSB6" }, 85 { ATA_HT1000, 0x00, SWKS_100, 0, ATA_UDMA5, "HT1000" }, 86 { ATA_HT1000_S1, 0x00, SWKS_MIO, 4, ATA_SA150, "HT1000" }, 87 { ATA_HT1000_S2, 0x00, SWKS_MIO, 4, ATA_SA150, "HT1000" }, 88 { ATA_K2, 0x00, SWKS_MIO, 4, ATA_SA150, "K2" }, 89 { ATA_FRODO4, 0x00, SWKS_MIO, 4, ATA_SA150, "Frodo4" }, 90 { ATA_FRODO8, 0x00, SWKS_MIO, 8, ATA_SA150, "Frodo8" }, 91 { 0, 0, 0, 0, 0, 0}}; 92 93 if (pci_get_vendor(dev) != ATA_SERVERWORKS_ID) 94 return ENXIO; 95 96 if (!(ctlr->chip = ata_match_chip(dev, ids))) 97 return ENXIO; 98 99 ata_set_desc(dev); 100 ctlr->chipinit = ata_serverworks_chipinit; 101 return (BUS_PROBE_DEFAULT); 102 } 103 104 #ifdef __powerpc__ 105 static int 106 ata_serverworks_status(device_t dev) 107 { 108 struct ata_channel *ch = device_get_softc(dev); 109 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 110 111 /* 112 * Check if this interrupt belongs to our channel. 113 */ 114 if (!(ATA_INL(ctlr->r_res2, 0x1f80) & (1 << ch->unit))) 115 return (0); 116 117 /* 118 * We need to do a 4-byte read on the status reg before the values 119 * will report correctly 120 */ 121 122 ATA_IDX_INL(ch,ATA_STATUS); 123 124 return ata_pci_status(dev); 125 } 126 #endif 127 128 static int 129 ata_serverworks_chipinit(device_t dev) 130 { 131 struct ata_pci_controller *ctlr = device_get_softc(dev); 132 133 if (ata_setup_interrupt(dev, ata_generic_intr)) 134 return ENXIO; 135 136 if (ctlr->chip->cfg1 == SWKS_MIO) { 137 ctlr->r_type2 = SYS_RES_MEMORY; 138 ctlr->r_rid2 = PCIR_BAR(5); 139 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 140 &ctlr->r_rid2, RF_ACTIVE))) 141 return ENXIO; 142 143 ctlr->channels = ctlr->chip->cfg2; 144 ctlr->ch_attach = ata_serverworks_ch_attach; 145 ctlr->ch_detach = ata_serverworks_ch_detach; 146 ctlr->setmode = ata_sata_setmode; 147 ctlr->getrev = ata_sata_getrev; 148 return 0; 149 } 150 else if (ctlr->chip->cfg1 == SWKS_33) { 151 device_t *children; 152 int nchildren, i; 153 154 /* locate the ISA part in the southbridge and enable UDMA33 */ 155 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){ 156 for (i = 0; i < nchildren; i++) { 157 if (pci_get_devid(children[i]) == ATA_ROSB4_ISA) { 158 pci_write_config(children[i], 0x64, 159 (pci_read_config(children[i], 0x64, 4) & 160 ~0x00002000) | 0x00004000, 4); 161 break; 162 } 163 } 164 free(children, M_TEMP); 165 } 166 } 167 else { 168 pci_write_config(dev, 0x5a, 169 (pci_read_config(dev, 0x5a, 1) & ~0x40) | 170 (ctlr->chip->cfg1 == SWKS_100) ? 0x03 : 0x02, 1); 171 } 172 ctlr->setmode = ata_serverworks_setmode; 173 return 0; 174 } 175 176 static int 177 ata_serverworks_ch_attach(device_t dev) 178 { 179 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 180 struct ata_channel *ch = device_get_softc(dev); 181 int ch_offset; 182 int i; 183 184 ata_pci_dmainit(dev); 185 186 ch_offset = ch->unit * 0x100; 187 188 for (i = ATA_DATA; i < ATA_MAX_RES; i++) 189 ch->r_io[i].res = ctlr->r_res2; 190 191 /* setup ATA registers */ 192 ch->r_io[ATA_DATA].offset = ch_offset + 0x00; 193 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x04; 194 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08; 195 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c; 196 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; 197 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14; 198 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18; 199 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1c; 200 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x20; 201 ata_default_registers(dev); 202 203 /* setup DMA registers */ 204 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x30; 205 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x32; 206 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x34; 207 208 /* setup SATA registers */ 209 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x40; 210 ch->r_io[ATA_SERROR].offset = ch_offset + 0x44; 211 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x48; 212 213 ch->flags |= ATA_NO_SLAVE; 214 ch->flags |= ATA_SATA; 215 ata_pci_hw(dev); 216 ch->hw.tf_read = ata_serverworks_tf_read; 217 ch->hw.tf_write = ata_serverworks_tf_write; 218 #ifdef __powerpc__ 219 ch->hw.status = ata_serverworks_status; 220 #endif 221 222 if (ctlr->chip->chipid == ATA_K2) { 223 /* 224 * The revision 1 K2 SATA controller has interesting bugs. Patch them. 225 * These magic numbers regulate interrupt delivery in the first few 226 * cases and are pure magic in the last case. 227 * 228 * Values obtained from the Darwin driver. 229 */ 230 231 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, 0x04); 232 ATA_IDX_OUTL(ch, ATA_SERROR, 0xffffffff); 233 ATA_IDX_OUTL(ch, ATA_SCONTROL, 0x00000300); 234 ATA_OUTL(ctlr->r_res2, ch_offset + 0x88, 0); 235 ATA_OUTL(ctlr->r_res2, ch_offset + 0x80, 236 ATA_INL(ctlr->r_res2, ch_offset + 0x80) & ~0x00040000); 237 238 /* 239 * Some controllers have a bug where they will send the command 240 * to the drive before seeing a DMA start, and then can begin 241 * receiving data before the DMA start arrives. The controller 242 * will then become confused and either corrupt the data or crash. 243 * Remedy this by starting DMA before sending the drive command. 244 */ 245 246 ch->flags |= ATA_DMA_BEFORE_CMD; 247 } 248 249 /* chip does not reliably do 64K DMA transfers */ 250 ch->dma.max_iosize = 64 * DEV_BSIZE; 251 252 return 0; 253 } 254 255 static int 256 ata_serverworks_ch_detach(device_t dev) 257 { 258 259 ata_pci_dmafini(dev); 260 return (0); 261 } 262 263 static void 264 ata_serverworks_tf_read(struct ata_request *request) 265 { 266 struct ata_channel *ch = device_get_softc(request->parent); 267 268 if (request->flags & ATA_R_48BIT) { 269 u_int16_t temp; 270 271 request->u.ata.count = ATA_IDX_INW(ch, ATA_COUNT); 272 temp = ATA_IDX_INW(ch, ATA_SECTOR); 273 request->u.ata.lba = (u_int64_t)(temp & 0x00ff) | 274 ((u_int64_t)(temp & 0xff00) << 24); 275 temp = ATA_IDX_INW(ch, ATA_CYL_LSB); 276 request->u.ata.lba |= ((u_int64_t)(temp & 0x00ff) << 8) | 277 ((u_int64_t)(temp & 0xff00) << 32); 278 temp = ATA_IDX_INW(ch, ATA_CYL_MSB); 279 request->u.ata.lba |= ((u_int64_t)(temp & 0x00ff) << 16) | 280 ((u_int64_t)(temp & 0xff00) << 40); 281 } 282 else { 283 request->u.ata.count = ATA_IDX_INW(ch, ATA_COUNT) & 0x00ff; 284 request->u.ata.lba = (ATA_IDX_INW(ch, ATA_SECTOR) & 0x00ff) | 285 ((ATA_IDX_INW(ch, ATA_CYL_LSB) & 0x00ff) << 8) | 286 ((ATA_IDX_INW(ch, ATA_CYL_MSB) & 0x00ff) << 16) | 287 ((ATA_IDX_INW(ch, ATA_DRIVE) & 0xf) << 24); 288 } 289 } 290 291 static void 292 ata_serverworks_tf_write(struct ata_request *request) 293 { 294 struct ata_channel *ch = device_get_softc(request->parent); 295 #ifndef ATA_CAM 296 struct ata_device *atadev = device_get_softc(request->dev); 297 #endif 298 299 if (request->flags & ATA_R_48BIT) { 300 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature); 301 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count); 302 ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) | 303 (request->u.ata.lba & 0x00ff)); 304 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) | 305 ((request->u.ata.lba >> 8) & 0x00ff)); 306 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) | 307 ((request->u.ata.lba >> 16) & 0x00ff)); 308 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit)); 309 } 310 else { 311 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature); 312 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count); 313 #ifndef ATA_CAM 314 if (atadev->flags & ATA_D_USE_CHS) { 315 int heads, sectors; 316 317 if (atadev->param.atavalid & ATA_FLAG_54_58) { 318 heads = atadev->param.current_heads; 319 sectors = atadev->param.current_sectors; 320 } 321 else { 322 heads = atadev->param.heads; 323 sectors = atadev->param.sectors; 324 } 325 ATA_IDX_OUTW(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1); 326 ATA_IDX_OUTW(ch, ATA_CYL_LSB, 327 (request->u.ata.lba / (sectors * heads))); 328 ATA_IDX_OUTW(ch, ATA_CYL_MSB, 329 (request->u.ata.lba / (sectors * heads)) >> 8); 330 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit) | 331 (((request->u.ata.lba% (sectors * heads)) / 332 sectors) & 0xf)); 333 } 334 else { 335 #endif 336 ATA_IDX_OUTW(ch, ATA_SECTOR, request->u.ata.lba); 337 ATA_IDX_OUTW(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 338 ATA_IDX_OUTW(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 339 ATA_IDX_OUTW(ch, ATA_DRIVE, 340 ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) | 341 ((request->u.ata.lba >> 24) & 0x0f)); 342 #ifndef ATA_CAM 343 } 344 #endif 345 } 346 } 347 348 static int 349 ata_serverworks_setmode(device_t dev, int target, int mode) 350 { 351 device_t parent = device_get_parent(dev); 352 struct ata_pci_controller *ctlr = device_get_softc(parent); 353 struct ata_channel *ch = device_get_softc(dev); 354 int devno = (ch->unit << 1) + target; 355 int offset = (devno ^ 0x01) << 3; 356 int piomode; 357 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 }; 358 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 }; 359 360 mode = min(mode, ctlr->chip->max_dma); 361 if (mode >= ATA_UDMA0) { 362 /* Set UDMA mode, enable UDMA, set WDMA2/PIO4 */ 363 pci_write_config(parent, 0x56, 364 (pci_read_config(parent, 0x56, 2) & 365 ~(0xf << (devno << 2))) | 366 ((mode & ATA_MODE_MASK) << (devno << 2)), 2); 367 pci_write_config(parent, 0x54, 368 pci_read_config(parent, 0x54, 1) | 369 (0x01 << devno), 1); 370 pci_write_config(parent, 0x44, 371 (pci_read_config(parent, 0x44, 4) & 372 ~(0xff << offset)) | 373 (dmatimings[2] << offset), 4); 374 piomode = ATA_PIO4; 375 } else if (mode >= ATA_WDMA0) { 376 /* Disable UDMA, set WDMA mode and timings, calculate PIO. */ 377 pci_write_config(parent, 0x54, 378 pci_read_config(parent, 0x54, 1) & 379 ~(0x01 << devno), 1); 380 pci_write_config(parent, 0x44, 381 (pci_read_config(parent, 0x44, 4) & 382 ~(0xff << offset)) | 383 (dmatimings[mode & ATA_MODE_MASK] << offset), 4); 384 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 : 385 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4; 386 } else { 387 /* Disable UDMA, set requested PIO. */ 388 pci_write_config(parent, 0x54, 389 pci_read_config(parent, 0x54, 1) & 390 ~(0x01 << devno), 1); 391 piomode = mode; 392 } 393 /* Set PIO mode and timings, calculated above. */ 394 if (ctlr->chip->cfg1 != SWKS_33) { 395 pci_write_config(parent, 0x4a, 396 (pci_read_config(parent, 0x4a, 2) & 397 ~(0xf << (devno << 2))) | 398 ((piomode - ATA_PIO0) << (devno<<2)),2); 399 } 400 pci_write_config(parent, 0x40, 401 (pci_read_config(parent, 0x40, 4) & 402 ~(0xff << offset)) | 403 (piotimings[ata_mode2idx(piomode)] << offset), 4); 404 return (mode); 405 } 406 407 ATA_DECLARE_DRIVER(ata_serverworks); 408