1 /*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ata.h" 31 #include <sys/param.h> 32 #include <sys/module.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/ata.h> 36 #include <sys/bus.h> 37 #include <sys/endian.h> 38 #include <sys/malloc.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/sema.h> 42 #include <sys/taskqueue.h> 43 #include <vm/uma.h> 44 #include <machine/stdarg.h> 45 #include <machine/resource.h> 46 #include <machine/bus.h> 47 #include <sys/rman.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/ata/ata-all.h> 51 #include <dev/ata/ata-pci.h> 52 #include <ata_if.h> 53 54 /* local prototypes */ 55 static int ata_serverworks_chipinit(device_t dev); 56 static int ata_serverworks_ch_attach(device_t dev); 57 static int ata_serverworks_ch_detach(device_t dev); 58 static void ata_serverworks_tf_read(struct ata_request *request); 59 static void ata_serverworks_tf_write(struct ata_request *request); 60 static void ata_serverworks_setmode(device_t dev, int mode); 61 #ifdef __powerpc__ 62 static int ata_serverworks_status(device_t dev); 63 #endif 64 65 /* misc defines */ 66 #define SWKS_33 0 67 #define SWKS_66 1 68 #define SWKS_100 2 69 #define SWKS_MIO 3 70 71 72 /* 73 * ServerWorks chipset support functions 74 */ 75 static int 76 ata_serverworks_probe(device_t dev) 77 { 78 struct ata_pci_controller *ctlr = device_get_softc(dev); 79 static struct ata_chip_id ids[] = 80 {{ ATA_ROSB4, 0x00, SWKS_33, 0, ATA_UDMA2, "ROSB4" }, 81 { ATA_CSB5, 0x92, SWKS_100, 0, ATA_UDMA5, "CSB5" }, 82 { ATA_CSB5, 0x00, SWKS_66, 0, ATA_UDMA4, "CSB5" }, 83 { ATA_CSB6, 0x00, SWKS_100, 0, ATA_UDMA5, "CSB6" }, 84 { ATA_CSB6_1, 0x00, SWKS_66, 0, ATA_UDMA4, "CSB6" }, 85 { ATA_HT1000, 0x00, SWKS_100, 0, ATA_UDMA5, "HT1000" }, 86 { ATA_HT1000_S1, 0x00, SWKS_MIO, 4, ATA_SA150, "HT1000" }, 87 { ATA_HT1000_S2, 0x00, SWKS_MIO, 4, ATA_SA150, "HT1000" }, 88 { ATA_K2, 0x00, SWKS_MIO, 4, ATA_SA150, "K2" }, 89 { ATA_FRODO4, 0x00, SWKS_MIO, 4, ATA_SA150, "Frodo4" }, 90 { ATA_FRODO8, 0x00, SWKS_MIO, 8, ATA_SA150, "Frodo8" }, 91 { 0, 0, 0, 0, 0, 0}}; 92 93 if (pci_get_vendor(dev) != ATA_SERVERWORKS_ID) 94 return ENXIO; 95 96 if (!(ctlr->chip = ata_match_chip(dev, ids))) 97 return ENXIO; 98 99 ata_set_desc(dev); 100 ctlr->chipinit = ata_serverworks_chipinit; 101 return (BUS_PROBE_DEFAULT); 102 } 103 104 #ifdef __powerpc__ 105 static int 106 ata_serverworks_status(device_t dev) 107 { 108 struct ata_channel *ch = device_get_softc(dev); 109 110 /* 111 * We need to do a 4-byte read on the status reg before the values 112 * will report correctly 113 */ 114 115 ATA_IDX_INL(ch,ATA_STATUS); 116 117 return ata_pci_status(dev); 118 } 119 #endif 120 121 static int 122 ata_serverworks_chipinit(device_t dev) 123 { 124 struct ata_pci_controller *ctlr = device_get_softc(dev); 125 126 if (ata_setup_interrupt(dev, ata_generic_intr)) 127 return ENXIO; 128 129 if (ctlr->chip->cfg1 == SWKS_MIO) { 130 ctlr->r_type2 = SYS_RES_MEMORY; 131 ctlr->r_rid2 = PCIR_BAR(5); 132 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 133 &ctlr->r_rid2, RF_ACTIVE))) 134 return ENXIO; 135 136 ctlr->channels = ctlr->chip->cfg2; 137 ctlr->ch_attach = ata_serverworks_ch_attach; 138 ctlr->ch_detach = ata_serverworks_ch_detach; 139 ctlr->setmode = ata_sata_setmode; 140 return 0; 141 } 142 else if (ctlr->chip->cfg1 == SWKS_33) { 143 device_t *children; 144 int nchildren, i; 145 146 /* locate the ISA part in the southbridge and enable UDMA33 */ 147 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){ 148 for (i = 0; i < nchildren; i++) { 149 if (pci_get_devid(children[i]) == ATA_ROSB4_ISA) { 150 pci_write_config(children[i], 0x64, 151 (pci_read_config(children[i], 0x64, 4) & 152 ~0x00002000) | 0x00004000, 4); 153 break; 154 } 155 } 156 free(children, M_TEMP); 157 } 158 } 159 else { 160 pci_write_config(dev, 0x5a, 161 (pci_read_config(dev, 0x5a, 1) & ~0x40) | 162 (ctlr->chip->cfg1 == SWKS_100) ? 0x03 : 0x02, 1); 163 } 164 ctlr->setmode = ata_serverworks_setmode; 165 return 0; 166 } 167 168 static int 169 ata_serverworks_ch_attach(device_t dev) 170 { 171 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 172 struct ata_channel *ch = device_get_softc(dev); 173 int ch_offset; 174 int i; 175 176 ata_pci_dmainit(dev); 177 178 ch_offset = ch->unit * 0x100; 179 180 for (i = ATA_DATA; i < ATA_MAX_RES; i++) 181 ch->r_io[i].res = ctlr->r_res2; 182 183 /* setup ATA registers */ 184 ch->r_io[ATA_DATA].offset = ch_offset + 0x00; 185 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x04; 186 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08; 187 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c; 188 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; 189 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14; 190 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18; 191 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1c; 192 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x20; 193 ata_default_registers(dev); 194 195 /* setup DMA registers */ 196 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x30; 197 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x32; 198 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x34; 199 200 /* setup SATA registers */ 201 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x40; 202 ch->r_io[ATA_SERROR].offset = ch_offset + 0x44; 203 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x48; 204 205 ch->flags |= ATA_NO_SLAVE; 206 ata_pci_hw(dev); 207 ch->hw.tf_read = ata_serverworks_tf_read; 208 ch->hw.tf_write = ata_serverworks_tf_write; 209 #ifdef __powerpc__ 210 ch->hw.status = ata_serverworks_status; 211 #endif 212 213 /* chip does not reliably do 64K DMA transfers */ 214 ch->dma.max_iosize = 64 * DEV_BSIZE; 215 216 return 0; 217 } 218 219 static int 220 ata_serverworks_ch_detach(device_t dev) 221 { 222 223 ata_pci_dmafini(dev); 224 return (0); 225 } 226 227 static void 228 ata_serverworks_tf_read(struct ata_request *request) 229 { 230 struct ata_channel *ch = device_get_softc(request->parent); 231 struct ata_device *atadev = device_get_softc(request->dev); 232 233 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 234 u_int16_t temp; 235 236 request->u.ata.count = ATA_IDX_INW(ch, ATA_COUNT); 237 temp = ATA_IDX_INW(ch, ATA_SECTOR); 238 request->u.ata.lba = (u_int64_t)(temp & 0x00ff) | 239 ((u_int64_t)(temp & 0xff00) << 24); 240 temp = ATA_IDX_INW(ch, ATA_CYL_LSB); 241 request->u.ata.lba |= ((u_int64_t)(temp & 0x00ff) << 8) | 242 ((u_int64_t)(temp & 0xff00) << 32); 243 temp = ATA_IDX_INW(ch, ATA_CYL_MSB); 244 request->u.ata.lba |= ((u_int64_t)(temp & 0x00ff) << 16) | 245 ((u_int64_t)(temp & 0xff00) << 40); 246 } 247 else { 248 request->u.ata.count = ATA_IDX_INW(ch, ATA_COUNT) & 0x00ff; 249 request->u.ata.lba = (ATA_IDX_INW(ch, ATA_SECTOR) & 0x00ff) | 250 ((ATA_IDX_INW(ch, ATA_CYL_LSB) & 0x00ff) << 8) | 251 ((ATA_IDX_INW(ch, ATA_CYL_MSB) & 0x00ff) << 16) | 252 ((ATA_IDX_INW(ch, ATA_DRIVE) & 0xf) << 24); 253 } 254 } 255 256 static void 257 ata_serverworks_tf_write(struct ata_request *request) 258 { 259 struct ata_channel *ch = device_get_softc(request->parent); 260 struct ata_device *atadev = device_get_softc(request->dev); 261 262 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 263 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature); 264 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count); 265 ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) | 266 (request->u.ata.lba & 0x00ff)); 267 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) | 268 ((request->u.ata.lba >> 8) & 0x00ff)); 269 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) | 270 ((request->u.ata.lba >> 16) & 0x00ff)); 271 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(atadev->unit)); 272 } 273 else { 274 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature); 275 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count); 276 if (atadev->flags & ATA_D_USE_CHS) { 277 int heads, sectors; 278 279 if (atadev->param.atavalid & ATA_FLAG_54_58) { 280 heads = atadev->param.current_heads; 281 sectors = atadev->param.current_sectors; 282 } 283 else { 284 heads = atadev->param.heads; 285 sectors = atadev->param.sectors; 286 } 287 ATA_IDX_OUTW(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1); 288 ATA_IDX_OUTW(ch, ATA_CYL_LSB, 289 (request->u.ata.lba / (sectors * heads))); 290 ATA_IDX_OUTW(ch, ATA_CYL_MSB, 291 (request->u.ata.lba / (sectors * heads)) >> 8); 292 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(atadev->unit) | 293 (((request->u.ata.lba% (sectors * heads)) / 294 sectors) & 0xf)); 295 } 296 else { 297 ATA_IDX_OUTW(ch, ATA_SECTOR, request->u.ata.lba); 298 ATA_IDX_OUTW(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 299 ATA_IDX_OUTW(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 300 ATA_IDX_OUTW(ch, ATA_DRIVE, 301 ATA_D_IBM | ATA_D_LBA | ATA_DEV(atadev->unit) | 302 ((request->u.ata.lba >> 24) & 0x0f)); 303 } 304 } 305 } 306 307 static void 308 ata_serverworks_setmode(device_t dev, int mode) 309 { 310 device_t gparent = GRANDPARENT(dev); 311 struct ata_pci_controller *ctlr = device_get_softc(gparent); 312 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 313 struct ata_device *atadev = device_get_softc(dev); 314 int devno = (ch->unit << 1) + atadev->unit; 315 int offset = (devno ^ 0x01) << 3; 316 int error; 317 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20, 318 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; 319 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 }; 320 321 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 322 323 mode = ata_check_80pin(dev, mode); 324 325 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 326 327 if (bootverbose) 328 device_printf(dev, "%ssetting %s on %s chip\n", 329 (error) ? "FAILURE " : "", 330 ata_mode2str(mode), ctlr->chip->text); 331 if (!error) { 332 if (mode >= ATA_UDMA0) { 333 pci_write_config(gparent, 0x56, 334 (pci_read_config(gparent, 0x56, 2) & 335 ~(0xf << (devno << 2))) | 336 ((mode & ATA_MODE_MASK) << (devno << 2)), 2); 337 pci_write_config(gparent, 0x54, 338 pci_read_config(gparent, 0x54, 1) | 339 (0x01 << devno), 1); 340 pci_write_config(gparent, 0x44, 341 (pci_read_config(gparent, 0x44, 4) & 342 ~(0xff << offset)) | 343 (dmatimings[2] << offset), 4); 344 } 345 else if (mode >= ATA_WDMA0) { 346 pci_write_config(gparent, 0x54, 347 pci_read_config(gparent, 0x54, 1) & 348 ~(0x01 << devno), 1); 349 pci_write_config(gparent, 0x44, 350 (pci_read_config(gparent, 0x44, 4) & 351 ~(0xff << offset)) | 352 (dmatimings[mode & ATA_MODE_MASK] << offset), 4); 353 } 354 else 355 pci_write_config(gparent, 0x54, 356 pci_read_config(gparent, 0x54, 1) & 357 ~(0x01 << devno), 1); 358 359 pci_write_config(gparent, 0x40, 360 (pci_read_config(gparent, 0x40, 4) & 361 ~(0xff << offset)) | 362 (piotimings[ata_mode2idx(mode)] << offset), 4); 363 atadev->mode = mode; 364 } 365 } 366 367 ATA_DECLARE_DRIVER(ata_serverworks); 368