1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification, immediately at the beginning of the file. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/module.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/ata.h> 37 #include <sys/bus.h> 38 #include <sys/endian.h> 39 #include <sys/malloc.h> 40 #include <sys/lock.h> 41 #include <sys/mutex.h> 42 #include <sys/sema.h> 43 #include <sys/taskqueue.h> 44 #include <vm/uma.h> 45 #include <machine/stdarg.h> 46 #include <machine/resource.h> 47 #include <machine/bus.h> 48 #include <sys/rman.h> 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcireg.h> 51 #include <dev/ata/ata-all.h> 52 #include <dev/ata/ata-pci.h> 53 #include <ata_if.h> 54 55 /* local prototypes */ 56 static int ata_serverworks_chipinit(device_t dev); 57 static int ata_serverworks_ch_attach(device_t dev); 58 static int ata_serverworks_ch_detach(device_t dev); 59 static void ata_serverworks_tf_read(struct ata_request *request); 60 static void ata_serverworks_tf_write(struct ata_request *request); 61 static int ata_serverworks_setmode(device_t dev, int target, int mode); 62 static void ata_serverworks_sata_reset(device_t dev); 63 static int ata_serverworks_status(device_t dev); 64 65 /* misc defines */ 66 #define SWKS_33 0 67 #define SWKS_66 1 68 #define SWKS_100 2 69 #define SWKS_MIO 3 70 71 72 /* 73 * ServerWorks chipset support functions 74 */ 75 static int 76 ata_serverworks_probe(device_t dev) 77 { 78 struct ata_pci_controller *ctlr = device_get_softc(dev); 79 static const struct ata_chip_id ids[] = 80 {{ ATA_ROSB4, 0x00, SWKS_33, 0, ATA_WDMA2, "ROSB4" }, 81 { ATA_CSB5, 0x92, SWKS_100, 0, ATA_UDMA5, "CSB5" }, 82 { ATA_CSB5, 0x00, SWKS_66, 0, ATA_UDMA4, "CSB5" }, 83 { ATA_CSB6, 0x00, SWKS_100, 0, ATA_UDMA5, "CSB6" }, 84 { ATA_CSB6_1, 0x00, SWKS_66, 0, ATA_UDMA4, "CSB6" }, 85 { ATA_HT1000, 0x00, SWKS_100, 0, ATA_UDMA5, "HT1000" }, 86 { ATA_HT1000_S1, 0x00, SWKS_MIO, 4, ATA_SA150, "HT1000" }, 87 { ATA_HT1000_S2, 0x00, SWKS_MIO, 4, ATA_SA150, "HT1000" }, 88 { ATA_K2, 0x00, SWKS_MIO, 4, ATA_SA150, "K2" }, 89 { ATA_FRODO4, 0x00, SWKS_MIO, 4, ATA_SA150, "Frodo4" }, 90 { ATA_FRODO8, 0x00, SWKS_MIO, 8, ATA_SA150, "Frodo8" }, 91 { 0, 0, 0, 0, 0, 0}}; 92 93 if (pci_get_vendor(dev) != ATA_SERVERWORKS_ID) 94 return ENXIO; 95 96 if (!(ctlr->chip = ata_match_chip(dev, ids))) 97 return ENXIO; 98 99 ata_set_desc(dev); 100 ctlr->chipinit = ata_serverworks_chipinit; 101 return (BUS_PROBE_LOW_PRIORITY); 102 } 103 104 static int 105 ata_serverworks_status(device_t dev) 106 { 107 struct ata_channel *ch = device_get_softc(dev); 108 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 109 110 /* 111 * Check if this interrupt belongs to our channel. 112 */ 113 if (!(ATA_INL(ctlr->r_res2, 0x1f80) & (1 << ch->unit))) 114 return (0); 115 116 /* 117 * We need to do a 4-byte read on the status reg before the values 118 * will report correctly 119 */ 120 121 ATA_IDX_INL(ch,ATA_STATUS); 122 123 return ata_pci_status(dev); 124 } 125 126 static int 127 ata_serverworks_chipinit(device_t dev) 128 { 129 struct ata_pci_controller *ctlr = device_get_softc(dev); 130 131 if (ata_setup_interrupt(dev, ata_generic_intr)) 132 return ENXIO; 133 134 if (ctlr->chip->cfg1 == SWKS_MIO) { 135 ctlr->r_type2 = SYS_RES_MEMORY; 136 ctlr->r_rid2 = PCIR_BAR(5); 137 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 138 &ctlr->r_rid2, RF_ACTIVE))) 139 return ENXIO; 140 141 ctlr->channels = ctlr->chip->cfg2; 142 ctlr->ch_attach = ata_serverworks_ch_attach; 143 ctlr->ch_detach = ata_serverworks_ch_detach; 144 ctlr->setmode = ata_sata_setmode; 145 ctlr->getrev = ata_sata_getrev; 146 ctlr->reset = ata_serverworks_sata_reset; 147 return 0; 148 } 149 else if (ctlr->chip->cfg1 == SWKS_33) { 150 device_t *children; 151 int nchildren, i; 152 153 /* locate the ISA part in the southbridge and enable UDMA33 */ 154 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){ 155 for (i = 0; i < nchildren; i++) { 156 if (pci_get_devid(children[i]) == ATA_ROSB4_ISA) { 157 pci_write_config(children[i], 0x64, 158 (pci_read_config(children[i], 0x64, 4) & 159 ~0x00002000) | 0x00004000, 4); 160 break; 161 } 162 } 163 free(children, M_TEMP); 164 } 165 } 166 else { 167 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x40) | 168 ((ctlr->chip->cfg1 == SWKS_100) ? 0x03 : 0x02), 1); 169 } 170 ctlr->setmode = ata_serverworks_setmode; 171 return 0; 172 } 173 174 static int 175 ata_serverworks_ch_attach(device_t dev) 176 { 177 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 178 struct ata_channel *ch = device_get_softc(dev); 179 int ch_offset; 180 int i; 181 182 ch_offset = ch->unit * 0x100; 183 184 for (i = ATA_DATA; i < ATA_MAX_RES; i++) 185 ch->r_io[i].res = ctlr->r_res2; 186 187 /* setup ATA registers */ 188 ch->r_io[ATA_DATA].offset = ch_offset + 0x00; 189 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x04; 190 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08; 191 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c; 192 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; 193 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14; 194 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18; 195 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1c; 196 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x20; 197 ata_default_registers(dev); 198 199 /* setup DMA registers */ 200 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x30; 201 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x32; 202 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x34; 203 204 /* setup SATA registers */ 205 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x40; 206 ch->r_io[ATA_SERROR].offset = ch_offset + 0x44; 207 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x48; 208 209 ch->flags |= ATA_NO_SLAVE | ATA_SATA | ATA_KNOWN_PRESENCE; 210 ata_pci_hw(dev); 211 ch->hw.tf_read = ata_serverworks_tf_read; 212 ch->hw.tf_write = ata_serverworks_tf_write; 213 214 if (ctlr->chip->chipid == ATA_K2) { 215 /* 216 * Set SICR registers to turn off waiting for a status message 217 * before sending FIS. Values obtained from the Darwin driver. 218 */ 219 220 ATA_OUTL(ctlr->r_res2, ch_offset + 0x80, 221 ATA_INL(ctlr->r_res2, ch_offset + 0x80) & ~0x00040000); 222 ATA_OUTL(ctlr->r_res2, ch_offset + 0x88, 0); 223 224 /* 225 * Some controllers have a bug where they will send the command 226 * to the drive before seeing a DMA start, and then can begin 227 * receiving data before the DMA start arrives. The controller 228 * will then become confused and either corrupt the data or crash. 229 * Remedy this by starting DMA before sending the drive command. 230 */ 231 232 ch->flags |= ATA_DMA_BEFORE_CMD; 233 234 /* 235 * The status register must be read as a long to fill the other 236 * registers. 237 */ 238 239 ch->hw.status = ata_serverworks_status; 240 ch->flags |= ATA_STATUS_IS_LONG; 241 } 242 243 /* chip does not reliably do 64K DMA transfers */ 244 ch->dma.max_iosize = 64 * DEV_BSIZE; 245 246 ata_pci_dmainit(dev); 247 248 return 0; 249 } 250 251 static int 252 ata_serverworks_ch_detach(device_t dev) 253 { 254 255 ata_pci_dmafini(dev); 256 return (0); 257 } 258 259 static void 260 ata_serverworks_tf_read(struct ata_request *request) 261 { 262 struct ata_channel *ch = device_get_softc(request->parent); 263 264 if (request->flags & ATA_R_48BIT) { 265 u_int16_t temp; 266 267 request->u.ata.count = ATA_IDX_INW(ch, ATA_COUNT); 268 temp = ATA_IDX_INW(ch, ATA_SECTOR); 269 request->u.ata.lba = (u_int64_t)(temp & 0x00ff) | 270 ((u_int64_t)(temp & 0xff00) << 24); 271 temp = ATA_IDX_INW(ch, ATA_CYL_LSB); 272 request->u.ata.lba |= ((u_int64_t)(temp & 0x00ff) << 8) | 273 ((u_int64_t)(temp & 0xff00) << 32); 274 temp = ATA_IDX_INW(ch, ATA_CYL_MSB); 275 request->u.ata.lba |= ((u_int64_t)(temp & 0x00ff) << 16) | 276 ((u_int64_t)(temp & 0xff00) << 40); 277 } 278 else { 279 request->u.ata.count = ATA_IDX_INW(ch, ATA_COUNT) & 0x00ff; 280 request->u.ata.lba = (ATA_IDX_INW(ch, ATA_SECTOR) & 0x00ff) | 281 ((ATA_IDX_INW(ch, ATA_CYL_LSB) & 0x00ff) << 8) | 282 ((ATA_IDX_INW(ch, ATA_CYL_MSB) & 0x00ff) << 16) | 283 ((ATA_IDX_INW(ch, ATA_DRIVE) & 0xf) << 24); 284 } 285 } 286 287 static void 288 ata_serverworks_tf_write(struct ata_request *request) 289 { 290 struct ata_channel *ch = device_get_softc(request->parent); 291 292 if (request->flags & ATA_R_48BIT) { 293 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature); 294 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count); 295 ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) | 296 (request->u.ata.lba & 0x00ff)); 297 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) | 298 ((request->u.ata.lba >> 8) & 0x00ff)); 299 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) | 300 ((request->u.ata.lba >> 16) & 0x00ff)); 301 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit)); 302 } 303 else { 304 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature); 305 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count); 306 ATA_IDX_OUTW(ch, ATA_SECTOR, request->u.ata.lba); 307 ATA_IDX_OUTW(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 308 ATA_IDX_OUTW(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 309 ATA_IDX_OUTW(ch, ATA_DRIVE, 310 ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) | 311 ((request->u.ata.lba >> 24) & 0x0f)); 312 } 313 } 314 315 static int 316 ata_serverworks_setmode(device_t dev, int target, int mode) 317 { 318 device_t parent = device_get_parent(dev); 319 struct ata_pci_controller *ctlr = device_get_softc(parent); 320 struct ata_channel *ch = device_get_softc(dev); 321 int devno = (ch->unit << 1) + target; 322 int offset = (devno ^ 0x01) << 3; 323 int piomode; 324 static const uint8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 }; 325 static const uint8_t dmatimings[] = { 0x77, 0x21, 0x20 }; 326 327 mode = min(mode, ctlr->chip->max_dma); 328 if (mode >= ATA_UDMA0) { 329 /* Set UDMA mode, enable UDMA, set WDMA2/PIO4 */ 330 pci_write_config(parent, 0x56, 331 (pci_read_config(parent, 0x56, 2) & 332 ~(0xf << (devno << 2))) | 333 ((mode & ATA_MODE_MASK) << (devno << 2)), 2); 334 pci_write_config(parent, 0x54, 335 pci_read_config(parent, 0x54, 1) | 336 (0x01 << devno), 1); 337 pci_write_config(parent, 0x44, 338 (pci_read_config(parent, 0x44, 4) & 339 ~(0xff << offset)) | 340 (dmatimings[2] << offset), 4); 341 piomode = ATA_PIO4; 342 } else if (mode >= ATA_WDMA0) { 343 /* Disable UDMA, set WDMA mode and timings, calculate PIO. */ 344 pci_write_config(parent, 0x54, 345 pci_read_config(parent, 0x54, 1) & 346 ~(0x01 << devno), 1); 347 pci_write_config(parent, 0x44, 348 (pci_read_config(parent, 0x44, 4) & 349 ~(0xff << offset)) | 350 (dmatimings[mode & ATA_MODE_MASK] << offset), 4); 351 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 : 352 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4; 353 } else { 354 /* Disable UDMA, set requested PIO. */ 355 pci_write_config(parent, 0x54, 356 pci_read_config(parent, 0x54, 1) & 357 ~(0x01 << devno), 1); 358 piomode = mode; 359 } 360 /* Set PIO mode and timings, calculated above. */ 361 if (ctlr->chip->cfg1 != SWKS_33) { 362 pci_write_config(parent, 0x4a, 363 (pci_read_config(parent, 0x4a, 2) & 364 ~(0xf << (devno << 2))) | 365 ((piomode - ATA_PIO0) << (devno<<2)),2); 366 } 367 pci_write_config(parent, 0x40, 368 (pci_read_config(parent, 0x40, 4) & 369 ~(0xff << offset)) | 370 (piotimings[ata_mode2idx(piomode)] << offset), 4); 371 return (mode); 372 } 373 374 static void 375 ata_serverworks_sata_reset(device_t dev) 376 { 377 struct ata_channel *ch = device_get_softc(dev); 378 379 if (ata_sata_phy_reset(dev, -1, 0)) 380 ata_generic_reset(dev); 381 else 382 ch->devices = 0; 383 } 384 385 ATA_DECLARE_DRIVER(ata_serverworks); 386