1 /*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ata.h" 31 #include <sys/param.h> 32 #include <sys/module.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/ata.h> 36 #include <sys/bus.h> 37 #include <sys/endian.h> 38 #include <sys/malloc.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/sema.h> 42 #include <sys/taskqueue.h> 43 #include <vm/uma.h> 44 #include <machine/stdarg.h> 45 #include <machine/resource.h> 46 #include <machine/bus.h> 47 #include <sys/rman.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/ata/ata-all.h> 51 #include <dev/ata/ata-pci.h> 52 #include <ata_if.h> 53 54 /* local prototypes */ 55 static int ata_serverworks_chipinit(device_t dev); 56 static int ata_serverworks_ch_attach(device_t dev); 57 static int ata_serverworks_ch_detach(device_t dev); 58 static void ata_serverworks_tf_read(struct ata_request *request); 59 static void ata_serverworks_tf_write(struct ata_request *request); 60 static void ata_serverworks_setmode(device_t dev, int mode); 61 62 /* misc defines */ 63 #define SWKS_33 0 64 #define SWKS_66 1 65 #define SWKS_100 2 66 #define SWKS_MIO 3 67 68 69 /* 70 * ServerWorks chipset support functions 71 */ 72 static int 73 ata_serverworks_probe(device_t dev) 74 { 75 struct ata_pci_controller *ctlr = device_get_softc(dev); 76 static struct ata_chip_id ids[] = 77 {{ ATA_ROSB4, 0x00, SWKS_33, 0, ATA_UDMA2, "ROSB4" }, 78 { ATA_CSB5, 0x92, SWKS_100, 0, ATA_UDMA5, "CSB5" }, 79 { ATA_CSB5, 0x00, SWKS_66, 0, ATA_UDMA4, "CSB5" }, 80 { ATA_CSB6, 0x00, SWKS_100, 0, ATA_UDMA5, "CSB6" }, 81 { ATA_CSB6_1, 0x00, SWKS_66, 0, ATA_UDMA4, "CSB6" }, 82 { ATA_HT1000, 0x00, SWKS_100, 0, ATA_UDMA5, "HT1000" }, 83 { ATA_HT1000_S1, 0x00, SWKS_MIO, 4, ATA_SA150, "HT1000" }, 84 { ATA_HT1000_S2, 0x00, SWKS_MIO, 4, ATA_SA150, "HT1000" }, 85 { ATA_K2, 0x00, SWKS_MIO, 4, ATA_SA150, "K2" }, 86 { ATA_FRODO4, 0x00, SWKS_MIO, 4, ATA_SA150, "Frodo4" }, 87 { ATA_FRODO8, 0x00, SWKS_MIO, 8, ATA_SA150, "Frodo8" }, 88 { 0, 0, 0, 0, 0, 0}}; 89 90 if (pci_get_vendor(dev) != ATA_SERVERWORKS_ID) 91 return ENXIO; 92 93 if (!(ctlr->chip = ata_match_chip(dev, ids))) 94 return ENXIO; 95 96 ata_set_desc(dev); 97 ctlr->chipinit = ata_serverworks_chipinit; 98 return 0; 99 } 100 101 static int 102 ata_serverworks_chipinit(device_t dev) 103 { 104 struct ata_pci_controller *ctlr = device_get_softc(dev); 105 106 if (ata_setup_interrupt(dev, ata_generic_intr)) 107 return ENXIO; 108 109 if (ctlr->chip->cfg1 == SWKS_MIO) { 110 ctlr->r_type2 = SYS_RES_MEMORY; 111 ctlr->r_rid2 = PCIR_BAR(5); 112 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 113 &ctlr->r_rid2, RF_ACTIVE))) 114 return ENXIO; 115 116 ctlr->channels = ctlr->chip->cfg2; 117 ctlr->ch_attach = ata_serverworks_ch_attach; 118 ctlr->ch_detach = ata_serverworks_ch_detach; 119 ctlr->setmode = ata_sata_setmode; 120 return 0; 121 } 122 else if (ctlr->chip->cfg1 == SWKS_33) { 123 device_t *children; 124 int nchildren, i; 125 126 /* locate the ISA part in the southbridge and enable UDMA33 */ 127 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){ 128 for (i = 0; i < nchildren; i++) { 129 if (pci_get_devid(children[i]) == ATA_ROSB4_ISA) { 130 pci_write_config(children[i], 0x64, 131 (pci_read_config(children[i], 0x64, 4) & 132 ~0x00002000) | 0x00004000, 4); 133 break; 134 } 135 } 136 free(children, M_TEMP); 137 } 138 } 139 else { 140 pci_write_config(dev, 0x5a, 141 (pci_read_config(dev, 0x5a, 1) & ~0x40) | 142 (ctlr->chip->cfg1 == SWKS_100) ? 0x03 : 0x02, 1); 143 } 144 ctlr->setmode = ata_serverworks_setmode; 145 return 0; 146 } 147 148 static int 149 ata_serverworks_ch_attach(device_t dev) 150 { 151 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 152 struct ata_channel *ch = device_get_softc(dev); 153 int ch_offset; 154 int i; 155 156 ata_pci_dmainit(dev); 157 158 ch_offset = ch->unit * 0x100; 159 160 for (i = ATA_DATA; i < ATA_MAX_RES; i++) 161 ch->r_io[i].res = ctlr->r_res2; 162 163 /* setup ATA registers */ 164 ch->r_io[ATA_DATA].offset = ch_offset + 0x00; 165 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x04; 166 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08; 167 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c; 168 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; 169 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14; 170 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18; 171 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1c; 172 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x20; 173 ata_default_registers(dev); 174 175 /* setup DMA registers */ 176 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x30; 177 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x32; 178 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x34; 179 180 /* setup SATA registers */ 181 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x40; 182 ch->r_io[ATA_SERROR].offset = ch_offset + 0x44; 183 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x48; 184 185 ch->flags |= ATA_NO_SLAVE; 186 ata_pci_hw(dev); 187 ch->hw.tf_read = ata_serverworks_tf_read; 188 ch->hw.tf_write = ata_serverworks_tf_write; 189 190 /* chip does not reliably do 64K DMA transfers */ 191 ch->dma.max_iosize = 64 * DEV_BSIZE; 192 193 return 0; 194 } 195 196 static int 197 ata_serverworks_ch_detach(device_t dev) 198 { 199 200 ata_pci_dmafini(dev); 201 return (0); 202 } 203 204 static void 205 ata_serverworks_tf_read(struct ata_request *request) 206 { 207 struct ata_channel *ch = device_get_softc(request->parent); 208 struct ata_device *atadev = device_get_softc(request->dev); 209 210 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 211 u_int16_t temp; 212 213 request->u.ata.count = ATA_IDX_INW(ch, ATA_COUNT); 214 temp = ATA_IDX_INW(ch, ATA_SECTOR); 215 request->u.ata.lba = (u_int64_t)(temp & 0x00ff) | 216 ((u_int64_t)(temp & 0xff00) << 24); 217 temp = ATA_IDX_INW(ch, ATA_CYL_LSB); 218 request->u.ata.lba |= ((u_int64_t)(temp & 0x00ff) << 8) | 219 ((u_int64_t)(temp & 0xff00) << 32); 220 temp = ATA_IDX_INW(ch, ATA_CYL_MSB); 221 request->u.ata.lba |= ((u_int64_t)(temp & 0x00ff) << 16) | 222 ((u_int64_t)(temp & 0xff00) << 40); 223 } 224 else { 225 request->u.ata.count = ATA_IDX_INW(ch, ATA_COUNT) & 0x00ff; 226 request->u.ata.lba = (ATA_IDX_INW(ch, ATA_SECTOR) & 0x00ff) | 227 ((ATA_IDX_INW(ch, ATA_CYL_LSB) & 0x00ff) << 8) | 228 ((ATA_IDX_INW(ch, ATA_CYL_MSB) & 0x00ff) << 16) | 229 ((ATA_IDX_INW(ch, ATA_DRIVE) & 0xf) << 24); 230 } 231 } 232 233 static void 234 ata_serverworks_tf_write(struct ata_request *request) 235 { 236 struct ata_channel *ch = device_get_softc(request->parent); 237 struct ata_device *atadev = device_get_softc(request->dev); 238 239 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 240 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature); 241 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count); 242 ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) | 243 (request->u.ata.lba & 0x00ff)); 244 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) | 245 ((request->u.ata.lba >> 8) & 0x00ff)); 246 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) | 247 ((request->u.ata.lba >> 16) & 0x00ff)); 248 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(atadev->unit)); 249 } 250 else { 251 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature); 252 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count); 253 if (atadev->flags & ATA_D_USE_CHS) { 254 int heads, sectors; 255 256 if (atadev->param.atavalid & ATA_FLAG_54_58) { 257 heads = atadev->param.current_heads; 258 sectors = atadev->param.current_sectors; 259 } 260 else { 261 heads = atadev->param.heads; 262 sectors = atadev->param.sectors; 263 } 264 ATA_IDX_OUTW(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1); 265 ATA_IDX_OUTW(ch, ATA_CYL_LSB, 266 (request->u.ata.lba / (sectors * heads))); 267 ATA_IDX_OUTW(ch, ATA_CYL_MSB, 268 (request->u.ata.lba / (sectors * heads)) >> 8); 269 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(atadev->unit) | 270 (((request->u.ata.lba% (sectors * heads)) / 271 sectors) & 0xf)); 272 } 273 else { 274 ATA_IDX_OUTW(ch, ATA_SECTOR, request->u.ata.lba); 275 ATA_IDX_OUTW(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 276 ATA_IDX_OUTW(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 277 ATA_IDX_OUTW(ch, ATA_DRIVE, 278 ATA_D_IBM | ATA_D_LBA | ATA_DEV(atadev->unit) | 279 ((request->u.ata.lba >> 24) & 0x0f)); 280 } 281 } 282 } 283 284 static void 285 ata_serverworks_setmode(device_t dev, int mode) 286 { 287 device_t gparent = GRANDPARENT(dev); 288 struct ata_pci_controller *ctlr = device_get_softc(gparent); 289 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 290 struct ata_device *atadev = device_get_softc(dev); 291 int devno = (ch->unit << 1) + atadev->unit; 292 int offset = (devno ^ 0x01) << 3; 293 int error; 294 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20, 295 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; 296 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 }; 297 298 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 299 300 mode = ata_check_80pin(dev, mode); 301 302 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 303 304 if (bootverbose) 305 device_printf(dev, "%ssetting %s on %s chip\n", 306 (error) ? "FAILURE " : "", 307 ata_mode2str(mode), ctlr->chip->text); 308 if (!error) { 309 if (mode >= ATA_UDMA0) { 310 pci_write_config(gparent, 0x56, 311 (pci_read_config(gparent, 0x56, 2) & 312 ~(0xf << (devno << 2))) | 313 ((mode & ATA_MODE_MASK) << (devno << 2)), 2); 314 pci_write_config(gparent, 0x54, 315 pci_read_config(gparent, 0x54, 1) | 316 (0x01 << devno), 1); 317 pci_write_config(gparent, 0x44, 318 (pci_read_config(gparent, 0x44, 4) & 319 ~(0xff << offset)) | 320 (dmatimings[2] << offset), 4); 321 } 322 else if (mode >= ATA_WDMA0) { 323 pci_write_config(gparent, 0x54, 324 pci_read_config(gparent, 0x54, 1) & 325 ~(0x01 << devno), 1); 326 pci_write_config(gparent, 0x44, 327 (pci_read_config(gparent, 0x44, 4) & 328 ~(0xff << offset)) | 329 (dmatimings[mode & ATA_MODE_MASK] << offset), 4); 330 } 331 else 332 pci_write_config(gparent, 0x54, 333 pci_read_config(gparent, 0x54, 1) & 334 ~(0x01 << devno), 1); 335 336 pci_write_config(gparent, 0x40, 337 (pci_read_config(gparent, 0x40, 4) & 338 ~(0xff << offset)) | 339 (piotimings[ata_mode2idx(mode)] << offset), 4); 340 atadev->mode = mode; 341 } 342 } 343 344 ATA_DECLARE_DRIVER(ata_serverworks); 345