1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification, immediately at the beginning of the file. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/module.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/ata.h> 37 #include <sys/bus.h> 38 #include <sys/endian.h> 39 #include <sys/malloc.h> 40 #include <sys/lock.h> 41 #include <sys/mutex.h> 42 #include <sys/sema.h> 43 #include <sys/taskqueue.h> 44 #include <vm/uma.h> 45 #include <machine/stdarg.h> 46 #include <machine/resource.h> 47 #include <machine/bus.h> 48 #include <sys/rman.h> 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcireg.h> 51 #include <dev/ata/ata-all.h> 52 #include <dev/ata/ata-pci.h> 53 #include <ata_if.h> 54 55 /* local prototypes */ 56 static int ata_promise_chipinit(device_t dev); 57 static int ata_promise_ch_attach(device_t dev); 58 static int ata_promise_status(device_t dev); 59 static int ata_promise_dmastart(struct ata_request *request); 60 static int ata_promise_dmastop(struct ata_request *request); 61 static void ata_promise_dmareset(device_t dev); 62 static int ata_promise_setmode(device_t dev, int target, int mode); 63 static int ata_promise_tx2_ch_attach(device_t dev); 64 static int ata_promise_tx2_status(device_t dev); 65 static int ata_promise_mio_ch_attach(device_t dev); 66 static int ata_promise_mio_ch_detach(device_t dev); 67 static void ata_promise_mio_intr(void *data); 68 static int ata_promise_mio_status(device_t dev); 69 static int ata_promise_mio_command(struct ata_request *request); 70 static void ata_promise_mio_reset(device_t dev); 71 static int ata_promise_mio_pm_read(device_t dev, int port, int reg, u_int32_t *result); 72 static int ata_promise_mio_pm_write(device_t dev, int port, int reg, u_int32_t result); 73 static u_int32_t ata_promise_mio_softreset(device_t dev, int port); 74 static void ata_promise_mio_dmainit(device_t dev); 75 static void ata_promise_mio_setprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 76 static int ata_promise_mio_setmode(device_t dev, int target, int mode); 77 static int ata_promise_mio_getrev(device_t dev, int target); 78 static void ata_promise_sx4_intr(void *data); 79 static int ata_promise_sx4_command(struct ata_request *request); 80 static int ata_promise_apkt(u_int8_t *bytep, struct ata_request *request); 81 static void ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt); 82 static void ata_promise_next_hpkt(struct ata_pci_controller *ctlr); 83 84 /* misc defines */ 85 #define PR_OLD 0 86 #define PR_NEW 1 87 #define PR_TX 2 88 #define PR_MIO 3 89 #define PR_TX4 0x01 90 #define PR_SX4X 0x02 91 #define PR_SX6K 0x04 92 #define PR_PATA 0x08 93 #define PR_CMBO 0x10 94 #define PR_CMBO2 0x20 95 #define PR_SATA 0x40 96 #define PR_SATA2 0x80 97 98 /* 99 * Promise chipset support functions 100 */ 101 #define ATA_PDC_APKT_OFFSET 0x00000010 102 #define ATA_PDC_HPKT_OFFSET 0x00000040 103 #define ATA_PDC_ASG_OFFSET 0x00000080 104 #define ATA_PDC_LSG_OFFSET 0x000000c0 105 #define ATA_PDC_HSG_OFFSET 0x00000100 106 #define ATA_PDC_CHN_OFFSET 0x00000400 107 #define ATA_PDC_BUF_BASE 0x00400000 108 #define ATA_PDC_BUF_OFFSET 0x00100000 109 #define ATA_PDC_MAX_HPKT 8 110 #define ATA_PDC_WRITE_REG 0x00 111 #define ATA_PDC_WRITE_CTL 0x0e 112 #define ATA_PDC_WRITE_END 0x08 113 #define ATA_PDC_WAIT_NBUSY 0x10 114 #define ATA_PDC_WAIT_READY 0x18 115 #define ATA_PDC_1B 0x20 116 #define ATA_PDC_2B 0x40 117 118 struct host_packet { 119 u_int32_t addr; 120 TAILQ_ENTRY(host_packet) chain; 121 }; 122 123 struct ata_promise_sx4 { 124 struct mtx mtx; 125 TAILQ_HEAD(, host_packet) queue; 126 int busy; 127 }; 128 129 static int 130 ata_promise_probe(device_t dev) 131 { 132 struct ata_pci_controller *ctlr = device_get_softc(dev); 133 const struct ata_chip_id *idx; 134 static const struct ata_chip_id ids[] = 135 {{ ATA_PDC20246, 0, PR_OLD, 0x00, ATA_UDMA2, "PDC20246" }, 136 { ATA_PDC20262, 0, PR_NEW, 0x00, ATA_UDMA4, "PDC20262" }, 137 { ATA_PDC20263, 0, PR_NEW, 0x00, ATA_UDMA4, "PDC20263" }, 138 { ATA_PDC20265, 0, PR_NEW, 0x00, ATA_UDMA5, "PDC20265" }, 139 { ATA_PDC20267, 0, PR_NEW, 0x00, ATA_UDMA5, "PDC20267" }, 140 { ATA_PDC20268, 0, PR_TX, PR_TX4, ATA_UDMA5, "PDC20268" }, 141 { ATA_PDC20269, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20269" }, 142 { ATA_PDC20270, 0, PR_TX, PR_TX4, ATA_UDMA5, "PDC20270" }, 143 { ATA_PDC20271, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20271" }, 144 { ATA_PDC20275, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20275" }, 145 { ATA_PDC20276, 0, PR_TX, PR_SX6K, ATA_UDMA6, "PDC20276" }, 146 { ATA_PDC20277, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20277" }, 147 { ATA_PDC20318, 0, PR_MIO, PR_SATA, ATA_SA150, "PDC20318" }, 148 { ATA_PDC20319, 0, PR_MIO, PR_SATA, ATA_SA150, "PDC20319" }, 149 { ATA_PDC20371, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20371" }, 150 { ATA_PDC20375, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20375" }, 151 { ATA_PDC20376, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20376" }, 152 { ATA_PDC20377, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20377" }, 153 { ATA_PDC20378, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20378" }, 154 { ATA_PDC20379, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20379" }, 155 { ATA_PDC20571, 0, PR_MIO, PR_CMBO2, ATA_SA150, "PDC20571" }, 156 { ATA_PDC20575, 0, PR_MIO, PR_CMBO2, ATA_SA150, "PDC20575" }, 157 { ATA_PDC20579, 0, PR_MIO, PR_CMBO2, ATA_SA150, "PDC20579" }, 158 { ATA_PDC20771, 0, PR_MIO, PR_CMBO2, ATA_SA300, "PDC20771" }, 159 { ATA_PDC40775, 0, PR_MIO, PR_CMBO2, ATA_SA300, "PDC40775" }, 160 { ATA_PDC20617, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20617" }, 161 { ATA_PDC20618, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20618" }, 162 { ATA_PDC20619, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20619" }, 163 { ATA_PDC20620, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20620" }, 164 { ATA_PDC20621, 0, PR_MIO, PR_SX4X, ATA_UDMA5, "PDC20621" }, 165 { ATA_PDC20622, 0, PR_MIO, PR_SX4X, ATA_SA150, "PDC20622" }, 166 { ATA_PDC40518, 0, PR_MIO, PR_SATA2, ATA_SA150, "PDC40518" }, 167 { ATA_PDC40519, 0, PR_MIO, PR_SATA2, ATA_SA150, "PDC40519" }, 168 { ATA_PDC40718, 0, PR_MIO, PR_SATA2, ATA_SA300, "PDC40718" }, 169 { ATA_PDC40719, 0, PR_MIO, PR_SATA2, ATA_SA300, "PDC40719" }, 170 { ATA_PDC40779, 0, PR_MIO, PR_SATA2, ATA_SA300, "PDC40779" }, 171 { 0, 0, 0, 0, 0, 0}}; 172 char buffer[64]; 173 uintptr_t devid = 0; 174 175 if (pci_get_vendor(dev) != ATA_PROMISE_ID) 176 return ENXIO; 177 178 if (!(idx = ata_match_chip(dev, ids))) 179 return ENXIO; 180 181 /* if we are on a SuperTrak SX6000 dont attach */ 182 if ((idx->cfg2 & PR_SX6K) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE && 183 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), 184 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && 185 devid == ATA_I960RM) 186 return ENXIO; 187 188 strcpy(buffer, "Promise "); 189 strcat(buffer, idx->text); 190 191 /* if we are on a FastTrak TX4, adjust the interrupt resource */ 192 if ((idx->cfg2 & PR_TX4) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE && 193 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), 194 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && 195 ((devid == ATA_DEC_21150) || (devid == ATA_DEC_21150_1))) { 196 static rman_res_t start = 0, end = 0; 197 198 if (pci_get_slot(dev) == 1) { 199 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end); 200 strcat(buffer, " (channel 0+1)"); 201 } 202 else if (pci_get_slot(dev) == 2 && start && end) { 203 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end); 204 strcat(buffer, " (channel 2+3)"); 205 } 206 else { 207 start = end = 0; 208 } 209 } 210 sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma)); 211 device_set_desc_copy(dev, buffer); 212 ctlr->chip = idx; 213 ctlr->chipinit = ata_promise_chipinit; 214 return (BUS_PROBE_LOW_PRIORITY); 215 } 216 217 static int 218 ata_promise_chipinit(device_t dev) 219 { 220 struct ata_pci_controller *ctlr = device_get_softc(dev); 221 int stat_reg; 222 223 if (ata_setup_interrupt(dev, ata_generic_intr)) 224 return ENXIO; 225 226 switch (ctlr->chip->cfg1) { 227 case PR_NEW: 228 /* setup clocks */ 229 ATA_OUTB(ctlr->r_res1, 0x11, ATA_INB(ctlr->r_res1, 0x11) | 0x0a); 230 /* FALLTHROUGH */ 231 232 case PR_OLD: 233 /* enable burst mode */ 234 ATA_OUTB(ctlr->r_res1, 0x1f, ATA_INB(ctlr->r_res1, 0x1f) | 0x01); 235 ctlr->ch_attach = ata_promise_ch_attach; 236 ctlr->ch_detach = ata_pci_ch_detach; 237 ctlr->setmode = ata_promise_setmode; 238 return 0; 239 240 case PR_TX: 241 ctlr->ch_attach = ata_promise_tx2_ch_attach; 242 ctlr->ch_detach = ata_pci_ch_detach; 243 ctlr->setmode = ata_promise_setmode; 244 return 0; 245 246 case PR_MIO: 247 ctlr->r_type1 = SYS_RES_MEMORY; 248 ctlr->r_rid1 = PCIR_BAR(4); 249 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 250 &ctlr->r_rid1, RF_ACTIVE))) 251 goto failnfree; 252 253 #ifdef __sparc64__ 254 if (ctlr->chip->cfg2 == PR_SX4X && 255 !bus_space_map(rman_get_bustag(ctlr->r_res1), 256 rman_get_bushandle(ctlr->r_res1), rman_get_size(ctlr->r_res1), 257 BUS_SPACE_MAP_LINEAR, NULL)) 258 goto failnfree; 259 #endif 260 261 ctlr->r_type2 = SYS_RES_MEMORY; 262 ctlr->r_rid2 = PCIR_BAR(3); 263 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 264 &ctlr->r_rid2, RF_ACTIVE))) 265 goto failnfree; 266 267 if (ctlr->chip->cfg2 == PR_SX4X) { 268 struct ata_promise_sx4 *hpkt; 269 u_int32_t dimm = ATA_INL(ctlr->r_res2, 0x000c0080); 270 271 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) || 272 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, NULL, 273 ata_promise_sx4_intr, ctlr, &ctlr->handle)) { 274 device_printf(dev, "unable to setup interrupt\n"); 275 goto failnfree; 276 } 277 278 /* print info about cache memory */ 279 device_printf(dev, "DIMM size %dMB @ 0x%08x%s\n", 280 (((dimm >> 16) & 0xff)-((dimm >> 24) & 0xff)+1) << 4, 281 ((dimm >> 24) & 0xff), 282 ATA_INL(ctlr->r_res2, 0x000c0088) & (1<<16) ? 283 " ECC enabled" : "" ); 284 285 /* adjust cache memory parameters */ 286 ATA_OUTL(ctlr->r_res2, 0x000c000c, 287 (ATA_INL(ctlr->r_res2, 0x000c000c) & 0xffff0000)); 288 289 /* setup host packet controls */ 290 hpkt = malloc(sizeof(struct ata_promise_sx4), 291 M_ATAPCI, M_NOWAIT | M_ZERO); 292 if (hpkt == NULL) { 293 device_printf(dev, "Cannot allocate HPKT\n"); 294 goto failnfree; 295 } 296 mtx_init(&hpkt->mtx, "ATA promise HPKT lock", NULL, MTX_DEF); 297 TAILQ_INIT(&hpkt->queue); 298 hpkt->busy = 0; 299 ctlr->chipset_data = hpkt; 300 ctlr->ch_attach = ata_promise_mio_ch_attach; 301 ctlr->ch_detach = ata_promise_mio_ch_detach; 302 ctlr->reset = ata_promise_mio_reset; 303 ctlr->setmode = ata_promise_setmode; 304 ctlr->channels = 4; 305 return 0; 306 } 307 308 /* mio type controllers need an interrupt intercept */ 309 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) || 310 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, NULL, 311 ata_promise_mio_intr, ctlr, &ctlr->handle)) { 312 device_printf(dev, "unable to setup interrupt\n"); 313 goto failnfree; 314 } 315 316 switch (ctlr->chip->cfg2) { 317 case PR_PATA: 318 ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x01) > 0) + 319 ((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 2; 320 goto sata150; 321 case PR_CMBO: 322 ctlr->channels = 3; 323 goto sata150; 324 case PR_SATA: 325 ctlr->channels = 4; 326 sata150: 327 stat_reg = 0x6c; 328 break; 329 330 case PR_CMBO2: 331 ctlr->channels = 3; 332 goto sataii; 333 case PR_SATA2: 334 default: 335 ctlr->channels = 4; 336 sataii: 337 stat_reg = 0x60; 338 break; 339 } 340 341 /* prime fake interrupt register */ 342 ctlr->chipset_data = (void *)(uintptr_t)0xffffffff; 343 344 /* clear SATA status and unmask interrupts */ 345 ATA_OUTL(ctlr->r_res2, stat_reg, 0x000000ff); 346 347 /* enable "long burst length" on gen2 chips */ 348 if ((ctlr->chip->cfg2 == PR_SATA2) || (ctlr->chip->cfg2 == PR_CMBO2)) 349 ATA_OUTL(ctlr->r_res2, 0x44, ATA_INL(ctlr->r_res2, 0x44) | 0x2000); 350 351 ctlr->ch_attach = ata_promise_mio_ch_attach; 352 ctlr->ch_detach = ata_promise_mio_ch_detach; 353 ctlr->reset = ata_promise_mio_reset; 354 ctlr->setmode = ata_promise_mio_setmode; 355 ctlr->getrev = ata_promise_mio_getrev; 356 357 return 0; 358 } 359 360 failnfree: 361 if (ctlr->r_res2) 362 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2); 363 if (ctlr->r_res1) 364 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1, ctlr->r_res1); 365 return ENXIO; 366 } 367 368 static int 369 ata_promise_ch_attach(device_t dev) 370 { 371 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 372 struct ata_channel *ch = device_get_softc(dev); 373 374 if (ata_pci_ch_attach(dev)) 375 return ENXIO; 376 377 if (ctlr->chip->cfg1 == PR_NEW) { 378 ch->dma.start = ata_promise_dmastart; 379 ch->dma.stop = ata_promise_dmastop; 380 ch->dma.reset = ata_promise_dmareset; 381 } 382 383 ch->hw.status = ata_promise_status; 384 ch->flags |= ATA_NO_ATAPI_DMA; 385 ch->flags |= ATA_CHECKS_CABLE; 386 return 0; 387 } 388 389 static int 390 ata_promise_status(device_t dev) 391 { 392 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 393 struct ata_channel *ch = device_get_softc(dev); 394 395 if (ATA_INL(ctlr->r_res1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)) { 396 return ata_pci_status(dev); 397 } 398 return 0; 399 } 400 401 static int 402 ata_promise_dmastart(struct ata_request *request) 403 { 404 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 405 struct ata_channel *ch = device_get_softc(request->parent); 406 407 if (request->flags & ATA_R_48BIT) { 408 ATA_OUTB(ctlr->r_res1, 0x11, 409 ATA_INB(ctlr->r_res1, 0x11) | (ch->unit ? 0x08 : 0x02)); 410 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 411 ((request->flags & ATA_R_READ) ? 0x05000000 : 0x06000000) | 412 (request->bytecount >> 1)); 413 } 414 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) | 415 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 416 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, request->dma->sg_bus); 417 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 418 ((request->flags & ATA_R_READ) ? ATA_BMCMD_WRITE_READ : 0) | 419 ATA_BMCMD_START_STOP); 420 ch->dma.flags |= ATA_DMA_ACTIVE; 421 return 0; 422 } 423 424 static int 425 ata_promise_dmastop(struct ata_request *request) 426 { 427 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 428 struct ata_channel *ch = device_get_softc(request->parent); 429 int error; 430 431 if (request->flags & ATA_R_48BIT) { 432 ATA_OUTB(ctlr->r_res1, 0x11, 433 ATA_INB(ctlr->r_res1, 0x11) & ~(ch->unit ? 0x08 : 0x02)); 434 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 0); 435 } 436 error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT); 437 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 438 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 439 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 440 ch->dma.flags &= ~ATA_DMA_ACTIVE; 441 return error; 442 } 443 444 static void 445 ata_promise_dmareset(device_t dev) 446 { 447 struct ata_channel *ch = device_get_softc(dev); 448 449 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 450 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 451 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 452 ch->flags &= ~ATA_DMA_ACTIVE; 453 } 454 455 static int 456 ata_promise_setmode(device_t dev, int target, int mode) 457 { 458 device_t parent = device_get_parent(dev); 459 struct ata_pci_controller *ctlr = device_get_softc(parent); 460 struct ata_channel *ch = device_get_softc(dev); 461 int devno = (ch->unit << 1) + target; 462 static const uint32_t timings[][2] = { 463 /* PR_OLD PR_NEW mode */ 464 { 0x004ff329, 0x004fff2f }, /* PIO 0 */ 465 { 0x004fec25, 0x004ff82a }, /* PIO 1 */ 466 { 0x004fe823, 0x004ff026 }, /* PIO 2 */ 467 { 0x004fe622, 0x004fec24 }, /* PIO 3 */ 468 { 0x004fe421, 0x004fe822 }, /* PIO 4 */ 469 { 0x004567f3, 0x004acef6 }, /* MWDMA 0 */ 470 { 0x004467f3, 0x0048cef6 }, /* MWDMA 1 */ 471 { 0x004367f3, 0x0046cef6 }, /* MWDMA 2 */ 472 { 0x004367f3, 0x0046cef6 }, /* UDMA 0 */ 473 { 0x004247f3, 0x00448ef6 }, /* UDMA 1 */ 474 { 0x004127f3, 0x00436ef6 }, /* UDMA 2 */ 475 { 0, 0x00424ef6 }, /* UDMA 3 */ 476 { 0, 0x004127f3 }, /* UDMA 4 */ 477 { 0, 0x004127f3 } /* UDMA 5 */ 478 }; 479 480 mode = min(mode, ctlr->chip->max_dma); 481 482 switch (ctlr->chip->cfg1) { 483 case PR_OLD: 484 case PR_NEW: 485 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 486 (pci_read_config(parent, 0x50, 2) & 487 (ch->unit ? 1 << 11 : 1 << 10))) { 488 ata_print_cable(dev, "controller"); 489 mode = ATA_UDMA2; 490 } 491 break; 492 493 case PR_TX: 494 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b); 495 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 496 ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x04) { 497 ata_print_cable(dev, "controller"); 498 mode = ATA_UDMA2; 499 } 500 break; 501 502 case PR_MIO: 503 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 504 (ATA_INL(ctlr->r_res2, 505 (ctlr->chip->cfg2 & PR_SX4X ? 0x000c0260 : 0x0260) + 506 (ch->unit << 7)) & 0x01000000)) { 507 ata_print_cable(dev, "controller"); 508 mode = ATA_UDMA2; 509 } 510 break; 511 } 512 513 if (ctlr->chip->cfg1 < PR_TX) 514 pci_write_config(parent, 0x60 + (devno << 2), 515 timings[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); 516 return (mode); 517 } 518 519 static int 520 ata_promise_tx2_ch_attach(device_t dev) 521 { 522 struct ata_channel *ch = device_get_softc(dev); 523 524 if (ata_pci_ch_attach(dev)) 525 return ENXIO; 526 527 ch->hw.status = ata_promise_tx2_status; 528 ch->flags |= ATA_CHECKS_CABLE; 529 return 0; 530 } 531 532 static int 533 ata_promise_tx2_status(device_t dev) 534 { 535 struct ata_channel *ch = device_get_softc(dev); 536 537 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b); 538 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) { 539 return ata_pci_status(dev); 540 } 541 return 0; 542 } 543 544 static int 545 ata_promise_mio_ch_attach(device_t dev) 546 { 547 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 548 struct ata_channel *ch = device_get_softc(dev); 549 int offset = (ctlr->chip->cfg2 & PR_SX4X) ? 0x000c0000 : 0; 550 int i; 551 552 ata_promise_mio_dmainit(dev); 553 554 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 555 ch->r_io[i].res = ctlr->r_res2; 556 ch->r_io[i].offset = offset + 0x0200 + (i << 2) + (ch->unit << 7); 557 } 558 ch->r_io[ATA_CONTROL].res = ctlr->r_res2; 559 ch->r_io[ATA_CONTROL].offset = offset + 0x0238 + (ch->unit << 7); 560 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 561 ata_default_registers(dev); 562 if ((ctlr->chip->cfg2 & (PR_SATA | PR_SATA2)) || 563 ((ctlr->chip->cfg2 & (PR_CMBO | PR_CMBO2)) && ch->unit < 2)) { 564 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 565 ch->r_io[ATA_SSTATUS].offset = 0x400 + (ch->unit << 8); 566 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 567 ch->r_io[ATA_SERROR].offset = 0x404 + (ch->unit << 8); 568 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 569 ch->r_io[ATA_SCONTROL].offset = 0x408 + (ch->unit << 8); 570 ch->flags |= ATA_NO_SLAVE; 571 ch->flags |= ATA_SATA; 572 } 573 ch->flags |= ATA_USE_16BIT; 574 ch->flags |= ATA_CHECKS_CABLE; 575 576 ata_generic_hw(dev); 577 if (ctlr->chip->cfg2 & PR_SX4X) { 578 ch->hw.command = ata_promise_sx4_command; 579 } 580 else { 581 ch->hw.command = ata_promise_mio_command; 582 ch->hw.status = ata_promise_mio_status; 583 ch->hw.softreset = ata_promise_mio_softreset; 584 ch->hw.pm_read = ata_promise_mio_pm_read; 585 ch->hw.pm_write = ata_promise_mio_pm_write; 586 } 587 return 0; 588 } 589 590 static int 591 ata_promise_mio_ch_detach(device_t dev) 592 { 593 594 ata_dmafini(dev); 595 return (0); 596 } 597 598 static void 599 ata_promise_mio_intr(void *data) 600 { 601 struct ata_pci_controller *ctlr = data; 602 struct ata_channel *ch; 603 u_int32_t vector; 604 int unit; 605 606 /* 607 * since reading interrupt status register on early "mio" chips 608 * clears the status bits we cannot read it for each channel later on 609 * in the generic interrupt routine. 610 */ 611 vector = ATA_INL(ctlr->r_res2, 0x040); 612 ATA_OUTL(ctlr->r_res2, 0x040, vector); 613 ctlr->chipset_data = (void *)(uintptr_t)vector; 614 615 for (unit = 0; unit < ctlr->channels; unit++) { 616 if ((ch = ctlr->interrupt[unit].argument)) 617 ctlr->interrupt[unit].function(ch); 618 } 619 620 ctlr->chipset_data = (void *)(uintptr_t)0xffffffff; 621 } 622 623 static int 624 ata_promise_mio_status(device_t dev) 625 { 626 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 627 struct ata_channel *ch = device_get_softc(dev); 628 u_int32_t stat_reg, vector, status; 629 630 switch (ctlr->chip->cfg2) { 631 case PR_PATA: 632 case PR_CMBO: 633 case PR_SATA: 634 stat_reg = 0x6c; 635 break; 636 case PR_CMBO2: 637 case PR_SATA2: 638 default: 639 stat_reg = 0x60; 640 break; 641 } 642 643 /* read and acknowledge interrupt */ 644 vector = (uint32_t)(uintptr_t)ctlr->chipset_data; 645 646 /* read and clear interface status */ 647 status = ATA_INL(ctlr->r_res2, stat_reg); 648 ATA_OUTL(ctlr->r_res2, stat_reg, status & (0x00000011 << ch->unit)); 649 650 /* check for and handle disconnect events */ 651 if (status & (0x00000001 << ch->unit)) { 652 if (bootverbose) 653 device_printf(dev, "DISCONNECT requested\n"); 654 taskqueue_enqueue(taskqueue_thread, &ch->conntask); 655 } 656 657 /* check for and handle connect events */ 658 if (status & (0x00000010 << ch->unit)) { 659 if (bootverbose) 660 device_printf(dev, "CONNECT requested\n"); 661 taskqueue_enqueue(taskqueue_thread, &ch->conntask); 662 } 663 664 /* do we have any device action ? */ 665 return (vector & (1 << (ch->unit + 1))); 666 } 667 668 static int 669 ata_promise_mio_command(struct ata_request *request) 670 { 671 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 672 struct ata_channel *ch = device_get_softc(request->parent); 673 674 u_int32_t *wordp = (u_int32_t *)ch->dma.work; 675 676 ATA_OUTL(ctlr->r_res2, (ch->unit + 1) << 2, 0x00000001); 677 678 if ((ctlr->chip->cfg2 == PR_SATA2) || 679 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) { 680 /* set portmultiplier port */ 681 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), request->unit & 0x0f); 682 } 683 684 /* XXX SOS add ATAPI commands support later */ 685 switch (request->u.ata.command) { 686 default: 687 return ata_generic_command(request); 688 689 case ATA_READ_DMA: 690 case ATA_READ_DMA48: 691 wordp[0] = htole32(0x04 | ((ch->unit + 1) << 16) | (0x00 << 24)); 692 break; 693 694 case ATA_WRITE_DMA: 695 case ATA_WRITE_DMA48: 696 wordp[0] = htole32(0x00 | ((ch->unit + 1) << 16) | (0x00 << 24)); 697 break; 698 } 699 wordp[1] = htole32(request->dma->sg_bus); 700 wordp[2] = 0; 701 ata_promise_apkt((u_int8_t*)wordp, request); 702 703 ATA_OUTL(ctlr->r_res2, 0x0240 + (ch->unit << 7), ch->dma.work_bus); 704 return 0; 705 } 706 707 static void 708 ata_promise_mio_reset(device_t dev) 709 { 710 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 711 struct ata_channel *ch = device_get_softc(dev); 712 struct ata_promise_sx4 *hpktp; 713 714 switch (ctlr->chip->cfg2) { 715 case PR_SX4X: 716 717 /* softreset channel ATA module */ 718 hpktp = ctlr->chipset_data; 719 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), ch->unit + 1); 720 ata_udelay(1000); 721 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), 722 (ATA_INL(ctlr->r_res2, 0xc0260 + (ch->unit << 7)) & 723 ~0x00003f9f) | (ch->unit + 1)); 724 725 /* softreset HOST module */ /* XXX SOS what about other outstandings */ 726 mtx_lock(&hpktp->mtx); 727 ATA_OUTL(ctlr->r_res2, 0xc012c, 728 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f) | (1 << 11)); 729 DELAY(10); 730 ATA_OUTL(ctlr->r_res2, 0xc012c, 731 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f)); 732 hpktp->busy = 0; 733 mtx_unlock(&hpktp->mtx); 734 ata_generic_reset(dev); 735 break; 736 737 case PR_PATA: 738 case PR_CMBO: 739 case PR_SATA: 740 if ((ctlr->chip->cfg2 == PR_SATA) || 741 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2))) { 742 743 /* mask plug/unplug intr */ 744 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00110000 << ch->unit)); 745 } 746 747 /* softreset channels ATA module */ 748 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11)); 749 ata_udelay(10000); 750 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), 751 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) & 752 ~0x00003f9f) | (ch->unit + 1)); 753 754 if ((ctlr->chip->cfg2 == PR_SATA) || 755 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2))) { 756 757 if (ata_sata_phy_reset(dev, -1, 1)) 758 ata_generic_reset(dev); 759 else 760 ch->devices = 0; 761 762 /* reset and enable plug/unplug intr */ 763 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00000011 << ch->unit)); 764 } 765 else 766 ata_generic_reset(dev); 767 break; 768 769 case PR_CMBO2: 770 case PR_SATA2: 771 if ((ctlr->chip->cfg2 == PR_SATA2) || 772 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) { 773 /* set portmultiplier port */ 774 //ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f); 775 776 /* mask plug/unplug intr */ 777 ATA_OUTL(ctlr->r_res2, 0x060, (0x00110000 << ch->unit)); 778 } 779 780 /* softreset channels ATA module */ 781 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11)); 782 ata_udelay(10000); 783 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), 784 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) & 785 ~0x00003f9f) | (ch->unit + 1)); 786 787 if ((ctlr->chip->cfg2 == PR_SATA2) || 788 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) { 789 790 /* set PHY mode to "improved" */ 791 ATA_OUTL(ctlr->r_res2, 0x414 + (ch->unit << 8), 792 (ATA_INL(ctlr->r_res2, 0x414 + (ch->unit << 8)) & 793 ~0x00000003) | 0x00000001); 794 795 if (ata_sata_phy_reset(dev, -1, 1)) { 796 u_int32_t signature = ch->hw.softreset(dev, ATA_PM); 797 798 if (1 | bootverbose) 799 device_printf(dev, "SIGNATURE: %08x\n", signature); 800 801 switch (signature >> 16) { 802 case 0x0000: 803 ch->devices = ATA_ATA_MASTER; 804 break; 805 case 0x9669: 806 ch->devices = ATA_PORTMULTIPLIER; 807 ata_pm_identify(dev); 808 break; 809 case 0xeb14: 810 ch->devices = ATA_ATAPI_MASTER; 811 break; 812 default: /* SOS XXX */ 813 if (bootverbose) 814 device_printf(dev, 815 "No signature, assuming disk device\n"); 816 ch->devices = ATA_ATA_MASTER; 817 } 818 if (bootverbose) 819 device_printf(dev, "promise_mio_reset devices=%08x\n", 820 ch->devices); 821 822 } else 823 ch->devices = 0; 824 825 /* reset and enable plug/unplug intr */ 826 ATA_OUTL(ctlr->r_res2, 0x060, (0x00000011 << ch->unit)); 827 828 ///* set portmultiplier port */ 829 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x00); 830 } 831 else 832 ata_generic_reset(dev); 833 break; 834 835 } 836 } 837 838 static int 839 ata_promise_mio_pm_read(device_t dev, int port, int reg, u_int32_t *result) 840 { 841 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 842 struct ata_channel *ch = device_get_softc(dev); 843 int timeout = 0; 844 845 if (port < 0) { 846 *result = ATA_IDX_INL(ch, reg); 847 return (0); 848 } 849 if (port < ATA_PM) { 850 switch (reg) { 851 case ATA_SSTATUS: 852 reg = 0; 853 break; 854 case ATA_SERROR: 855 reg = 1; 856 break; 857 case ATA_SCONTROL: 858 reg = 2; 859 break; 860 default: 861 return (EINVAL); 862 } 863 } 864 /* set portmultiplier port */ 865 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f); 866 867 ATA_IDX_OUTB(ch, ATA_FEATURE, reg); 868 ATA_IDX_OUTB(ch, ATA_DRIVE, port); 869 870 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_READ_PM); 871 872 while (timeout < 1000000) { 873 u_int8_t status = ATA_IDX_INB(ch, ATA_STATUS); 874 if (!(status & ATA_S_BUSY)) 875 break; 876 timeout += 1000; 877 DELAY(1000); 878 } 879 if (timeout >= 1000000) 880 return ATA_E_ABORT; 881 882 *result = ATA_IDX_INB(ch, ATA_COUNT) | 883 (ATA_IDX_INB(ch, ATA_SECTOR) << 8) | 884 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 16) | 885 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 24); 886 return 0; 887 } 888 889 static int 890 ata_promise_mio_pm_write(device_t dev, int port, int reg, u_int32_t value) 891 { 892 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 893 struct ata_channel *ch = device_get_softc(dev); 894 int timeout = 0; 895 896 if (port < 0) { 897 ATA_IDX_OUTL(ch, reg, value); 898 return (0); 899 } 900 if (port < ATA_PM) { 901 switch (reg) { 902 case ATA_SSTATUS: 903 reg = 0; 904 break; 905 case ATA_SERROR: 906 reg = 1; 907 break; 908 case ATA_SCONTROL: 909 reg = 2; 910 break; 911 default: 912 return (EINVAL); 913 } 914 } 915 /* set portmultiplier port */ 916 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f); 917 918 ATA_IDX_OUTB(ch, ATA_FEATURE, reg); 919 ATA_IDX_OUTB(ch, ATA_DRIVE, port); 920 ATA_IDX_OUTB(ch, ATA_COUNT, value & 0xff); 921 ATA_IDX_OUTB(ch, ATA_SECTOR, (value >> 8) & 0xff); 922 ATA_IDX_OUTB(ch, ATA_CYL_LSB, (value >> 16) & 0xff); 923 ATA_IDX_OUTB(ch, ATA_CYL_MSB, (value >> 24) & 0xff); 924 925 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_WRITE_PM); 926 927 while (timeout < 1000000) { 928 u_int8_t status = ATA_IDX_INB(ch, ATA_STATUS); 929 if (!(status & ATA_S_BUSY)) 930 break; 931 timeout += 1000; 932 DELAY(1000); 933 } 934 if (timeout >= 1000000) 935 return ATA_E_ABORT; 936 937 return ATA_IDX_INB(ch, ATA_ERROR); 938 } 939 940 /* must be called with ATA channel locked and state_mtx held */ 941 static u_int32_t 942 ata_promise_mio_softreset(device_t dev, int port) 943 { 944 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 945 struct ata_channel *ch = device_get_softc(dev); 946 int timeout; 947 948 /* set portmultiplier port */ 949 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), port & 0x0f); 950 951 /* softreset device on this channel */ 952 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_MASTER)); 953 DELAY(10); 954 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS | ATA_A_RESET); 955 ata_udelay(10000); 956 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS); 957 ata_udelay(150000); 958 ATA_IDX_INB(ch, ATA_ERROR); 959 960 /* wait for BUSY to go inactive */ 961 for (timeout = 0; timeout < 100; timeout++) { 962 u_int8_t /* err, */ stat; 963 964 /* err = */ ATA_IDX_INB(ch, ATA_ERROR); 965 stat = ATA_IDX_INB(ch, ATA_STATUS); 966 967 //if (stat == err && timeout > (stat & ATA_S_BUSY ? 100 : 10)) 968 //break; 969 970 if (!(stat & ATA_S_BUSY)) { 971 //if ((err & 0x7f) == ATA_E_ILI) { 972 return ATA_IDX_INB(ch, ATA_COUNT) | 973 (ATA_IDX_INB(ch, ATA_SECTOR) << 8) | 974 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 16) | 975 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 24); 976 //} 977 //else if (stat & 0x0f) { 978 //stat |= ATA_S_BUSY; 979 //} 980 } 981 982 if (!(stat & ATA_S_BUSY) || (stat == 0xff && timeout > 10)) 983 break; 984 ata_udelay(100000); 985 } 986 return -1; 987 } 988 989 static void 990 ata_promise_mio_dmainit(device_t dev) 991 { 992 struct ata_channel *ch = device_get_softc(dev); 993 994 /* note start and stop are not used here */ 995 ch->dma.setprd = ata_promise_mio_setprd; 996 ch->dma.max_iosize = 65536; 997 ata_dmainit(dev); 998 } 999 1000 #define MAXLASTSGSIZE (32 * sizeof(u_int32_t)) 1001 static void 1002 ata_promise_mio_setprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 1003 { 1004 struct ata_dmasetprd_args *args = xsc; 1005 struct ata_dma_prdentry *prd = args->dmatab; 1006 int i; 1007 1008 if ((args->error = error)) 1009 return; 1010 1011 for (i = 0; i < nsegs; i++) { 1012 prd[i].addr = htole32(segs[i].ds_addr); 1013 prd[i].count = htole32(segs[i].ds_len); 1014 } 1015 if (segs[i - 1].ds_len > MAXLASTSGSIZE) { 1016 //printf("split last SG element of %u\n", segs[i - 1].ds_len); 1017 prd[i - 1].count = htole32(segs[i - 1].ds_len - MAXLASTSGSIZE); 1018 prd[i].count = htole32(MAXLASTSGSIZE); 1019 prd[i].addr = htole32(segs[i - 1].ds_addr + 1020 (segs[i - 1].ds_len - MAXLASTSGSIZE)); 1021 nsegs++; 1022 i++; 1023 } 1024 prd[i - 1].count |= htole32(ATA_DMA_EOT); 1025 KASSERT(nsegs <= ATA_DMA_ENTRIES, ("too many DMA segment entries\n")); 1026 args->nsegs = nsegs; 1027 } 1028 1029 static int 1030 ata_promise_mio_setmode(device_t dev, int target, int mode) 1031 { 1032 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1033 struct ata_channel *ch = device_get_softc(dev); 1034 1035 if ( (ctlr->chip->cfg2 == PR_SATA) || 1036 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2)) || 1037 (ctlr->chip->cfg2 == PR_SATA2) || 1038 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) 1039 mode = ata_sata_setmode(dev, target, mode); 1040 else 1041 mode = ata_promise_setmode(dev, target, mode); 1042 return (mode); 1043 } 1044 1045 static int 1046 ata_promise_mio_getrev(device_t dev, int target) 1047 { 1048 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1049 struct ata_channel *ch = device_get_softc(dev); 1050 1051 if ( (ctlr->chip->cfg2 == PR_SATA) || 1052 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2)) || 1053 (ctlr->chip->cfg2 == PR_SATA2) || 1054 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) 1055 return (ata_sata_getrev(dev, target)); 1056 else 1057 return (0); 1058 } 1059 1060 static void 1061 ata_promise_sx4_intr(void *data) 1062 { 1063 struct ata_pci_controller *ctlr = data; 1064 struct ata_channel *ch; 1065 u_int32_t vector = ATA_INL(ctlr->r_res2, 0x000c0480); 1066 int unit; 1067 1068 for (unit = 0; unit < ctlr->channels; unit++) { 1069 if (vector & (1 << (unit + 1))) 1070 if ((ch = ctlr->interrupt[unit].argument)) 1071 ctlr->interrupt[unit].function(ch); 1072 if (vector & (1 << (unit + 5))) 1073 if ((ch = ctlr->interrupt[unit].argument)) 1074 ata_promise_queue_hpkt(ctlr, 1075 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + 1076 ATA_PDC_HPKT_OFFSET)); 1077 if (vector & (1 << (unit + 9))) { 1078 ata_promise_next_hpkt(ctlr); 1079 if ((ch = ctlr->interrupt[unit].argument)) 1080 ctlr->interrupt[unit].function(ch); 1081 } 1082 if (vector & (1 << (unit + 13))) { 1083 ata_promise_next_hpkt(ctlr); 1084 if ((ch = ctlr->interrupt[unit].argument)) 1085 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 1086 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + 1087 ATA_PDC_APKT_OFFSET)); 1088 } 1089 } 1090 } 1091 1092 static int 1093 ata_promise_sx4_command(struct ata_request *request) 1094 { 1095 device_t gparent = device_get_parent(request->parent); 1096 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1097 struct ata_channel *ch = device_get_softc(request->parent); 1098 struct ata_dma_prdentry *prd; 1099 caddr_t window = rman_get_virtual(ctlr->r_res1); 1100 u_int32_t *wordp; 1101 int i, idx, length = 0; 1102 1103 /* XXX SOS add ATAPI commands support later */ 1104 switch (request->u.ata.command) { 1105 1106 default: 1107 return -1; 1108 1109 case ATA_ATA_IDENTIFY: 1110 case ATA_READ: 1111 case ATA_READ48: 1112 case ATA_READ_MUL: 1113 case ATA_READ_MUL48: 1114 case ATA_WRITE: 1115 case ATA_WRITE48: 1116 case ATA_WRITE_MUL: 1117 case ATA_WRITE_MUL48: 1118 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001); 1119 return ata_generic_command(request); 1120 1121 case ATA_SETFEATURES: 1122 case ATA_FLUSHCACHE: 1123 case ATA_FLUSHCACHE48: 1124 case ATA_SLEEP: 1125 case ATA_SET_MULTI: 1126 wordp = (u_int32_t *) 1127 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET); 1128 wordp[0] = htole32(0x08 | ((ch->unit + 1)<<16) | (0x00 << 24)); 1129 wordp[1] = 0; 1130 wordp[2] = 0; 1131 ata_promise_apkt((u_int8_t *)wordp, request); 1132 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001); 1133 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001); 1134 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 1135 htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_APKT_OFFSET)); 1136 return 0; 1137 1138 case ATA_READ_DMA: 1139 case ATA_READ_DMA48: 1140 case ATA_WRITE_DMA: 1141 case ATA_WRITE_DMA48: 1142 prd = request->dma->sg; 1143 wordp = (u_int32_t *) 1144 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HSG_OFFSET); 1145 i = idx = 0; 1146 do { 1147 wordp[idx++] = prd[i].addr; 1148 wordp[idx++] = prd[i].count; 1149 length += (prd[i].count & ~ATA_DMA_EOT); 1150 } while (!(prd[i++].count & ATA_DMA_EOT)); 1151 1152 wordp = (u_int32_t *) 1153 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_LSG_OFFSET); 1154 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE); 1155 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT); 1156 1157 wordp = (u_int32_t *) 1158 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_ASG_OFFSET); 1159 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE); 1160 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT); 1161 1162 wordp = (u_int32_t *) 1163 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET); 1164 if (request->flags & ATA_R_READ) 1165 wordp[0] = htole32(0x14 | ((ch->unit+9)<<16) | ((ch->unit+5)<<24)); 1166 if (request->flags & ATA_R_WRITE) 1167 wordp[0] = htole32(0x00 | ((ch->unit+13)<<16) | (0x00<<24)); 1168 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_HSG_OFFSET); 1169 wordp[2] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_LSG_OFFSET); 1170 wordp[3] = 0; 1171 1172 wordp = (u_int32_t *) 1173 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET); 1174 if (request->flags & ATA_R_READ) 1175 wordp[0] = htole32(0x04 | ((ch->unit+5)<<16) | (0x00<<24)); 1176 if (request->flags & ATA_R_WRITE) 1177 wordp[0] = htole32(0x10 | ((ch->unit+1)<<16) | ((ch->unit+13)<<24)); 1178 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_ASG_OFFSET); 1179 wordp[2] = 0; 1180 ata_promise_apkt((u_int8_t *)wordp, request); 1181 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001); 1182 1183 if (request->flags & ATA_R_READ) { 1184 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+5)<<2), 0x00000001); 1185 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+9)<<2), 0x00000001); 1186 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 1187 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET)); 1188 } 1189 if (request->flags & ATA_R_WRITE) { 1190 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+1)<<2), 0x00000001); 1191 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+13)<<2), 0x00000001); 1192 ata_promise_queue_hpkt(ctlr, 1193 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET)); 1194 } 1195 return 0; 1196 } 1197 } 1198 1199 static int 1200 ata_promise_apkt(u_int8_t *bytep, struct ata_request *request) 1201 { 1202 int i = 12; 1203 1204 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_PDC_WAIT_NBUSY|ATA_DRIVE; 1205 bytep[i++] = ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit); 1206 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_CTL; 1207 bytep[i++] = ATA_A_4BIT; 1208 1209 if (request->flags & ATA_R_48BIT) { 1210 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_FEATURE; 1211 bytep[i++] = request->u.ata.feature >> 8; 1212 bytep[i++] = request->u.ata.feature; 1213 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_COUNT; 1214 bytep[i++] = request->u.ata.count >> 8; 1215 bytep[i++] = request->u.ata.count; 1216 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_SECTOR; 1217 bytep[i++] = request->u.ata.lba >> 24; 1218 bytep[i++] = request->u.ata.lba; 1219 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_LSB; 1220 bytep[i++] = request->u.ata.lba >> 32; 1221 bytep[i++] = request->u.ata.lba >> 8; 1222 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_MSB; 1223 bytep[i++] = request->u.ata.lba >> 40; 1224 bytep[i++] = request->u.ata.lba >> 16; 1225 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE; 1226 bytep[i++] = ATA_D_LBA | ATA_DEV(request->unit); 1227 } 1228 else { 1229 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_FEATURE; 1230 bytep[i++] = request->u.ata.feature; 1231 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_COUNT; 1232 bytep[i++] = request->u.ata.count; 1233 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_SECTOR; 1234 bytep[i++] = request->u.ata.lba; 1235 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_LSB; 1236 bytep[i++] = request->u.ata.lba >> 8; 1237 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_MSB; 1238 bytep[i++] = request->u.ata.lba >> 16; 1239 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE; 1240 bytep[i++] = ATA_D_LBA | ATA_D_IBM | ATA_DEV(request->unit) | 1241 ((request->u.ata.lba >> 24)&0xf); 1242 } 1243 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_END | ATA_COMMAND; 1244 bytep[i++] = request->u.ata.command; 1245 return i; 1246 } 1247 1248 static void 1249 ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt) 1250 { 1251 struct ata_promise_sx4 *hpktp = ctlr->chipset_data; 1252 1253 mtx_lock(&hpktp->mtx); 1254 if (hpktp->busy) { 1255 struct host_packet *hp = 1256 malloc(sizeof(struct host_packet), M_TEMP, M_NOWAIT | M_ZERO); 1257 hp->addr = hpkt; 1258 TAILQ_INSERT_TAIL(&hpktp->queue, hp, chain); 1259 } 1260 else { 1261 hpktp->busy = 1; 1262 ATA_OUTL(ctlr->r_res2, 0x000c0100, hpkt); 1263 } 1264 mtx_unlock(&hpktp->mtx); 1265 } 1266 1267 static void 1268 ata_promise_next_hpkt(struct ata_pci_controller *ctlr) 1269 { 1270 struct ata_promise_sx4 *hpktp = ctlr->chipset_data; 1271 struct host_packet *hp; 1272 1273 mtx_lock(&hpktp->mtx); 1274 if ((hp = TAILQ_FIRST(&hpktp->queue))) { 1275 TAILQ_REMOVE(&hpktp->queue, hp, chain); 1276 ATA_OUTL(ctlr->r_res2, 0x000c0100, hp->addr); 1277 free(hp, M_TEMP); 1278 } 1279 else 1280 hpktp->busy = 0; 1281 mtx_unlock(&hpktp->mtx); 1282 } 1283 1284 ATA_DECLARE_DRIVER(ata_promise); 1285