1 /*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ata.h" 31 #include <sys/param.h> 32 #include <sys/module.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/ata.h> 36 #include <sys/bus.h> 37 #include <sys/endian.h> 38 #include <sys/malloc.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/sema.h> 42 #include <sys/taskqueue.h> 43 #include <vm/uma.h> 44 #include <machine/stdarg.h> 45 #include <machine/resource.h> 46 #include <machine/bus.h> 47 #include <sys/rman.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/ata/ata-all.h> 51 #include <dev/ata/ata-pci.h> 52 #include <ata_if.h> 53 54 /* local prototypes */ 55 static int ata_promise_chipinit(device_t dev); 56 static int ata_promise_ch_attach(device_t dev); 57 static int ata_promise_status(device_t dev); 58 static int ata_promise_dmastart(struct ata_request *request); 59 static int ata_promise_dmastop(struct ata_request *request); 60 static void ata_promise_dmareset(device_t dev); 61 static int ata_promise_setmode(device_t dev, int target, int mode); 62 static int ata_promise_tx2_ch_attach(device_t dev); 63 static int ata_promise_tx2_status(device_t dev); 64 static int ata_promise_mio_ch_attach(device_t dev); 65 static int ata_promise_mio_ch_detach(device_t dev); 66 static void ata_promise_mio_intr(void *data); 67 static int ata_promise_mio_status(device_t dev); 68 static int ata_promise_mio_command(struct ata_request *request); 69 static void ata_promise_mio_reset(device_t dev); 70 static int ata_promise_mio_pm_read(device_t dev, int port, int reg, u_int32_t *result); 71 static int ata_promise_mio_pm_write(device_t dev, int port, int reg, u_int32_t result); 72 static u_int32_t ata_promise_mio_softreset(device_t dev, int port); 73 static void ata_promise_mio_dmainit(device_t dev); 74 static void ata_promise_mio_setprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 75 static int ata_promise_mio_setmode(device_t dev, int target, int mode); 76 static void ata_promise_sx4_intr(void *data); 77 static int ata_promise_sx4_command(struct ata_request *request); 78 static int ata_promise_apkt(u_int8_t *bytep, struct ata_request *request); 79 static void ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt); 80 static void ata_promise_next_hpkt(struct ata_pci_controller *ctlr); 81 82 /* misc defines */ 83 #define PR_OLD 0 84 #define PR_NEW 1 85 #define PR_TX 2 86 #define PR_MIO 3 87 #define PR_TX4 0x01 88 #define PR_SX4X 0x02 89 #define PR_SX6K 0x04 90 #define PR_PATA 0x08 91 #define PR_CMBO 0x10 92 #define PR_CMBO2 0x20 93 #define PR_SATA 0x40 94 #define PR_SATA2 0x80 95 96 97 /* 98 * Promise chipset support functions 99 */ 100 #define ATA_PDC_APKT_OFFSET 0x00000010 101 #define ATA_PDC_HPKT_OFFSET 0x00000040 102 #define ATA_PDC_ASG_OFFSET 0x00000080 103 #define ATA_PDC_LSG_OFFSET 0x000000c0 104 #define ATA_PDC_HSG_OFFSET 0x00000100 105 #define ATA_PDC_CHN_OFFSET 0x00000400 106 #define ATA_PDC_BUF_BASE 0x00400000 107 #define ATA_PDC_BUF_OFFSET 0x00100000 108 #define ATA_PDC_MAX_HPKT 8 109 #define ATA_PDC_WRITE_REG 0x00 110 #define ATA_PDC_WRITE_CTL 0x0e 111 #define ATA_PDC_WRITE_END 0x08 112 #define ATA_PDC_WAIT_NBUSY 0x10 113 #define ATA_PDC_WAIT_READY 0x18 114 #define ATA_PDC_1B 0x20 115 #define ATA_PDC_2B 0x40 116 117 struct host_packet { 118 u_int32_t addr; 119 TAILQ_ENTRY(host_packet) chain; 120 }; 121 122 struct ata_promise_sx4 { 123 struct mtx mtx; 124 TAILQ_HEAD(, host_packet) queue; 125 int busy; 126 }; 127 128 static int 129 ata_promise_probe(device_t dev) 130 { 131 struct ata_pci_controller *ctlr = device_get_softc(dev); 132 struct ata_chip_id *idx; 133 static struct ata_chip_id ids[] = 134 {{ ATA_PDC20246, 0, PR_OLD, 0x00, ATA_UDMA2, "PDC20246" }, 135 { ATA_PDC20262, 0, PR_NEW, 0x00, ATA_UDMA4, "PDC20262" }, 136 { ATA_PDC20263, 0, PR_NEW, 0x00, ATA_UDMA4, "PDC20263" }, 137 { ATA_PDC20265, 0, PR_NEW, 0x00, ATA_UDMA5, "PDC20265" }, 138 { ATA_PDC20267, 0, PR_NEW, 0x00, ATA_UDMA5, "PDC20267" }, 139 { ATA_PDC20268, 0, PR_TX, PR_TX4, ATA_UDMA5, "PDC20268" }, 140 { ATA_PDC20269, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20269" }, 141 { ATA_PDC20270, 0, PR_TX, PR_TX4, ATA_UDMA5, "PDC20270" }, 142 { ATA_PDC20271, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20271" }, 143 { ATA_PDC20275, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20275" }, 144 { ATA_PDC20276, 0, PR_TX, PR_SX6K, ATA_UDMA6, "PDC20276" }, 145 { ATA_PDC20277, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20277" }, 146 { ATA_PDC20318, 0, PR_MIO, PR_SATA, ATA_SA150, "PDC20318" }, 147 { ATA_PDC20319, 0, PR_MIO, PR_SATA, ATA_SA150, "PDC20319" }, 148 { ATA_PDC20371, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20371" }, 149 { ATA_PDC20375, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20375" }, 150 { ATA_PDC20376, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20376" }, 151 { ATA_PDC20377, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20377" }, 152 { ATA_PDC20378, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20378" }, 153 { ATA_PDC20379, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20379" }, 154 { ATA_PDC20571, 0, PR_MIO, PR_CMBO2, ATA_SA150, "PDC20571" }, 155 { ATA_PDC20575, 0, PR_MIO, PR_CMBO2, ATA_SA150, "PDC20575" }, 156 { ATA_PDC20579, 0, PR_MIO, PR_CMBO2, ATA_SA150, "PDC20579" }, 157 { ATA_PDC20771, 0, PR_MIO, PR_CMBO2, ATA_SA300, "PDC20771" }, 158 { ATA_PDC40775, 0, PR_MIO, PR_CMBO2, ATA_SA300, "PDC40775" }, 159 { ATA_PDC20617, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20617" }, 160 { ATA_PDC20618, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20618" }, 161 { ATA_PDC20619, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20619" }, 162 { ATA_PDC20620, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20620" }, 163 { ATA_PDC20621, 0, PR_MIO, PR_SX4X, ATA_UDMA5, "PDC20621" }, 164 { ATA_PDC20622, 0, PR_MIO, PR_SX4X, ATA_SA150, "PDC20622" }, 165 { ATA_PDC40518, 0, PR_MIO, PR_SATA2, ATA_SA150, "PDC40518" }, 166 { ATA_PDC40519, 0, PR_MIO, PR_SATA2, ATA_SA150, "PDC40519" }, 167 { ATA_PDC40718, 0, PR_MIO, PR_SATA2, ATA_SA300, "PDC40718" }, 168 { ATA_PDC40719, 0, PR_MIO, PR_SATA2, ATA_SA300, "PDC40719" }, 169 { ATA_PDC40779, 0, PR_MIO, PR_SATA2, ATA_SA300, "PDC40779" }, 170 { 0, 0, 0, 0, 0, 0}}; 171 char buffer[64]; 172 uintptr_t devid = 0; 173 174 if (pci_get_vendor(dev) != ATA_PROMISE_ID) 175 return ENXIO; 176 177 if (!(idx = ata_match_chip(dev, ids))) 178 return ENXIO; 179 180 /* if we are on a SuperTrak SX6000 dont attach */ 181 if ((idx->cfg2 & PR_SX6K) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE && 182 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), 183 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && 184 devid == ATA_I960RM) 185 return ENXIO; 186 187 strcpy(buffer, "Promise "); 188 strcat(buffer, idx->text); 189 190 /* if we are on a FastTrak TX4, adjust the interrupt resource */ 191 if ((idx->cfg2 & PR_TX4) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE && 192 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), 193 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && 194 ((devid == ATA_DEC_21150) || (devid == ATA_DEC_21150_1))) { 195 static long start = 0, end = 0; 196 197 if (pci_get_slot(dev) == 1) { 198 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end); 199 strcat(buffer, " (channel 0+1)"); 200 } 201 else if (pci_get_slot(dev) == 2 && start && end) { 202 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end); 203 strcat(buffer, " (channel 2+3)"); 204 } 205 else { 206 start = end = 0; 207 } 208 } 209 sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma)); 210 device_set_desc_copy(dev, buffer); 211 ctlr->chip = idx; 212 ctlr->chipinit = ata_promise_chipinit; 213 return (BUS_PROBE_DEFAULT); 214 } 215 216 static int 217 ata_promise_chipinit(device_t dev) 218 { 219 struct ata_pci_controller *ctlr = device_get_softc(dev); 220 int fake_reg, stat_reg; 221 222 if (ata_setup_interrupt(dev, ata_generic_intr)) 223 return ENXIO; 224 225 switch (ctlr->chip->cfg1) { 226 case PR_NEW: 227 /* setup clocks */ 228 ATA_OUTB(ctlr->r_res1, 0x11, ATA_INB(ctlr->r_res1, 0x11) | 0x0a); 229 /* FALLTHROUGH */ 230 231 case PR_OLD: 232 /* enable burst mode */ 233 ATA_OUTB(ctlr->r_res1, 0x1f, ATA_INB(ctlr->r_res1, 0x1f) | 0x01); 234 ctlr->ch_attach = ata_promise_ch_attach; 235 ctlr->ch_detach = ata_pci_ch_detach; 236 ctlr->setmode = ata_promise_setmode; 237 return 0; 238 239 case PR_TX: 240 ctlr->ch_attach = ata_promise_tx2_ch_attach; 241 ctlr->ch_detach = ata_pci_ch_detach; 242 ctlr->setmode = ata_promise_setmode; 243 return 0; 244 245 case PR_MIO: 246 ctlr->r_type1 = SYS_RES_MEMORY; 247 ctlr->r_rid1 = PCIR_BAR(4); 248 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 249 &ctlr->r_rid1, RF_ACTIVE))) 250 goto failnfree; 251 252 ctlr->r_type2 = SYS_RES_MEMORY; 253 ctlr->r_rid2 = PCIR_BAR(3); 254 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 255 &ctlr->r_rid2, RF_ACTIVE))) 256 goto failnfree; 257 258 if (ctlr->chip->cfg2 == PR_SX4X) { 259 struct ata_promise_sx4 *hpkt; 260 u_int32_t dimm = ATA_INL(ctlr->r_res2, 0x000c0080); 261 262 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) || 263 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, NULL, 264 ata_promise_sx4_intr, ctlr, &ctlr->handle)) { 265 device_printf(dev, "unable to setup interrupt\n"); 266 goto failnfree; 267 } 268 269 /* print info about cache memory */ 270 device_printf(dev, "DIMM size %dMB @ 0x%08x%s\n", 271 (((dimm >> 16) & 0xff)-((dimm >> 24) & 0xff)+1) << 4, 272 ((dimm >> 24) & 0xff), 273 ATA_INL(ctlr->r_res2, 0x000c0088) & (1<<16) ? 274 " ECC enabled" : "" ); 275 276 /* adjust cache memory parameters */ 277 ATA_OUTL(ctlr->r_res2, 0x000c000c, 278 (ATA_INL(ctlr->r_res2, 0x000c000c) & 0xffff0000)); 279 280 /* setup host packet controls */ 281 hpkt = malloc(sizeof(struct ata_promise_sx4), 282 M_TEMP, M_NOWAIT | M_ZERO); 283 mtx_init(&hpkt->mtx, "ATA promise HPKT lock", NULL, MTX_DEF); 284 TAILQ_INIT(&hpkt->queue); 285 hpkt->busy = 0; 286 ctlr->chipset_data = hpkt; 287 ctlr->ch_attach = ata_promise_mio_ch_attach; 288 ctlr->ch_detach = ata_promise_mio_ch_detach; 289 ctlr->reset = ata_promise_mio_reset; 290 ctlr->setmode = ata_promise_setmode; 291 ctlr->channels = 4; 292 return 0; 293 } 294 295 /* mio type controllers need an interrupt intercept */ 296 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) || 297 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, NULL, 298 ata_promise_mio_intr, ctlr, &ctlr->handle)) { 299 device_printf(dev, "unable to setup interrupt\n"); 300 goto failnfree; 301 } 302 303 switch (ctlr->chip->cfg2) { 304 case PR_PATA: 305 ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x01) > 0) + 306 ((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 2; 307 goto sata150; 308 case PR_CMBO: 309 ctlr->channels = 3; 310 goto sata150; 311 case PR_SATA: 312 ctlr->channels = 4; 313 sata150: 314 fake_reg = 0x60; 315 stat_reg = 0x6c; 316 break; 317 318 case PR_CMBO2: 319 ctlr->channels = 3; 320 goto sataii; 321 case PR_SATA2: 322 default: 323 ctlr->channels = 4; 324 sataii: 325 fake_reg = 0x54; 326 stat_reg = 0x60; 327 break; 328 } 329 330 /* prime fake interrupt register */ 331 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff); 332 333 /* clear SATA status and unmask interrupts */ 334 ATA_OUTL(ctlr->r_res2, stat_reg, 0x000000ff); 335 336 /* enable "long burst length" on gen2 chips */ 337 if ((ctlr->chip->cfg2 == PR_SATA2) || (ctlr->chip->cfg2 == PR_CMBO2)) 338 ATA_OUTL(ctlr->r_res2, 0x44, ATA_INL(ctlr->r_res2, 0x44) | 0x2000); 339 340 ctlr->ch_attach = ata_promise_mio_ch_attach; 341 ctlr->ch_detach = ata_promise_mio_ch_detach; 342 ctlr->reset = ata_promise_mio_reset; 343 ctlr->setmode = ata_promise_mio_setmode; 344 345 return 0; 346 } 347 348 failnfree: 349 if (ctlr->r_res2) 350 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2); 351 if (ctlr->r_res1) 352 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1, ctlr->r_res1); 353 return ENXIO; 354 } 355 356 static int 357 ata_promise_ch_attach(device_t dev) 358 { 359 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 360 struct ata_channel *ch = device_get_softc(dev); 361 362 if (ata_pci_ch_attach(dev)) 363 return ENXIO; 364 365 if (ctlr->chip->cfg1 == PR_NEW) { 366 ch->dma.start = ata_promise_dmastart; 367 ch->dma.stop = ata_promise_dmastop; 368 ch->dma.reset = ata_promise_dmareset; 369 } 370 371 ch->hw.status = ata_promise_status; 372 ch->flags |= ATA_NO_ATAPI_DMA; 373 ch->flags |= ATA_CHECKS_CABLE; 374 return 0; 375 } 376 377 static int 378 ata_promise_status(device_t dev) 379 { 380 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 381 struct ata_channel *ch = device_get_softc(dev); 382 383 if (ATA_INL(ctlr->r_res1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)) { 384 return ata_pci_status(dev); 385 } 386 return 0; 387 } 388 389 static int 390 ata_promise_dmastart(struct ata_request *request) 391 { 392 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 393 struct ata_channel *ch = device_get_softc(request->parent); 394 395 if (request->flags & ATA_R_48BIT) { 396 ATA_OUTB(ctlr->r_res1, 0x11, 397 ATA_INB(ctlr->r_res1, 0x11) | (ch->unit ? 0x08 : 0x02)); 398 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 399 ((request->flags & ATA_R_READ) ? 0x05000000 : 0x06000000) | 400 (request->bytecount >> 1)); 401 } 402 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) | 403 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 404 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, request->dma->sg_bus); 405 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 406 ((request->flags & ATA_R_READ) ? ATA_BMCMD_WRITE_READ : 0) | 407 ATA_BMCMD_START_STOP); 408 ch->dma.flags |= ATA_DMA_ACTIVE; 409 return 0; 410 } 411 412 static int 413 ata_promise_dmastop(struct ata_request *request) 414 { 415 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 416 struct ata_channel *ch = device_get_softc(request->parent); 417 int error; 418 419 if (request->flags & ATA_R_48BIT) { 420 ATA_OUTB(ctlr->r_res1, 0x11, 421 ATA_INB(ctlr->r_res1, 0x11) & ~(ch->unit ? 0x08 : 0x02)); 422 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 0); 423 } 424 error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT); 425 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 426 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 427 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 428 ch->dma.flags &= ~ATA_DMA_ACTIVE; 429 return error; 430 } 431 432 static void 433 ata_promise_dmareset(device_t dev) 434 { 435 struct ata_channel *ch = device_get_softc(dev); 436 437 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 438 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 439 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 440 ch->flags &= ~ATA_DMA_ACTIVE; 441 } 442 443 static int 444 ata_promise_setmode(device_t dev, int target, int mode) 445 { 446 device_t parent = device_get_parent(dev); 447 struct ata_pci_controller *ctlr = device_get_softc(parent); 448 struct ata_channel *ch = device_get_softc(dev); 449 int devno = (ch->unit << 1) + target; 450 u_int32_t timings[][2] = { 451 /* PR_OLD PR_NEW mode */ 452 { 0x004ff329, 0x004fff2f }, /* PIO 0 */ 453 { 0x004fec25, 0x004ff82a }, /* PIO 1 */ 454 { 0x004fe823, 0x004ff026 }, /* PIO 2 */ 455 { 0x004fe622, 0x004fec24 }, /* PIO 3 */ 456 { 0x004fe421, 0x004fe822 }, /* PIO 4 */ 457 { 0x004567f3, 0x004acef6 }, /* MWDMA 0 */ 458 { 0x004467f3, 0x0048cef6 }, /* MWDMA 1 */ 459 { 0x004367f3, 0x0046cef6 }, /* MWDMA 2 */ 460 { 0x004367f3, 0x0046cef6 }, /* UDMA 0 */ 461 { 0x004247f3, 0x00448ef6 }, /* UDMA 1 */ 462 { 0x004127f3, 0x00436ef6 }, /* UDMA 2 */ 463 { 0, 0x00424ef6 }, /* UDMA 3 */ 464 { 0, 0x004127f3 }, /* UDMA 4 */ 465 { 0, 0x004127f3 } /* UDMA 5 */ 466 }; 467 468 mode = min(mode, ctlr->chip->max_dma); 469 470 switch (ctlr->chip->cfg1) { 471 case PR_OLD: 472 case PR_NEW: 473 if (mode > ATA_UDMA2 && (pci_read_config(parent, 0x50, 2) & 474 (ch->unit ? 1 << 11 : 1 << 10))) { 475 ata_print_cable(dev, "controller"); 476 mode = ATA_UDMA2; 477 } 478 break; 479 480 case PR_TX: 481 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b); 482 if (mode > ATA_UDMA2 && 483 ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x04) { 484 ata_print_cable(dev, "controller"); 485 mode = ATA_UDMA2; 486 } 487 break; 488 489 case PR_MIO: 490 if (mode > ATA_UDMA2 && 491 (ATA_INL(ctlr->r_res2, 492 (ctlr->chip->cfg2 & PR_SX4X ? 0x000c0260 : 0x0260) + 493 (ch->unit << 7)) & 0x01000000)) { 494 ata_print_cable(dev, "controller"); 495 mode = ATA_UDMA2; 496 } 497 break; 498 } 499 500 if (ctlr->chip->cfg1 < PR_TX) 501 pci_write_config(parent, 0x60 + (devno << 2), 502 timings[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); 503 return (mode); 504 } 505 506 static int 507 ata_promise_tx2_ch_attach(device_t dev) 508 { 509 struct ata_channel *ch = device_get_softc(dev); 510 511 if (ata_pci_ch_attach(dev)) 512 return ENXIO; 513 514 ch->hw.status = ata_promise_tx2_status; 515 ch->flags |= ATA_CHECKS_CABLE; 516 return 0; 517 } 518 519 static int 520 ata_promise_tx2_status(device_t dev) 521 { 522 struct ata_channel *ch = device_get_softc(dev); 523 524 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b); 525 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) { 526 return ata_pci_status(dev); 527 } 528 return 0; 529 } 530 531 static int 532 ata_promise_mio_ch_attach(device_t dev) 533 { 534 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 535 struct ata_channel *ch = device_get_softc(dev); 536 int offset = (ctlr->chip->cfg2 & PR_SX4X) ? 0x000c0000 : 0; 537 int i; 538 539 ata_promise_mio_dmainit(dev); 540 541 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 542 ch->r_io[i].res = ctlr->r_res2; 543 ch->r_io[i].offset = offset + 0x0200 + (i << 2) + (ch->unit << 7); 544 } 545 ch->r_io[ATA_CONTROL].res = ctlr->r_res2; 546 ch->r_io[ATA_CONTROL].offset = offset + 0x0238 + (ch->unit << 7); 547 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 548 ata_default_registers(dev); 549 if ((ctlr->chip->cfg2 & (PR_SATA | PR_SATA2)) || 550 ((ctlr->chip->cfg2 & (PR_CMBO | PR_CMBO2)) && ch->unit < 2)) { 551 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 552 ch->r_io[ATA_SSTATUS].offset = 0x400 + (ch->unit << 8); 553 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 554 ch->r_io[ATA_SERROR].offset = 0x404 + (ch->unit << 8); 555 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 556 ch->r_io[ATA_SCONTROL].offset = 0x408 + (ch->unit << 8); 557 ch->flags |= ATA_NO_SLAVE; 558 ch->flags |= ATA_SATA; 559 } 560 ch->flags |= ATA_USE_16BIT; 561 ch->flags |= ATA_CHECKS_CABLE; 562 563 ata_generic_hw(dev); 564 if (ctlr->chip->cfg2 & PR_SX4X) { 565 ch->hw.command = ata_promise_sx4_command; 566 } 567 else { 568 ch->hw.command = ata_promise_mio_command; 569 ch->hw.status = ata_promise_mio_status; 570 ch->hw.softreset = ata_promise_mio_softreset; 571 ch->hw.pm_read = ata_promise_mio_pm_read; 572 ch->hw.pm_write = ata_promise_mio_pm_write; 573 } 574 return 0; 575 } 576 577 static int 578 ata_promise_mio_ch_detach(device_t dev) 579 { 580 581 ata_dmafini(dev); 582 return (0); 583 } 584 585 static void 586 ata_promise_mio_intr(void *data) 587 { 588 struct ata_pci_controller *ctlr = data; 589 struct ata_channel *ch; 590 u_int32_t vector; 591 int unit, fake_reg; 592 593 switch (ctlr->chip->cfg2) { 594 case PR_PATA: 595 case PR_CMBO: 596 case PR_SATA: 597 fake_reg = 0x60; 598 break; 599 case PR_CMBO2: 600 case PR_SATA2: 601 default: 602 fake_reg = 0x54; 603 break; 604 } 605 606 /* 607 * since reading interrupt status register on early "mio" chips 608 * clears the status bits we cannot read it for each channel later on 609 * in the generic interrupt routine. 610 * store the bits in an unused register in the chip so we can read 611 * it from there safely to get around this "feature". 612 */ 613 vector = ATA_INL(ctlr->r_res2, 0x040); 614 ATA_OUTL(ctlr->r_res2, 0x040, vector); 615 ATA_OUTL(ctlr->r_res2, fake_reg, vector); 616 617 for (unit = 0; unit < ctlr->channels; unit++) { 618 if ((ch = ctlr->interrupt[unit].argument)) 619 ctlr->interrupt[unit].function(ch); 620 } 621 622 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff); 623 } 624 625 static int 626 ata_promise_mio_status(device_t dev) 627 { 628 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 629 struct ata_channel *ch = device_get_softc(dev); 630 u_int32_t fake_reg, stat_reg, vector, status; 631 632 switch (ctlr->chip->cfg2) { 633 case PR_PATA: 634 case PR_CMBO: 635 case PR_SATA: 636 fake_reg = 0x60; 637 stat_reg = 0x6c; 638 break; 639 case PR_CMBO2: 640 case PR_SATA2: 641 default: 642 fake_reg = 0x54; 643 stat_reg = 0x60; 644 break; 645 } 646 647 /* read and acknowledge interrupt */ 648 vector = ATA_INL(ctlr->r_res2, fake_reg); 649 650 /* read and clear interface status */ 651 status = ATA_INL(ctlr->r_res2, stat_reg); 652 ATA_OUTL(ctlr->r_res2, stat_reg, status & (0x00000011 << ch->unit)); 653 654 /* check for and handle disconnect events */ 655 if (status & (0x00000001 << ch->unit)) { 656 if (bootverbose) 657 device_printf(dev, "DISCONNECT requested\n"); 658 taskqueue_enqueue(taskqueue_thread, &ch->conntask); 659 } 660 661 /* check for and handle connect events */ 662 if (status & (0x00000010 << ch->unit)) { 663 if (bootverbose) 664 device_printf(dev, "CONNECT requested\n"); 665 taskqueue_enqueue(taskqueue_thread, &ch->conntask); 666 } 667 668 /* do we have any device action ? */ 669 return (vector & (1 << (ch->unit + 1))); 670 } 671 672 static int 673 ata_promise_mio_command(struct ata_request *request) 674 { 675 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 676 struct ata_channel *ch = device_get_softc(request->parent); 677 678 u_int32_t *wordp = (u_int32_t *)ch->dma.work; 679 680 ATA_OUTL(ctlr->r_res2, (ch->unit + 1) << 2, 0x00000001); 681 682 if ((ctlr->chip->cfg2 == PR_SATA2) || 683 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) { 684 /* set portmultiplier port */ 685 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), request->unit & 0x0f); 686 } 687 688 /* XXX SOS add ATAPI commands support later */ 689 switch (request->u.ata.command) { 690 default: 691 return ata_generic_command(request); 692 693 case ATA_READ_DMA: 694 case ATA_READ_DMA48: 695 wordp[0] = htole32(0x04 | ((ch->unit + 1) << 16) | (0x00 << 24)); 696 break; 697 698 case ATA_WRITE_DMA: 699 case ATA_WRITE_DMA48: 700 wordp[0] = htole32(0x00 | ((ch->unit + 1) << 16) | (0x00 << 24)); 701 break; 702 } 703 wordp[1] = htole32(request->dma->sg_bus); 704 wordp[2] = 0; 705 ata_promise_apkt((u_int8_t*)wordp, request); 706 707 ATA_OUTL(ctlr->r_res2, 0x0240 + (ch->unit << 7), ch->dma.work_bus); 708 return 0; 709 } 710 711 static void 712 ata_promise_mio_reset(device_t dev) 713 { 714 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 715 struct ata_channel *ch = device_get_softc(dev); 716 struct ata_promise_sx4 *hpktp; 717 718 switch (ctlr->chip->cfg2) { 719 case PR_SX4X: 720 721 /* softreset channel ATA module */ 722 hpktp = ctlr->chipset_data; 723 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), ch->unit + 1); 724 ata_udelay(1000); 725 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), 726 (ATA_INL(ctlr->r_res2, 0xc0260 + (ch->unit << 7)) & 727 ~0x00003f9f) | (ch->unit + 1)); 728 729 /* softreset HOST module */ /* XXX SOS what about other outstandings */ 730 mtx_lock(&hpktp->mtx); 731 ATA_OUTL(ctlr->r_res2, 0xc012c, 732 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f) | (1 << 11)); 733 DELAY(10); 734 ATA_OUTL(ctlr->r_res2, 0xc012c, 735 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f)); 736 hpktp->busy = 0; 737 mtx_unlock(&hpktp->mtx); 738 ata_generic_reset(dev); 739 break; 740 741 case PR_PATA: 742 case PR_CMBO: 743 case PR_SATA: 744 if ((ctlr->chip->cfg2 == PR_SATA) || 745 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2))) { 746 747 /* mask plug/unplug intr */ 748 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00110000 << ch->unit)); 749 } 750 751 /* softreset channels ATA module */ 752 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11)); 753 ata_udelay(10000); 754 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), 755 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) & 756 ~0x00003f9f) | (ch->unit + 1)); 757 758 if ((ctlr->chip->cfg2 == PR_SATA) || 759 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2))) { 760 761 if (ata_sata_phy_reset(dev, -1, 1)) 762 ata_generic_reset(dev); 763 764 /* reset and enable plug/unplug intr */ 765 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00000011 << ch->unit)); 766 } 767 else 768 ata_generic_reset(dev); 769 break; 770 771 case PR_CMBO2: 772 case PR_SATA2: 773 if ((ctlr->chip->cfg2 == PR_SATA2) || 774 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) { 775 /* set portmultiplier port */ 776 //ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f); 777 778 /* mask plug/unplug intr */ 779 ATA_OUTL(ctlr->r_res2, 0x060, (0x00110000 << ch->unit)); 780 } 781 782 /* softreset channels ATA module */ 783 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11)); 784 ata_udelay(10000); 785 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), 786 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) & 787 ~0x00003f9f) | (ch->unit + 1)); 788 789 if ((ctlr->chip->cfg2 == PR_SATA2) || 790 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) { 791 792 /* set PHY mode to "improved" */ 793 ATA_OUTL(ctlr->r_res2, 0x414 + (ch->unit << 8), 794 (ATA_INL(ctlr->r_res2, 0x414 + (ch->unit << 8)) & 795 ~0x00000003) | 0x00000001); 796 797 if (ata_sata_phy_reset(dev, -1, 1)) { 798 u_int32_t signature = ch->hw.softreset(dev, ATA_PM); 799 800 if (1 | bootverbose) 801 device_printf(dev, "SIGNATURE: %08x\n", signature); 802 803 switch (signature >> 16) { 804 case 0x0000: 805 ch->devices = ATA_ATA_MASTER; 806 break; 807 case 0x9669: 808 ch->devices = ATA_PORTMULTIPLIER; 809 ata_pm_identify(dev); 810 break; 811 case 0xeb14: 812 ch->devices = ATA_ATAPI_MASTER; 813 break; 814 default: /* SOS XXX */ 815 if (bootverbose) 816 device_printf(dev, 817 "No signature, assuming disk device\n"); 818 ch->devices = ATA_ATA_MASTER; 819 } 820 if (bootverbose) 821 device_printf(dev, "promise_mio_reset devices=%08x\n", 822 ch->devices); 823 824 } 825 826 /* reset and enable plug/unplug intr */ 827 ATA_OUTL(ctlr->r_res2, 0x060, (0x00000011 << ch->unit)); 828 829 ///* set portmultiplier port */ 830 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x00); 831 } 832 else 833 ata_generic_reset(dev); 834 break; 835 836 } 837 } 838 839 static int 840 ata_promise_mio_pm_read(device_t dev, int port, int reg, u_int32_t *result) 841 { 842 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 843 struct ata_channel *ch = device_get_softc(dev); 844 int timeout = 0; 845 846 /* set portmultiplier port */ 847 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f); 848 849 ATA_IDX_OUTB(ch, ATA_FEATURE, reg); 850 ATA_IDX_OUTB(ch, ATA_DRIVE, port); 851 852 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_READ_PM); 853 854 while (timeout < 1000000) { 855 u_int8_t status = ATA_IDX_INB(ch, ATA_STATUS); 856 if (!(status & ATA_S_BUSY)) 857 break; 858 timeout += 1000; 859 DELAY(1000); 860 } 861 if (timeout >= 1000000) 862 return ATA_E_ABORT; 863 864 *result = ATA_IDX_INB(ch, ATA_COUNT) | 865 (ATA_IDX_INB(ch, ATA_SECTOR) << 8) | 866 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 16) | 867 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 24); 868 return 0; 869 } 870 871 static int 872 ata_promise_mio_pm_write(device_t dev, int port, int reg, u_int32_t value) 873 { 874 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 875 struct ata_channel *ch = device_get_softc(dev); 876 int timeout = 0; 877 878 /* set portmultiplier port */ 879 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f); 880 881 ATA_IDX_OUTB(ch, ATA_FEATURE, reg); 882 ATA_IDX_OUTB(ch, ATA_DRIVE, port); 883 ATA_IDX_OUTB(ch, ATA_COUNT, value & 0xff); 884 ATA_IDX_OUTB(ch, ATA_SECTOR, (value >> 8) & 0xff); 885 ATA_IDX_OUTB(ch, ATA_CYL_LSB, (value >> 16) & 0xff); 886 ATA_IDX_OUTB(ch, ATA_CYL_MSB, (value >> 24) & 0xff); 887 888 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_WRITE_PM); 889 890 while (timeout < 1000000) { 891 u_int8_t status = ATA_IDX_INB(ch, ATA_STATUS); 892 if (!(status & ATA_S_BUSY)) 893 break; 894 timeout += 1000; 895 DELAY(1000); 896 } 897 if (timeout >= 1000000) 898 return ATA_E_ABORT; 899 900 return ATA_IDX_INB(ch, ATA_ERROR); 901 } 902 903 /* must be called with ATA channel locked and state_mtx held */ 904 static u_int32_t 905 ata_promise_mio_softreset(device_t dev, int port) 906 { 907 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 908 struct ata_channel *ch = device_get_softc(dev); 909 int timeout; 910 911 /* set portmultiplier port */ 912 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), port & 0x0f); 913 914 /* softreset device on this channel */ 915 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_MASTER)); 916 DELAY(10); 917 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS | ATA_A_RESET); 918 ata_udelay(10000); 919 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS); 920 ata_udelay(150000); 921 ATA_IDX_INB(ch, ATA_ERROR); 922 923 /* wait for BUSY to go inactive */ 924 for (timeout = 0; timeout < 100; timeout++) { 925 u_int8_t err, stat; 926 927 err = ATA_IDX_INB(ch, ATA_ERROR); 928 stat = ATA_IDX_INB(ch, ATA_STATUS); 929 930 //if (stat == err && timeout > (stat & ATA_S_BUSY ? 100 : 10)) 931 //break; 932 933 if (!(stat & ATA_S_BUSY)) { 934 //if ((err & 0x7f) == ATA_E_ILI) { 935 return ATA_IDX_INB(ch, ATA_COUNT) | 936 (ATA_IDX_INB(ch, ATA_SECTOR) << 8) | 937 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 16) | 938 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 24); 939 //} 940 //else if (stat & 0x0f) { 941 //stat |= ATA_S_BUSY; 942 //} 943 } 944 945 if (!(stat & ATA_S_BUSY) || (stat == 0xff && timeout > 10)) 946 break; 947 ata_udelay(100000); 948 } 949 return -1; 950 } 951 952 static void 953 ata_promise_mio_dmainit(device_t dev) 954 { 955 struct ata_channel *ch = device_get_softc(dev); 956 957 ata_dmainit(dev); 958 /* note start and stop are not used here */ 959 ch->dma.setprd = ata_promise_mio_setprd; 960 } 961 962 963 #define MAXLASTSGSIZE (32 * sizeof(u_int32_t)) 964 static void 965 ata_promise_mio_setprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 966 { 967 struct ata_dmasetprd_args *args = xsc; 968 struct ata_dma_prdentry *prd = args->dmatab; 969 int i; 970 971 if ((args->error = error)) 972 return; 973 974 for (i = 0; i < nsegs; i++) { 975 prd[i].addr = htole32(segs[i].ds_addr); 976 prd[i].count = htole32(segs[i].ds_len); 977 } 978 if (segs[i - 1].ds_len > MAXLASTSGSIZE) { 979 //printf("split last SG element of %u\n", segs[i - 1].ds_len); 980 prd[i - 1].count = htole32(segs[i - 1].ds_len - MAXLASTSGSIZE); 981 prd[i].count = htole32(MAXLASTSGSIZE); 982 prd[i].addr = htole32(segs[i - 1].ds_addr + 983 (segs[i - 1].ds_len - MAXLASTSGSIZE)); 984 nsegs++; 985 i++; 986 } 987 prd[i - 1].count |= htole32(ATA_DMA_EOT); 988 KASSERT(nsegs <= ATA_DMA_ENTRIES, ("too many DMA segment entries\n")); 989 args->nsegs = nsegs; 990 } 991 992 static int 993 ata_promise_mio_setmode(device_t dev, int target, int mode) 994 { 995 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 996 struct ata_channel *ch = device_get_softc(dev); 997 998 if ( (ctlr->chip->cfg2 == PR_SATA) || 999 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2)) || 1000 (ctlr->chip->cfg2 == PR_SATA2) || 1001 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) 1002 mode = ata_sata_setmode(dev, target, mode); 1003 else 1004 mode = ata_promise_setmode(dev, target, mode); 1005 return (mode); 1006 } 1007 1008 static void 1009 ata_promise_sx4_intr(void *data) 1010 { 1011 struct ata_pci_controller *ctlr = data; 1012 struct ata_channel *ch; 1013 u_int32_t vector = ATA_INL(ctlr->r_res2, 0x000c0480); 1014 int unit; 1015 1016 for (unit = 0; unit < ctlr->channels; unit++) { 1017 if (vector & (1 << (unit + 1))) 1018 if ((ch = ctlr->interrupt[unit].argument)) 1019 ctlr->interrupt[unit].function(ch); 1020 if (vector & (1 << (unit + 5))) 1021 if ((ch = ctlr->interrupt[unit].argument)) 1022 ata_promise_queue_hpkt(ctlr, 1023 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + 1024 ATA_PDC_HPKT_OFFSET)); 1025 if (vector & (1 << (unit + 9))) { 1026 ata_promise_next_hpkt(ctlr); 1027 if ((ch = ctlr->interrupt[unit].argument)) 1028 ctlr->interrupt[unit].function(ch); 1029 } 1030 if (vector & (1 << (unit + 13))) { 1031 ata_promise_next_hpkt(ctlr); 1032 if ((ch = ctlr->interrupt[unit].argument)) 1033 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 1034 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + 1035 ATA_PDC_APKT_OFFSET)); 1036 } 1037 } 1038 } 1039 1040 static int 1041 ata_promise_sx4_command(struct ata_request *request) 1042 { 1043 device_t gparent = device_get_parent(request->parent); 1044 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1045 struct ata_channel *ch = device_get_softc(request->parent); 1046 struct ata_dma_prdentry *prd; 1047 caddr_t window = rman_get_virtual(ctlr->r_res1); 1048 u_int32_t *wordp; 1049 int i, idx, length = 0; 1050 1051 /* XXX SOS add ATAPI commands support later */ 1052 switch (request->u.ata.command) { 1053 1054 default: 1055 return -1; 1056 1057 case ATA_ATA_IDENTIFY: 1058 case ATA_READ: 1059 case ATA_READ48: 1060 case ATA_READ_MUL: 1061 case ATA_READ_MUL48: 1062 case ATA_WRITE: 1063 case ATA_WRITE48: 1064 case ATA_WRITE_MUL: 1065 case ATA_WRITE_MUL48: 1066 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001); 1067 return ata_generic_command(request); 1068 1069 case ATA_SETFEATURES: 1070 case ATA_FLUSHCACHE: 1071 case ATA_FLUSHCACHE48: 1072 case ATA_SLEEP: 1073 case ATA_SET_MULTI: 1074 wordp = (u_int32_t *) 1075 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET); 1076 wordp[0] = htole32(0x08 | ((ch->unit + 1)<<16) | (0x00 << 24)); 1077 wordp[1] = 0; 1078 wordp[2] = 0; 1079 ata_promise_apkt((u_int8_t *)wordp, request); 1080 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001); 1081 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001); 1082 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 1083 htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_APKT_OFFSET)); 1084 return 0; 1085 1086 case ATA_READ_DMA: 1087 case ATA_READ_DMA48: 1088 case ATA_WRITE_DMA: 1089 case ATA_WRITE_DMA48: 1090 prd = request->dma->sg; 1091 wordp = (u_int32_t *) 1092 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HSG_OFFSET); 1093 i = idx = 0; 1094 do { 1095 wordp[idx++] = prd[i].addr; 1096 wordp[idx++] = prd[i].count; 1097 length += (prd[i].count & ~ATA_DMA_EOT); 1098 } while (!(prd[i++].count & ATA_DMA_EOT)); 1099 1100 wordp = (u_int32_t *) 1101 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_LSG_OFFSET); 1102 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE); 1103 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT); 1104 1105 wordp = (u_int32_t *) 1106 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_ASG_OFFSET); 1107 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE); 1108 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT); 1109 1110 wordp = (u_int32_t *) 1111 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET); 1112 if (request->flags & ATA_R_READ) 1113 wordp[0] = htole32(0x14 | ((ch->unit+9)<<16) | ((ch->unit+5)<<24)); 1114 if (request->flags & ATA_R_WRITE) 1115 wordp[0] = htole32(0x00 | ((ch->unit+13)<<16) | (0x00<<24)); 1116 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_HSG_OFFSET); 1117 wordp[2] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_LSG_OFFSET); 1118 wordp[3] = 0; 1119 1120 wordp = (u_int32_t *) 1121 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET); 1122 if (request->flags & ATA_R_READ) 1123 wordp[0] = htole32(0x04 | ((ch->unit+5)<<16) | (0x00<<24)); 1124 if (request->flags & ATA_R_WRITE) 1125 wordp[0] = htole32(0x10 | ((ch->unit+1)<<16) | ((ch->unit+13)<<24)); 1126 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_ASG_OFFSET); 1127 wordp[2] = 0; 1128 ata_promise_apkt((u_int8_t *)wordp, request); 1129 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001); 1130 1131 if (request->flags & ATA_R_READ) { 1132 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+5)<<2), 0x00000001); 1133 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+9)<<2), 0x00000001); 1134 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 1135 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET)); 1136 } 1137 if (request->flags & ATA_R_WRITE) { 1138 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+1)<<2), 0x00000001); 1139 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+13)<<2), 0x00000001); 1140 ata_promise_queue_hpkt(ctlr, 1141 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET)); 1142 } 1143 return 0; 1144 } 1145 } 1146 1147 static int 1148 ata_promise_apkt(u_int8_t *bytep, struct ata_request *request) 1149 { 1150 int i = 12; 1151 1152 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_PDC_WAIT_NBUSY|ATA_DRIVE; 1153 bytep[i++] = ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit); 1154 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_CTL; 1155 bytep[i++] = ATA_A_4BIT; 1156 1157 if (request->flags & ATA_R_48BIT) { 1158 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_FEATURE; 1159 bytep[i++] = request->u.ata.feature >> 8; 1160 bytep[i++] = request->u.ata.feature; 1161 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_COUNT; 1162 bytep[i++] = request->u.ata.count >> 8; 1163 bytep[i++] = request->u.ata.count; 1164 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_SECTOR; 1165 bytep[i++] = request->u.ata.lba >> 24; 1166 bytep[i++] = request->u.ata.lba; 1167 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_LSB; 1168 bytep[i++] = request->u.ata.lba >> 32; 1169 bytep[i++] = request->u.ata.lba >> 8; 1170 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_MSB; 1171 bytep[i++] = request->u.ata.lba >> 40; 1172 bytep[i++] = request->u.ata.lba >> 16; 1173 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE; 1174 bytep[i++] = ATA_D_LBA | ATA_DEV(request->unit); 1175 } 1176 else { 1177 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_FEATURE; 1178 bytep[i++] = request->u.ata.feature; 1179 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_COUNT; 1180 bytep[i++] = request->u.ata.count; 1181 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_SECTOR; 1182 bytep[i++] = request->u.ata.lba; 1183 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_LSB; 1184 bytep[i++] = request->u.ata.lba >> 8; 1185 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_MSB; 1186 bytep[i++] = request->u.ata.lba >> 16; 1187 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE; 1188 bytep[i++] = ATA_D_LBA | ATA_D_IBM | ATA_DEV(request->unit) | 1189 ((request->u.ata.lba >> 24)&0xf); 1190 } 1191 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_END | ATA_COMMAND; 1192 bytep[i++] = request->u.ata.command; 1193 return i; 1194 } 1195 1196 static void 1197 ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt) 1198 { 1199 struct ata_promise_sx4 *hpktp = ctlr->chipset_data; 1200 1201 mtx_lock(&hpktp->mtx); 1202 if (hpktp->busy) { 1203 struct host_packet *hp = 1204 malloc(sizeof(struct host_packet), M_TEMP, M_NOWAIT | M_ZERO); 1205 hp->addr = hpkt; 1206 TAILQ_INSERT_TAIL(&hpktp->queue, hp, chain); 1207 } 1208 else { 1209 hpktp->busy = 1; 1210 ATA_OUTL(ctlr->r_res2, 0x000c0100, hpkt); 1211 } 1212 mtx_unlock(&hpktp->mtx); 1213 } 1214 1215 static void 1216 ata_promise_next_hpkt(struct ata_pci_controller *ctlr) 1217 { 1218 struct ata_promise_sx4 *hpktp = ctlr->chipset_data; 1219 struct host_packet *hp; 1220 1221 mtx_lock(&hpktp->mtx); 1222 if ((hp = TAILQ_FIRST(&hpktp->queue))) { 1223 TAILQ_REMOVE(&hpktp->queue, hp, chain); 1224 ATA_OUTL(ctlr->r_res2, 0x000c0100, hp->addr); 1225 free(hp, M_TEMP); 1226 } 1227 else 1228 hpktp->busy = 0; 1229 mtx_unlock(&hpktp->mtx); 1230 } 1231 1232 ATA_DECLARE_DRIVER(ata_promise); 1233