1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification, immediately at the beginning of the file. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/param.h> 30 #include <sys/module.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/ata.h> 34 #include <sys/bus.h> 35 #include <sys/endian.h> 36 #include <sys/malloc.h> 37 #include <sys/lock.h> 38 #include <sys/mutex.h> 39 #include <sys/sema.h> 40 #include <sys/taskqueue.h> 41 #include <vm/uma.h> 42 #include <machine/stdarg.h> 43 #include <machine/resource.h> 44 #include <machine/bus.h> 45 #include <sys/rman.h> 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcireg.h> 48 #include <dev/ata/ata-all.h> 49 #include <dev/ata/ata-pci.h> 50 #include <ata_if.h> 51 52 /* local prototypes */ 53 static int ata_promise_chipinit(device_t dev); 54 static int ata_promise_ch_attach(device_t dev); 55 static int ata_promise_status(device_t dev); 56 static int ata_promise_dmastart(struct ata_request *request); 57 static int ata_promise_dmastop(struct ata_request *request); 58 static void ata_promise_dmareset(device_t dev); 59 static int ata_promise_setmode(device_t dev, int target, int mode); 60 static int ata_promise_tx2_ch_attach(device_t dev); 61 static int ata_promise_tx2_status(device_t dev); 62 static int ata_promise_mio_ch_attach(device_t dev); 63 static int ata_promise_mio_ch_detach(device_t dev); 64 static void ata_promise_mio_intr(void *data); 65 static int ata_promise_mio_status(device_t dev); 66 static int ata_promise_mio_command(struct ata_request *request); 67 static void ata_promise_mio_reset(device_t dev); 68 static int ata_promise_mio_pm_read(device_t dev, int port, int reg, u_int32_t *result); 69 static int ata_promise_mio_pm_write(device_t dev, int port, int reg, u_int32_t result); 70 static u_int32_t ata_promise_mio_softreset(device_t dev, int port); 71 static void ata_promise_mio_dmainit(device_t dev); 72 static void ata_promise_mio_setprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 73 static int ata_promise_mio_setmode(device_t dev, int target, int mode); 74 static int ata_promise_mio_getrev(device_t dev, int target); 75 static void ata_promise_sx4_intr(void *data); 76 static int ata_promise_sx4_command(struct ata_request *request); 77 static int ata_promise_apkt(u_int8_t *bytep, struct ata_request *request); 78 static void ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt); 79 static void ata_promise_next_hpkt(struct ata_pci_controller *ctlr); 80 81 /* misc defines */ 82 #define PR_OLD 0 83 #define PR_NEW 1 84 #define PR_TX 2 85 #define PR_MIO 3 86 #define PR_TX4 0x01 87 #define PR_SX4X 0x02 88 #define PR_SX6K 0x04 89 #define PR_PATA 0x08 90 #define PR_CMBO 0x10 91 #define PR_CMBO2 0x20 92 #define PR_SATA 0x40 93 #define PR_SATA2 0x80 94 95 /* 96 * Promise chipset support functions 97 */ 98 #define ATA_PDC_APKT_OFFSET 0x00000010 99 #define ATA_PDC_HPKT_OFFSET 0x00000040 100 #define ATA_PDC_ASG_OFFSET 0x00000080 101 #define ATA_PDC_LSG_OFFSET 0x000000c0 102 #define ATA_PDC_HSG_OFFSET 0x00000100 103 #define ATA_PDC_CHN_OFFSET 0x00000400 104 #define ATA_PDC_BUF_BASE 0x00400000 105 #define ATA_PDC_BUF_OFFSET 0x00100000 106 #define ATA_PDC_MAX_HPKT 8 107 #define ATA_PDC_WRITE_REG 0x00 108 #define ATA_PDC_WRITE_CTL 0x0e 109 #define ATA_PDC_WRITE_END 0x08 110 #define ATA_PDC_WAIT_NBUSY 0x10 111 #define ATA_PDC_WAIT_READY 0x18 112 #define ATA_PDC_1B 0x20 113 #define ATA_PDC_2B 0x40 114 115 struct host_packet { 116 u_int32_t addr; 117 TAILQ_ENTRY(host_packet) chain; 118 }; 119 120 struct ata_promise_sx4 { 121 struct mtx mtx; 122 TAILQ_HEAD(, host_packet) queue; 123 int busy; 124 }; 125 126 static int 127 ata_promise_probe(device_t dev) 128 { 129 struct ata_pci_controller *ctlr = device_get_softc(dev); 130 const struct ata_chip_id *idx; 131 static const struct ata_chip_id ids[] = 132 {{ ATA_PDC20246, 0, PR_OLD, 0x00, ATA_UDMA2, "PDC20246" }, 133 { ATA_PDC20262, 0, PR_NEW, 0x00, ATA_UDMA4, "PDC20262" }, 134 { ATA_PDC20263, 0, PR_NEW, 0x00, ATA_UDMA4, "PDC20263" }, 135 { ATA_PDC20265, 0, PR_NEW, 0x00, ATA_UDMA5, "PDC20265" }, 136 { ATA_PDC20267, 0, PR_NEW, 0x00, ATA_UDMA5, "PDC20267" }, 137 { ATA_PDC20268, 0, PR_TX, PR_TX4, ATA_UDMA5, "PDC20268" }, 138 { ATA_PDC20269, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20269" }, 139 { ATA_PDC20270, 0, PR_TX, PR_TX4, ATA_UDMA5, "PDC20270" }, 140 { ATA_PDC20271, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20271" }, 141 { ATA_PDC20275, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20275" }, 142 { ATA_PDC20276, 0, PR_TX, PR_SX6K, ATA_UDMA6, "PDC20276" }, 143 { ATA_PDC20277, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20277" }, 144 { ATA_PDC20318, 0, PR_MIO, PR_SATA, ATA_SA150, "PDC20318" }, 145 { ATA_PDC20319, 0, PR_MIO, PR_SATA, ATA_SA150, "PDC20319" }, 146 { ATA_PDC20371, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20371" }, 147 { ATA_PDC20375, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20375" }, 148 { ATA_PDC20376, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20376" }, 149 { ATA_PDC20377, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20377" }, 150 { ATA_PDC20378, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20378" }, 151 { ATA_PDC20379, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20379" }, 152 { ATA_PDC20571, 0, PR_MIO, PR_CMBO2, ATA_SA150, "PDC20571" }, 153 { ATA_PDC20575, 0, PR_MIO, PR_CMBO2, ATA_SA150, "PDC20575" }, 154 { ATA_PDC20579, 0, PR_MIO, PR_CMBO2, ATA_SA150, "PDC20579" }, 155 { ATA_PDC20771, 0, PR_MIO, PR_CMBO2, ATA_SA300, "PDC20771" }, 156 { ATA_PDC40775, 0, PR_MIO, PR_CMBO2, ATA_SA300, "PDC40775" }, 157 { ATA_PDC20617, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20617" }, 158 { ATA_PDC20618, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20618" }, 159 { ATA_PDC20619, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20619" }, 160 { ATA_PDC20620, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20620" }, 161 { ATA_PDC20621, 0, PR_MIO, PR_SX4X, ATA_UDMA5, "PDC20621" }, 162 { ATA_PDC20622, 0, PR_MIO, PR_SX4X, ATA_SA150, "PDC20622" }, 163 { ATA_PDC40518, 0, PR_MIO, PR_SATA2, ATA_SA150, "PDC40518" }, 164 { ATA_PDC40519, 0, PR_MIO, PR_SATA2, ATA_SA150, "PDC40519" }, 165 { ATA_PDC40718, 0, PR_MIO, PR_SATA2, ATA_SA300, "PDC40718" }, 166 { ATA_PDC40719, 0, PR_MIO, PR_SATA2, ATA_SA300, "PDC40719" }, 167 { ATA_PDC40779, 0, PR_MIO, PR_SATA2, ATA_SA300, "PDC40779" }, 168 { 0, 0, 0, 0, 0, 0}}; 169 char buffer[64]; 170 uintptr_t devid = 0; 171 172 if (pci_get_vendor(dev) != ATA_PROMISE_ID) 173 return ENXIO; 174 175 if (!(idx = ata_match_chip(dev, ids))) 176 return ENXIO; 177 178 /* if we are on a SuperTrak SX6000 dont attach */ 179 if ((idx->cfg2 & PR_SX6K) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE && 180 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), 181 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && 182 devid == ATA_I960RM) 183 return ENXIO; 184 185 strcpy(buffer, "Promise "); 186 strcat(buffer, idx->text); 187 188 /* if we are on a FastTrak TX4, adjust the interrupt resource */ 189 if ((idx->cfg2 & PR_TX4) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE && 190 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), 191 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && 192 ((devid == ATA_DEC_21150) || (devid == ATA_DEC_21150_1))) { 193 static rman_res_t start = 0, end = 0; 194 195 if (pci_get_slot(dev) == 1) { 196 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end); 197 strcat(buffer, " (channel 0+1)"); 198 } 199 else if (pci_get_slot(dev) == 2 && start && end) { 200 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end); 201 strcat(buffer, " (channel 2+3)"); 202 } 203 else { 204 start = end = 0; 205 } 206 } 207 sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma)); 208 device_set_desc_copy(dev, buffer); 209 ctlr->chip = idx; 210 ctlr->chipinit = ata_promise_chipinit; 211 return (BUS_PROBE_LOW_PRIORITY); 212 } 213 214 static int 215 ata_promise_chipinit(device_t dev) 216 { 217 struct ata_pci_controller *ctlr = device_get_softc(dev); 218 int stat_reg; 219 220 if (ata_setup_interrupt(dev, ata_generic_intr)) 221 return ENXIO; 222 223 switch (ctlr->chip->cfg1) { 224 case PR_NEW: 225 /* setup clocks */ 226 ATA_OUTB(ctlr->r_res1, 0x11, ATA_INB(ctlr->r_res1, 0x11) | 0x0a); 227 /* FALLTHROUGH */ 228 229 case PR_OLD: 230 /* enable burst mode */ 231 ATA_OUTB(ctlr->r_res1, 0x1f, ATA_INB(ctlr->r_res1, 0x1f) | 0x01); 232 ctlr->ch_attach = ata_promise_ch_attach; 233 ctlr->ch_detach = ata_pci_ch_detach; 234 ctlr->setmode = ata_promise_setmode; 235 return 0; 236 237 case PR_TX: 238 ctlr->ch_attach = ata_promise_tx2_ch_attach; 239 ctlr->ch_detach = ata_pci_ch_detach; 240 ctlr->setmode = ata_promise_setmode; 241 return 0; 242 243 case PR_MIO: 244 ctlr->r_type1 = SYS_RES_MEMORY; 245 ctlr->r_rid1 = PCIR_BAR(4); 246 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 247 &ctlr->r_rid1, RF_ACTIVE))) 248 goto failnfree; 249 250 ctlr->r_type2 = SYS_RES_MEMORY; 251 ctlr->r_rid2 = PCIR_BAR(3); 252 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 253 &ctlr->r_rid2, RF_ACTIVE))) 254 goto failnfree; 255 256 if (ctlr->chip->cfg2 == PR_SX4X) { 257 struct ata_promise_sx4 *hpkt; 258 u_int32_t dimm = ATA_INL(ctlr->r_res2, 0x000c0080); 259 260 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) || 261 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, NULL, 262 ata_promise_sx4_intr, ctlr, &ctlr->handle)) { 263 device_printf(dev, "unable to setup interrupt\n"); 264 goto failnfree; 265 } 266 267 /* print info about cache memory */ 268 device_printf(dev, "DIMM size %dMB @ 0x%08x%s\n", 269 (((dimm >> 16) & 0xff)-((dimm >> 24) & 0xff)+1) << 4, 270 ((dimm >> 24) & 0xff), 271 ATA_INL(ctlr->r_res2, 0x000c0088) & (1<<16) ? 272 " ECC enabled" : "" ); 273 274 /* adjust cache memory parameters */ 275 ATA_OUTL(ctlr->r_res2, 0x000c000c, 276 (ATA_INL(ctlr->r_res2, 0x000c000c) & 0xffff0000)); 277 278 /* setup host packet controls */ 279 hpkt = malloc(sizeof(struct ata_promise_sx4), 280 M_ATAPCI, M_NOWAIT | M_ZERO); 281 if (hpkt == NULL) { 282 device_printf(dev, "Cannot allocate HPKT\n"); 283 goto failnfree; 284 } 285 mtx_init(&hpkt->mtx, "ATA promise HPKT lock", NULL, MTX_DEF); 286 TAILQ_INIT(&hpkt->queue); 287 hpkt->busy = 0; 288 ctlr->chipset_data = hpkt; 289 ctlr->ch_attach = ata_promise_mio_ch_attach; 290 ctlr->ch_detach = ata_promise_mio_ch_detach; 291 ctlr->reset = ata_promise_mio_reset; 292 ctlr->setmode = ata_promise_setmode; 293 ctlr->channels = 4; 294 return 0; 295 } 296 297 /* mio type controllers need an interrupt intercept */ 298 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) || 299 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, NULL, 300 ata_promise_mio_intr, ctlr, &ctlr->handle)) { 301 device_printf(dev, "unable to setup interrupt\n"); 302 goto failnfree; 303 } 304 305 switch (ctlr->chip->cfg2) { 306 case PR_PATA: 307 ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x01) > 0) + 308 ((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 2; 309 goto sata150; 310 case PR_CMBO: 311 ctlr->channels = 3; 312 goto sata150; 313 case PR_SATA: 314 ctlr->channels = 4; 315 sata150: 316 stat_reg = 0x6c; 317 break; 318 319 case PR_CMBO2: 320 ctlr->channels = 3; 321 goto sataii; 322 case PR_SATA2: 323 default: 324 ctlr->channels = 4; 325 sataii: 326 stat_reg = 0x60; 327 break; 328 } 329 330 /* prime fake interrupt register */ 331 ctlr->chipset_data = (void *)(uintptr_t)0xffffffff; 332 333 /* clear SATA status and unmask interrupts */ 334 ATA_OUTL(ctlr->r_res2, stat_reg, 0x000000ff); 335 336 /* enable "long burst length" on gen2 chips */ 337 if ((ctlr->chip->cfg2 == PR_SATA2) || (ctlr->chip->cfg2 == PR_CMBO2)) 338 ATA_OUTL(ctlr->r_res2, 0x44, ATA_INL(ctlr->r_res2, 0x44) | 0x2000); 339 340 ctlr->ch_attach = ata_promise_mio_ch_attach; 341 ctlr->ch_detach = ata_promise_mio_ch_detach; 342 ctlr->reset = ata_promise_mio_reset; 343 ctlr->setmode = ata_promise_mio_setmode; 344 ctlr->getrev = ata_promise_mio_getrev; 345 346 return 0; 347 } 348 349 failnfree: 350 if (ctlr->r_res2) 351 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2); 352 if (ctlr->r_res1) 353 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1, ctlr->r_res1); 354 return ENXIO; 355 } 356 357 static int 358 ata_promise_ch_attach(device_t dev) 359 { 360 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 361 struct ata_channel *ch = device_get_softc(dev); 362 363 if (ata_pci_ch_attach(dev)) 364 return ENXIO; 365 366 if (ctlr->chip->cfg1 == PR_NEW) { 367 ch->dma.start = ata_promise_dmastart; 368 ch->dma.stop = ata_promise_dmastop; 369 ch->dma.reset = ata_promise_dmareset; 370 } 371 372 ch->hw.status = ata_promise_status; 373 ch->flags |= ATA_NO_ATAPI_DMA; 374 ch->flags |= ATA_CHECKS_CABLE; 375 return 0; 376 } 377 378 static int 379 ata_promise_status(device_t dev) 380 { 381 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 382 struct ata_channel *ch = device_get_softc(dev); 383 384 if (ATA_INL(ctlr->r_res1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)) { 385 return ata_pci_status(dev); 386 } 387 return 0; 388 } 389 390 static int 391 ata_promise_dmastart(struct ata_request *request) 392 { 393 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 394 struct ata_channel *ch = device_get_softc(request->parent); 395 396 if (request->flags & ATA_R_48BIT) { 397 ATA_OUTB(ctlr->r_res1, 0x11, 398 ATA_INB(ctlr->r_res1, 0x11) | (ch->unit ? 0x08 : 0x02)); 399 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 400 ((request->flags & ATA_R_READ) ? 0x05000000 : 0x06000000) | 401 (request->bytecount >> 1)); 402 } 403 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) | 404 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 405 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, request->dma->sg_bus); 406 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 407 ((request->flags & ATA_R_READ) ? ATA_BMCMD_WRITE_READ : 0) | 408 ATA_BMCMD_START_STOP); 409 ch->dma.flags |= ATA_DMA_ACTIVE; 410 return 0; 411 } 412 413 static int 414 ata_promise_dmastop(struct ata_request *request) 415 { 416 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 417 struct ata_channel *ch = device_get_softc(request->parent); 418 int error; 419 420 if (request->flags & ATA_R_48BIT) { 421 ATA_OUTB(ctlr->r_res1, 0x11, 422 ATA_INB(ctlr->r_res1, 0x11) & ~(ch->unit ? 0x08 : 0x02)); 423 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 0); 424 } 425 error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT); 426 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 427 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 428 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 429 ch->dma.flags &= ~ATA_DMA_ACTIVE; 430 return error; 431 } 432 433 static void 434 ata_promise_dmareset(device_t dev) 435 { 436 struct ata_channel *ch = device_get_softc(dev); 437 438 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 439 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 440 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 441 ch->flags &= ~ATA_DMA_ACTIVE; 442 } 443 444 static int 445 ata_promise_setmode(device_t dev, int target, int mode) 446 { 447 device_t parent = device_get_parent(dev); 448 struct ata_pci_controller *ctlr = device_get_softc(parent); 449 struct ata_channel *ch = device_get_softc(dev); 450 int devno = (ch->unit << 1) + target; 451 static const uint32_t timings[][2] = { 452 /* PR_OLD PR_NEW mode */ 453 { 0x004ff329, 0x004fff2f }, /* PIO 0 */ 454 { 0x004fec25, 0x004ff82a }, /* PIO 1 */ 455 { 0x004fe823, 0x004ff026 }, /* PIO 2 */ 456 { 0x004fe622, 0x004fec24 }, /* PIO 3 */ 457 { 0x004fe421, 0x004fe822 }, /* PIO 4 */ 458 { 0x004567f3, 0x004acef6 }, /* MWDMA 0 */ 459 { 0x004467f3, 0x0048cef6 }, /* MWDMA 1 */ 460 { 0x004367f3, 0x0046cef6 }, /* MWDMA 2 */ 461 { 0x004367f3, 0x0046cef6 }, /* UDMA 0 */ 462 { 0x004247f3, 0x00448ef6 }, /* UDMA 1 */ 463 { 0x004127f3, 0x00436ef6 }, /* UDMA 2 */ 464 { 0, 0x00424ef6 }, /* UDMA 3 */ 465 { 0, 0x004127f3 }, /* UDMA 4 */ 466 { 0, 0x004127f3 } /* UDMA 5 */ 467 }; 468 469 mode = min(mode, ctlr->chip->max_dma); 470 471 switch (ctlr->chip->cfg1) { 472 case PR_OLD: 473 case PR_NEW: 474 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 475 (pci_read_config(parent, 0x50, 2) & 476 (ch->unit ? 1 << 11 : 1 << 10))) { 477 ata_print_cable(dev, "controller"); 478 mode = ATA_UDMA2; 479 } 480 break; 481 482 case PR_TX: 483 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b); 484 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 485 ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x04) { 486 ata_print_cable(dev, "controller"); 487 mode = ATA_UDMA2; 488 } 489 break; 490 491 case PR_MIO: 492 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 493 (ATA_INL(ctlr->r_res2, 494 (ctlr->chip->cfg2 & PR_SX4X ? 0x000c0260 : 0x0260) + 495 (ch->unit << 7)) & 0x01000000)) { 496 ata_print_cable(dev, "controller"); 497 mode = ATA_UDMA2; 498 } 499 break; 500 } 501 502 if (ctlr->chip->cfg1 < PR_TX) 503 pci_write_config(parent, 0x60 + (devno << 2), 504 timings[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); 505 return (mode); 506 } 507 508 static int 509 ata_promise_tx2_ch_attach(device_t dev) 510 { 511 struct ata_channel *ch = device_get_softc(dev); 512 513 if (ata_pci_ch_attach(dev)) 514 return ENXIO; 515 516 ch->hw.status = ata_promise_tx2_status; 517 ch->flags |= ATA_CHECKS_CABLE; 518 return 0; 519 } 520 521 static int 522 ata_promise_tx2_status(device_t dev) 523 { 524 struct ata_channel *ch = device_get_softc(dev); 525 526 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b); 527 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) { 528 return ata_pci_status(dev); 529 } 530 return 0; 531 } 532 533 static int 534 ata_promise_mio_ch_attach(device_t dev) 535 { 536 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 537 struct ata_channel *ch = device_get_softc(dev); 538 int offset = (ctlr->chip->cfg2 & PR_SX4X) ? 0x000c0000 : 0; 539 int i; 540 541 ata_promise_mio_dmainit(dev); 542 543 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 544 ch->r_io[i].res = ctlr->r_res2; 545 ch->r_io[i].offset = offset + 0x0200 + (i << 2) + (ch->unit << 7); 546 } 547 ch->r_io[ATA_CONTROL].res = ctlr->r_res2; 548 ch->r_io[ATA_CONTROL].offset = offset + 0x0238 + (ch->unit << 7); 549 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 550 ata_default_registers(dev); 551 if ((ctlr->chip->cfg2 & (PR_SATA | PR_SATA2)) || 552 ((ctlr->chip->cfg2 & (PR_CMBO | PR_CMBO2)) && ch->unit < 2)) { 553 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 554 ch->r_io[ATA_SSTATUS].offset = 0x400 + (ch->unit << 8); 555 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 556 ch->r_io[ATA_SERROR].offset = 0x404 + (ch->unit << 8); 557 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 558 ch->r_io[ATA_SCONTROL].offset = 0x408 + (ch->unit << 8); 559 ch->flags |= ATA_NO_SLAVE; 560 ch->flags |= ATA_SATA; 561 } 562 ch->flags |= ATA_USE_16BIT; 563 ch->flags |= ATA_CHECKS_CABLE; 564 565 ata_generic_hw(dev); 566 if (ctlr->chip->cfg2 & PR_SX4X) { 567 ch->hw.command = ata_promise_sx4_command; 568 } 569 else { 570 ch->hw.command = ata_promise_mio_command; 571 ch->hw.status = ata_promise_mio_status; 572 ch->hw.softreset = ata_promise_mio_softreset; 573 ch->hw.pm_read = ata_promise_mio_pm_read; 574 ch->hw.pm_write = ata_promise_mio_pm_write; 575 } 576 return 0; 577 } 578 579 static int 580 ata_promise_mio_ch_detach(device_t dev) 581 { 582 583 ata_dmafini(dev); 584 return (0); 585 } 586 587 static void 588 ata_promise_mio_intr(void *data) 589 { 590 struct ata_pci_controller *ctlr = data; 591 struct ata_channel *ch; 592 u_int32_t vector; 593 int unit; 594 595 /* 596 * since reading interrupt status register on early "mio" chips 597 * clears the status bits we cannot read it for each channel later on 598 * in the generic interrupt routine. 599 */ 600 vector = ATA_INL(ctlr->r_res2, 0x040); 601 ATA_OUTL(ctlr->r_res2, 0x040, vector); 602 ctlr->chipset_data = (void *)(uintptr_t)vector; 603 604 for (unit = 0; unit < ctlr->channels; unit++) { 605 if ((ch = ctlr->interrupt[unit].argument)) 606 ctlr->interrupt[unit].function(ch); 607 } 608 609 ctlr->chipset_data = (void *)(uintptr_t)0xffffffff; 610 } 611 612 static int 613 ata_promise_mio_status(device_t dev) 614 { 615 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 616 struct ata_channel *ch = device_get_softc(dev); 617 u_int32_t stat_reg, vector, status; 618 619 switch (ctlr->chip->cfg2) { 620 case PR_PATA: 621 case PR_CMBO: 622 case PR_SATA: 623 stat_reg = 0x6c; 624 break; 625 case PR_CMBO2: 626 case PR_SATA2: 627 default: 628 stat_reg = 0x60; 629 break; 630 } 631 632 /* read and acknowledge interrupt */ 633 vector = (uint32_t)(uintptr_t)ctlr->chipset_data; 634 635 /* read and clear interface status */ 636 status = ATA_INL(ctlr->r_res2, stat_reg); 637 ATA_OUTL(ctlr->r_res2, stat_reg, status & (0x00000011 << ch->unit)); 638 639 /* check for and handle disconnect events */ 640 if (status & (0x00000001 << ch->unit)) { 641 if (bootverbose) 642 device_printf(dev, "DISCONNECT requested\n"); 643 taskqueue_enqueue(taskqueue_thread, &ch->conntask); 644 } 645 646 /* check for and handle connect events */ 647 if (status & (0x00000010 << ch->unit)) { 648 if (bootverbose) 649 device_printf(dev, "CONNECT requested\n"); 650 taskqueue_enqueue(taskqueue_thread, &ch->conntask); 651 } 652 653 /* do we have any device action ? */ 654 return (vector & (1 << (ch->unit + 1))); 655 } 656 657 static int 658 ata_promise_mio_command(struct ata_request *request) 659 { 660 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 661 struct ata_channel *ch = device_get_softc(request->parent); 662 663 u_int32_t *wordp = (u_int32_t *)ch->dma.work; 664 665 ATA_OUTL(ctlr->r_res2, (ch->unit + 1) << 2, 0x00000001); 666 667 if ((ctlr->chip->cfg2 == PR_SATA2) || 668 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) { 669 /* set portmultiplier port */ 670 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), request->unit & 0x0f); 671 } 672 673 /* XXX SOS add ATAPI commands support later */ 674 switch (request->u.ata.command) { 675 default: 676 return ata_generic_command(request); 677 678 case ATA_READ_DMA: 679 case ATA_READ_DMA48: 680 wordp[0] = htole32(0x04 | ((ch->unit + 1) << 16) | (0x00 << 24)); 681 break; 682 683 case ATA_WRITE_DMA: 684 case ATA_WRITE_DMA48: 685 wordp[0] = htole32(0x00 | ((ch->unit + 1) << 16) | (0x00 << 24)); 686 break; 687 } 688 wordp[1] = htole32(request->dma->sg_bus); 689 wordp[2] = 0; 690 ata_promise_apkt((u_int8_t*)wordp, request); 691 692 ATA_OUTL(ctlr->r_res2, 0x0240 + (ch->unit << 7), ch->dma.work_bus); 693 return 0; 694 } 695 696 static void 697 ata_promise_mio_reset(device_t dev) 698 { 699 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 700 struct ata_channel *ch = device_get_softc(dev); 701 struct ata_promise_sx4 *hpktp; 702 703 switch (ctlr->chip->cfg2) { 704 case PR_SX4X: 705 706 /* softreset channel ATA module */ 707 hpktp = ctlr->chipset_data; 708 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), ch->unit + 1); 709 ata_udelay(1000); 710 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), 711 (ATA_INL(ctlr->r_res2, 0xc0260 + (ch->unit << 7)) & 712 ~0x00003f9f) | (ch->unit + 1)); 713 714 /* softreset HOST module */ /* XXX SOS what about other outstandings */ 715 mtx_lock(&hpktp->mtx); 716 ATA_OUTL(ctlr->r_res2, 0xc012c, 717 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f) | (1 << 11)); 718 DELAY(10); 719 ATA_OUTL(ctlr->r_res2, 0xc012c, 720 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f)); 721 hpktp->busy = 0; 722 mtx_unlock(&hpktp->mtx); 723 ata_generic_reset(dev); 724 break; 725 726 case PR_PATA: 727 case PR_CMBO: 728 case PR_SATA: 729 if ((ctlr->chip->cfg2 == PR_SATA) || 730 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2))) { 731 /* mask plug/unplug intr */ 732 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00110000 << ch->unit)); 733 } 734 735 /* softreset channels ATA module */ 736 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11)); 737 ata_udelay(10000); 738 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), 739 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) & 740 ~0x00003f9f) | (ch->unit + 1)); 741 742 if ((ctlr->chip->cfg2 == PR_SATA) || 743 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2))) { 744 if (ata_sata_phy_reset(dev, -1, 1)) 745 ata_generic_reset(dev); 746 else 747 ch->devices = 0; 748 749 /* reset and enable plug/unplug intr */ 750 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00000011 << ch->unit)); 751 } 752 else 753 ata_generic_reset(dev); 754 break; 755 756 case PR_CMBO2: 757 case PR_SATA2: 758 if ((ctlr->chip->cfg2 == PR_SATA2) || 759 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) { 760 /* set portmultiplier port */ 761 //ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f); 762 763 /* mask plug/unplug intr */ 764 ATA_OUTL(ctlr->r_res2, 0x060, (0x00110000 << ch->unit)); 765 } 766 767 /* softreset channels ATA module */ 768 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11)); 769 ata_udelay(10000); 770 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), 771 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) & 772 ~0x00003f9f) | (ch->unit + 1)); 773 774 if ((ctlr->chip->cfg2 == PR_SATA2) || 775 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) { 776 /* set PHY mode to "improved" */ 777 ATA_OUTL(ctlr->r_res2, 0x414 + (ch->unit << 8), 778 (ATA_INL(ctlr->r_res2, 0x414 + (ch->unit << 8)) & 779 ~0x00000003) | 0x00000001); 780 781 if (ata_sata_phy_reset(dev, -1, 1)) { 782 u_int32_t signature = ch->hw.softreset(dev, ATA_PM); 783 784 if (bootverbose) 785 device_printf(dev, "SIGNATURE: %08x\n", signature); 786 787 switch (signature >> 16) { 788 case 0x0000: 789 ch->devices = ATA_ATA_MASTER; 790 break; 791 case 0x9669: 792 ch->devices = ATA_PORTMULTIPLIER; 793 ata_pm_identify(dev); 794 break; 795 case 0xeb14: 796 ch->devices = ATA_ATAPI_MASTER; 797 break; 798 default: /* SOS XXX */ 799 if (bootverbose) 800 device_printf(dev, 801 "No signature, assuming disk device\n"); 802 ch->devices = ATA_ATA_MASTER; 803 } 804 if (bootverbose) 805 device_printf(dev, "promise_mio_reset devices=%08x\n", 806 ch->devices); 807 808 } else 809 ch->devices = 0; 810 811 /* reset and enable plug/unplug intr */ 812 ATA_OUTL(ctlr->r_res2, 0x060, (0x00000011 << ch->unit)); 813 814 ///* set portmultiplier port */ 815 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x00); 816 } 817 else 818 ata_generic_reset(dev); 819 break; 820 } 821 } 822 823 static int 824 ata_promise_mio_pm_read(device_t dev, int port, int reg, u_int32_t *result) 825 { 826 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 827 struct ata_channel *ch = device_get_softc(dev); 828 int timeout = 0; 829 830 if (port < 0) { 831 *result = ATA_IDX_INL(ch, reg); 832 return (0); 833 } 834 if (port < ATA_PM) { 835 switch (reg) { 836 case ATA_SSTATUS: 837 reg = 0; 838 break; 839 case ATA_SERROR: 840 reg = 1; 841 break; 842 case ATA_SCONTROL: 843 reg = 2; 844 break; 845 default: 846 return (EINVAL); 847 } 848 } 849 /* set portmultiplier port */ 850 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f); 851 852 ATA_IDX_OUTB(ch, ATA_FEATURE, reg); 853 ATA_IDX_OUTB(ch, ATA_DRIVE, port); 854 855 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_READ_PM); 856 857 while (timeout < 1000000) { 858 u_int8_t status = ATA_IDX_INB(ch, ATA_STATUS); 859 if (!(status & ATA_S_BUSY)) 860 break; 861 timeout += 1000; 862 DELAY(1000); 863 } 864 if (timeout >= 1000000) 865 return ATA_E_ABORT; 866 867 *result = ATA_IDX_INB(ch, ATA_COUNT) | 868 (ATA_IDX_INB(ch, ATA_SECTOR) << 8) | 869 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 16) | 870 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 24); 871 return 0; 872 } 873 874 static int 875 ata_promise_mio_pm_write(device_t dev, int port, int reg, u_int32_t value) 876 { 877 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 878 struct ata_channel *ch = device_get_softc(dev); 879 int timeout = 0; 880 881 if (port < 0) { 882 ATA_IDX_OUTL(ch, reg, value); 883 return (0); 884 } 885 if (port < ATA_PM) { 886 switch (reg) { 887 case ATA_SSTATUS: 888 reg = 0; 889 break; 890 case ATA_SERROR: 891 reg = 1; 892 break; 893 case ATA_SCONTROL: 894 reg = 2; 895 break; 896 default: 897 return (EINVAL); 898 } 899 } 900 /* set portmultiplier port */ 901 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f); 902 903 ATA_IDX_OUTB(ch, ATA_FEATURE, reg); 904 ATA_IDX_OUTB(ch, ATA_DRIVE, port); 905 ATA_IDX_OUTB(ch, ATA_COUNT, value & 0xff); 906 ATA_IDX_OUTB(ch, ATA_SECTOR, (value >> 8) & 0xff); 907 ATA_IDX_OUTB(ch, ATA_CYL_LSB, (value >> 16) & 0xff); 908 ATA_IDX_OUTB(ch, ATA_CYL_MSB, (value >> 24) & 0xff); 909 910 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_WRITE_PM); 911 912 while (timeout < 1000000) { 913 u_int8_t status = ATA_IDX_INB(ch, ATA_STATUS); 914 if (!(status & ATA_S_BUSY)) 915 break; 916 timeout += 1000; 917 DELAY(1000); 918 } 919 if (timeout >= 1000000) 920 return ATA_E_ABORT; 921 922 return ATA_IDX_INB(ch, ATA_ERROR); 923 } 924 925 /* must be called with ATA channel locked and state_mtx held */ 926 static u_int32_t 927 ata_promise_mio_softreset(device_t dev, int port) 928 { 929 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 930 struct ata_channel *ch = device_get_softc(dev); 931 int timeout; 932 933 /* set portmultiplier port */ 934 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), port & 0x0f); 935 936 /* softreset device on this channel */ 937 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_MASTER)); 938 DELAY(10); 939 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS | ATA_A_RESET); 940 ata_udelay(10000); 941 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS); 942 ata_udelay(150000); 943 ATA_IDX_INB(ch, ATA_ERROR); 944 945 /* wait for BUSY to go inactive */ 946 for (timeout = 0; timeout < 100; timeout++) { 947 u_int8_t /* err, */ stat; 948 949 /* err = */ ATA_IDX_INB(ch, ATA_ERROR); 950 stat = ATA_IDX_INB(ch, ATA_STATUS); 951 952 //if (stat == err && timeout > (stat & ATA_S_BUSY ? 100 : 10)) 953 //break; 954 955 if (!(stat & ATA_S_BUSY)) { 956 //if ((err & 0x7f) == ATA_E_ILI) { 957 return ATA_IDX_INB(ch, ATA_COUNT) | 958 (ATA_IDX_INB(ch, ATA_SECTOR) << 8) | 959 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 16) | 960 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 24); 961 //} 962 //else if (stat & 0x0f) { 963 //stat |= ATA_S_BUSY; 964 //} 965 } 966 967 if (!(stat & ATA_S_BUSY) || (stat == 0xff && timeout > 10)) 968 break; 969 ata_udelay(100000); 970 } 971 return -1; 972 } 973 974 static void 975 ata_promise_mio_dmainit(device_t dev) 976 { 977 struct ata_channel *ch = device_get_softc(dev); 978 979 /* note start and stop are not used here */ 980 ch->dma.setprd = ata_promise_mio_setprd; 981 ch->dma.max_iosize = 65536; 982 ata_dmainit(dev); 983 } 984 985 #define MAXLASTSGSIZE (32 * sizeof(u_int32_t)) 986 static void 987 ata_promise_mio_setprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 988 { 989 struct ata_dmasetprd_args *args = xsc; 990 struct ata_dma_prdentry *prd = args->dmatab; 991 int i; 992 993 if ((args->error = error)) 994 return; 995 996 for (i = 0; i < nsegs; i++) { 997 prd[i].addr = htole32(segs[i].ds_addr); 998 prd[i].count = htole32(segs[i].ds_len); 999 } 1000 if (segs[i - 1].ds_len > MAXLASTSGSIZE) { 1001 //printf("split last SG element of %u\n", segs[i - 1].ds_len); 1002 prd[i - 1].count = htole32(segs[i - 1].ds_len - MAXLASTSGSIZE); 1003 prd[i].count = htole32(MAXLASTSGSIZE); 1004 prd[i].addr = htole32(segs[i - 1].ds_addr + 1005 (segs[i - 1].ds_len - MAXLASTSGSIZE)); 1006 nsegs++; 1007 i++; 1008 } 1009 prd[i - 1].count |= htole32(ATA_DMA_EOT); 1010 KASSERT(nsegs <= ATA_DMA_ENTRIES, ("too many DMA segment entries\n")); 1011 args->nsegs = nsegs; 1012 } 1013 1014 static int 1015 ata_promise_mio_setmode(device_t dev, int target, int mode) 1016 { 1017 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1018 struct ata_channel *ch = device_get_softc(dev); 1019 1020 if ( (ctlr->chip->cfg2 == PR_SATA) || 1021 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2)) || 1022 (ctlr->chip->cfg2 == PR_SATA2) || 1023 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) 1024 mode = ata_sata_setmode(dev, target, mode); 1025 else 1026 mode = ata_promise_setmode(dev, target, mode); 1027 return (mode); 1028 } 1029 1030 static int 1031 ata_promise_mio_getrev(device_t dev, int target) 1032 { 1033 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1034 struct ata_channel *ch = device_get_softc(dev); 1035 1036 if ( (ctlr->chip->cfg2 == PR_SATA) || 1037 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2)) || 1038 (ctlr->chip->cfg2 == PR_SATA2) || 1039 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) 1040 return (ata_sata_getrev(dev, target)); 1041 else 1042 return (0); 1043 } 1044 1045 static void 1046 ata_promise_sx4_intr(void *data) 1047 { 1048 struct ata_pci_controller *ctlr = data; 1049 struct ata_channel *ch; 1050 u_int32_t vector = ATA_INL(ctlr->r_res2, 0x000c0480); 1051 int unit; 1052 1053 for (unit = 0; unit < ctlr->channels; unit++) { 1054 if (vector & (1 << (unit + 1))) 1055 if ((ch = ctlr->interrupt[unit].argument)) 1056 ctlr->interrupt[unit].function(ch); 1057 if (vector & (1 << (unit + 5))) 1058 if ((ch = ctlr->interrupt[unit].argument)) 1059 ata_promise_queue_hpkt(ctlr, 1060 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + 1061 ATA_PDC_HPKT_OFFSET)); 1062 if (vector & (1 << (unit + 9))) { 1063 ata_promise_next_hpkt(ctlr); 1064 if ((ch = ctlr->interrupt[unit].argument)) 1065 ctlr->interrupt[unit].function(ch); 1066 } 1067 if (vector & (1 << (unit + 13))) { 1068 ata_promise_next_hpkt(ctlr); 1069 if ((ch = ctlr->interrupt[unit].argument)) 1070 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 1071 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + 1072 ATA_PDC_APKT_OFFSET)); 1073 } 1074 } 1075 } 1076 1077 static int 1078 ata_promise_sx4_command(struct ata_request *request) 1079 { 1080 device_t gparent = device_get_parent(request->parent); 1081 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1082 struct ata_channel *ch = device_get_softc(request->parent); 1083 struct ata_dma_prdentry *prd; 1084 caddr_t window = rman_get_virtual(ctlr->r_res1); 1085 u_int32_t *wordp; 1086 int i, idx; 1087 1088 /* XXX SOS add ATAPI commands support later */ 1089 switch (request->u.ata.command) { 1090 1091 default: 1092 return -1; 1093 1094 case ATA_ATA_IDENTIFY: 1095 case ATA_READ: 1096 case ATA_READ48: 1097 case ATA_READ_MUL: 1098 case ATA_READ_MUL48: 1099 case ATA_WRITE: 1100 case ATA_WRITE48: 1101 case ATA_WRITE_MUL: 1102 case ATA_WRITE_MUL48: 1103 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001); 1104 return ata_generic_command(request); 1105 1106 case ATA_SETFEATURES: 1107 case ATA_FLUSHCACHE: 1108 case ATA_FLUSHCACHE48: 1109 case ATA_SLEEP: 1110 case ATA_SET_MULTI: 1111 wordp = (u_int32_t *) 1112 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET); 1113 wordp[0] = htole32(0x08 | ((ch->unit + 1)<<16) | (0x00 << 24)); 1114 wordp[1] = 0; 1115 wordp[2] = 0; 1116 ata_promise_apkt((u_int8_t *)wordp, request); 1117 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001); 1118 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001); 1119 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 1120 htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_APKT_OFFSET)); 1121 return 0; 1122 1123 case ATA_READ_DMA: 1124 case ATA_READ_DMA48: 1125 case ATA_WRITE_DMA: 1126 case ATA_WRITE_DMA48: 1127 prd = request->dma->sg; 1128 wordp = (u_int32_t *) 1129 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HSG_OFFSET); 1130 i = idx = 0; 1131 do { 1132 wordp[idx++] = prd[i].addr; 1133 wordp[idx++] = prd[i].count; 1134 } while (!(prd[i++].count & ATA_DMA_EOT)); 1135 1136 wordp = (u_int32_t *) 1137 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_LSG_OFFSET); 1138 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE); 1139 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT); 1140 1141 wordp = (u_int32_t *) 1142 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_ASG_OFFSET); 1143 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE); 1144 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT); 1145 1146 wordp = (u_int32_t *) 1147 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET); 1148 if (request->flags & ATA_R_READ) 1149 wordp[0] = htole32(0x14 | ((ch->unit+9)<<16) | ((ch->unit+5)<<24)); 1150 if (request->flags & ATA_R_WRITE) 1151 wordp[0] = htole32(0x00 | ((ch->unit+13)<<16) | (0x00<<24)); 1152 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_HSG_OFFSET); 1153 wordp[2] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_LSG_OFFSET); 1154 wordp[3] = 0; 1155 1156 wordp = (u_int32_t *) 1157 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET); 1158 if (request->flags & ATA_R_READ) 1159 wordp[0] = htole32(0x04 | ((ch->unit+5)<<16) | (0x00<<24)); 1160 if (request->flags & ATA_R_WRITE) 1161 wordp[0] = htole32(0x10 | ((ch->unit+1)<<16) | ((ch->unit+13)<<24)); 1162 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_ASG_OFFSET); 1163 wordp[2] = 0; 1164 ata_promise_apkt((u_int8_t *)wordp, request); 1165 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001); 1166 1167 if (request->flags & ATA_R_READ) { 1168 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+5)<<2), 0x00000001); 1169 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+9)<<2), 0x00000001); 1170 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 1171 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET)); 1172 } 1173 if (request->flags & ATA_R_WRITE) { 1174 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+1)<<2), 0x00000001); 1175 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+13)<<2), 0x00000001); 1176 ata_promise_queue_hpkt(ctlr, 1177 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET)); 1178 } 1179 return 0; 1180 } 1181 } 1182 1183 static int 1184 ata_promise_apkt(u_int8_t *bytep, struct ata_request *request) 1185 { 1186 int i = 12; 1187 1188 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_PDC_WAIT_NBUSY|ATA_DRIVE; 1189 bytep[i++] = ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit); 1190 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_CTL; 1191 bytep[i++] = ATA_A_4BIT; 1192 1193 if (request->flags & ATA_R_48BIT) { 1194 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_FEATURE; 1195 bytep[i++] = request->u.ata.feature >> 8; 1196 bytep[i++] = request->u.ata.feature; 1197 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_COUNT; 1198 bytep[i++] = request->u.ata.count >> 8; 1199 bytep[i++] = request->u.ata.count; 1200 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_SECTOR; 1201 bytep[i++] = request->u.ata.lba >> 24; 1202 bytep[i++] = request->u.ata.lba; 1203 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_LSB; 1204 bytep[i++] = request->u.ata.lba >> 32; 1205 bytep[i++] = request->u.ata.lba >> 8; 1206 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_MSB; 1207 bytep[i++] = request->u.ata.lba >> 40; 1208 bytep[i++] = request->u.ata.lba >> 16; 1209 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE; 1210 bytep[i++] = ATA_D_LBA | ATA_DEV(request->unit); 1211 } 1212 else { 1213 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_FEATURE; 1214 bytep[i++] = request->u.ata.feature; 1215 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_COUNT; 1216 bytep[i++] = request->u.ata.count; 1217 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_SECTOR; 1218 bytep[i++] = request->u.ata.lba; 1219 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_LSB; 1220 bytep[i++] = request->u.ata.lba >> 8; 1221 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_MSB; 1222 bytep[i++] = request->u.ata.lba >> 16; 1223 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE; 1224 bytep[i++] = ATA_D_LBA | ATA_D_IBM | ATA_DEV(request->unit) | 1225 ((request->u.ata.lba >> 24)&0xf); 1226 } 1227 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_END | ATA_COMMAND; 1228 bytep[i++] = request->u.ata.command; 1229 return i; 1230 } 1231 1232 static void 1233 ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt) 1234 { 1235 struct ata_promise_sx4 *hpktp = ctlr->chipset_data; 1236 1237 mtx_lock(&hpktp->mtx); 1238 if (hpktp->busy) { 1239 struct host_packet *hp = 1240 malloc(sizeof(struct host_packet), M_TEMP, M_NOWAIT | M_ZERO); 1241 hp->addr = hpkt; 1242 TAILQ_INSERT_TAIL(&hpktp->queue, hp, chain); 1243 } 1244 else { 1245 hpktp->busy = 1; 1246 ATA_OUTL(ctlr->r_res2, 0x000c0100, hpkt); 1247 } 1248 mtx_unlock(&hpktp->mtx); 1249 } 1250 1251 static void 1252 ata_promise_next_hpkt(struct ata_pci_controller *ctlr) 1253 { 1254 struct ata_promise_sx4 *hpktp = ctlr->chipset_data; 1255 struct host_packet *hp; 1256 1257 mtx_lock(&hpktp->mtx); 1258 if ((hp = TAILQ_FIRST(&hpktp->queue))) { 1259 TAILQ_REMOVE(&hpktp->queue, hp, chain); 1260 ATA_OUTL(ctlr->r_res2, 0x000c0100, hp->addr); 1261 free(hp, M_TEMP); 1262 } 1263 else 1264 hpktp->busy = 0; 1265 mtx_unlock(&hpktp->mtx); 1266 } 1267 1268 ATA_DECLARE_DRIVER(ata_promise); 1269