1 /*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ata.h" 31 #include <sys/param.h> 32 #include <sys/module.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/ata.h> 36 #include <sys/bus.h> 37 #include <sys/endian.h> 38 #include <sys/malloc.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/sema.h> 42 #include <sys/taskqueue.h> 43 #include <vm/uma.h> 44 #include <machine/stdarg.h> 45 #include <machine/resource.h> 46 #include <machine/bus.h> 47 #include <sys/rman.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/ata/ata-all.h> 51 #include <dev/ata/ata-pci.h> 52 #include <ata_if.h> 53 54 /* local prototypes */ 55 static int ata_promise_chipinit(device_t dev); 56 static int ata_promise_ch_attach(device_t dev); 57 static int ata_promise_status(device_t dev); 58 static int ata_promise_dmastart(struct ata_request *request); 59 static int ata_promise_dmastop(struct ata_request *request); 60 static void ata_promise_dmareset(device_t dev); 61 static void ata_promise_setmode(device_t dev, int mode); 62 static int ata_promise_tx2_ch_attach(device_t dev); 63 static int ata_promise_tx2_status(device_t dev); 64 static int ata_promise_mio_ch_attach(device_t dev); 65 static int ata_promise_mio_ch_detach(device_t dev); 66 static void ata_promise_mio_intr(void *data); 67 static int ata_promise_mio_status(device_t dev); 68 static int ata_promise_mio_command(struct ata_request *request); 69 static void ata_promise_mio_reset(device_t dev); 70 static int ata_promise_mio_pm_read(device_t dev, int port, int reg, u_int32_t *result); 71 static int ata_promise_mio_pm_write(device_t dev, int port, int reg, u_int32_t result); 72 static u_int32_t ata_promise_mio_softreset(device_t dev, int port); 73 static void ata_promise_mio_dmainit(device_t dev); 74 static void ata_promise_mio_setprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 75 static void ata_promise_mio_setmode(device_t dev, int mode); 76 static void ata_promise_sx4_intr(void *data); 77 static int ata_promise_sx4_command(struct ata_request *request); 78 static int ata_promise_apkt(u_int8_t *bytep, struct ata_request *request); 79 static void ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt); 80 static void ata_promise_next_hpkt(struct ata_pci_controller *ctlr); 81 82 /* misc defines */ 83 #define PR_OLD 0 84 #define PR_NEW 1 85 #define PR_TX 2 86 #define PR_MIO 3 87 #define PR_TX4 0x01 88 #define PR_SX4X 0x02 89 #define PR_SX6K 0x04 90 #define PR_PATA 0x08 91 #define PR_CMBO 0x10 92 #define PR_CMBO2 0x20 93 #define PR_SATA 0x40 94 #define PR_SATA2 0x80 95 96 97 /* 98 * Promise chipset support functions 99 */ 100 #define ATA_PDC_APKT_OFFSET 0x00000010 101 #define ATA_PDC_HPKT_OFFSET 0x00000040 102 #define ATA_PDC_ASG_OFFSET 0x00000080 103 #define ATA_PDC_LSG_OFFSET 0x000000c0 104 #define ATA_PDC_HSG_OFFSET 0x00000100 105 #define ATA_PDC_CHN_OFFSET 0x00000400 106 #define ATA_PDC_BUF_BASE 0x00400000 107 #define ATA_PDC_BUF_OFFSET 0x00100000 108 #define ATA_PDC_MAX_HPKT 8 109 #define ATA_PDC_WRITE_REG 0x00 110 #define ATA_PDC_WRITE_CTL 0x0e 111 #define ATA_PDC_WRITE_END 0x08 112 #define ATA_PDC_WAIT_NBUSY 0x10 113 #define ATA_PDC_WAIT_READY 0x18 114 #define ATA_PDC_1B 0x20 115 #define ATA_PDC_2B 0x40 116 117 struct host_packet { 118 u_int32_t addr; 119 TAILQ_ENTRY(host_packet) chain; 120 }; 121 122 struct ata_promise_sx4 { 123 struct mtx mtx; 124 TAILQ_HEAD(, host_packet) queue; 125 int busy; 126 }; 127 128 static int 129 ata_promise_probe(device_t dev) 130 { 131 struct ata_pci_controller *ctlr = device_get_softc(dev); 132 struct ata_chip_id *idx; 133 static struct ata_chip_id ids[] = 134 {{ ATA_PDC20246, 0, PR_OLD, 0x00, ATA_UDMA2, "PDC20246" }, 135 { ATA_PDC20262, 0, PR_NEW, 0x00, ATA_UDMA4, "PDC20262" }, 136 { ATA_PDC20263, 0, PR_NEW, 0x00, ATA_UDMA4, "PDC20263" }, 137 { ATA_PDC20265, 0, PR_NEW, 0x00, ATA_UDMA5, "PDC20265" }, 138 { ATA_PDC20267, 0, PR_NEW, 0x00, ATA_UDMA5, "PDC20267" }, 139 { ATA_PDC20268, 0, PR_TX, PR_TX4, ATA_UDMA5, "PDC20268" }, 140 { ATA_PDC20269, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20269" }, 141 { ATA_PDC20270, 0, PR_TX, PR_TX4, ATA_UDMA5, "PDC20270" }, 142 { ATA_PDC20271, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20271" }, 143 { ATA_PDC20275, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20275" }, 144 { ATA_PDC20276, 0, PR_TX, PR_SX6K, ATA_UDMA6, "PDC20276" }, 145 { ATA_PDC20277, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20277" }, 146 { ATA_PDC20318, 0, PR_MIO, PR_SATA, ATA_SA150, "PDC20318" }, 147 { ATA_PDC20319, 0, PR_MIO, PR_SATA, ATA_SA150, "PDC20319" }, 148 { ATA_PDC20371, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20371" }, 149 { ATA_PDC20375, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20375" }, 150 { ATA_PDC20376, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20376" }, 151 { ATA_PDC20377, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20377" }, 152 { ATA_PDC20378, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20378" }, 153 { ATA_PDC20379, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20379" }, 154 { ATA_PDC20571, 0, PR_MIO, PR_CMBO2, ATA_SA150, "PDC20571" }, 155 { ATA_PDC20575, 0, PR_MIO, PR_CMBO2, ATA_SA150, "PDC20575" }, 156 { ATA_PDC20579, 0, PR_MIO, PR_CMBO2, ATA_SA150, "PDC20579" }, 157 { ATA_PDC20771, 0, PR_MIO, PR_CMBO2, ATA_SA300, "PDC20771" }, 158 { ATA_PDC40775, 0, PR_MIO, PR_CMBO2, ATA_SA300, "PDC40775" }, 159 { ATA_PDC20617, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20617" }, 160 { ATA_PDC20618, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20618" }, 161 { ATA_PDC20619, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20619" }, 162 { ATA_PDC20620, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20620" }, 163 { ATA_PDC20621, 0, PR_MIO, PR_SX4X, ATA_UDMA5, "PDC20621" }, 164 { ATA_PDC20622, 0, PR_MIO, PR_SX4X, ATA_SA150, "PDC20622" }, 165 { ATA_PDC40518, 0, PR_MIO, PR_SATA2, ATA_SA150, "PDC40518" }, 166 { ATA_PDC40519, 0, PR_MIO, PR_SATA2, ATA_SA150, "PDC40519" }, 167 { ATA_PDC40718, 0, PR_MIO, PR_SATA2, ATA_SA300, "PDC40718" }, 168 { ATA_PDC40719, 0, PR_MIO, PR_SATA2, ATA_SA300, "PDC40719" }, 169 { ATA_PDC40779, 0, PR_MIO, PR_SATA2, ATA_SA300, "PDC40779" }, 170 { 0, 0, 0, 0, 0, 0}}; 171 char buffer[64]; 172 uintptr_t devid = 0; 173 174 if (pci_get_vendor(dev) != ATA_PROMISE_ID) 175 return ENXIO; 176 177 if (!(idx = ata_match_chip(dev, ids))) 178 return ENXIO; 179 180 /* if we are on a SuperTrak SX6000 dont attach */ 181 if ((idx->cfg2 & PR_SX6K) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE && 182 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), 183 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && 184 devid == ATA_I960RM) 185 return ENXIO; 186 187 strcpy(buffer, "Promise "); 188 strcat(buffer, idx->text); 189 190 /* if we are on a FastTrak TX4, adjust the interrupt resource */ 191 if ((idx->cfg2 & PR_TX4) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE && 192 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), 193 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && 194 ((devid == ATA_DEC_21150) || (devid == ATA_DEC_21150_1))) { 195 static long start = 0, end = 0; 196 197 if (pci_get_slot(dev) == 1) { 198 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end); 199 strcat(buffer, " (channel 0+1)"); 200 } 201 else if (pci_get_slot(dev) == 2 && start && end) { 202 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end); 203 strcat(buffer, " (channel 2+3)"); 204 } 205 else { 206 start = end = 0; 207 } 208 } 209 sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma)); 210 device_set_desc_copy(dev, buffer); 211 ctlr->chip = idx; 212 ctlr->chipinit = ata_promise_chipinit; 213 return 0; 214 } 215 216 static int 217 ata_promise_chipinit(device_t dev) 218 { 219 struct ata_pci_controller *ctlr = device_get_softc(dev); 220 int fake_reg, stat_reg; 221 222 if (ata_setup_interrupt(dev, ata_generic_intr)) 223 return ENXIO; 224 225 switch (ctlr->chip->cfg1) { 226 case PR_NEW: 227 /* setup clocks */ 228 ATA_OUTB(ctlr->r_res1, 0x11, ATA_INB(ctlr->r_res1, 0x11) | 0x0a); 229 /* FALLTHROUGH */ 230 231 case PR_OLD: 232 /* enable burst mode */ 233 ATA_OUTB(ctlr->r_res1, 0x1f, ATA_INB(ctlr->r_res1, 0x1f) | 0x01); 234 ctlr->ch_attach = ata_promise_ch_attach; 235 ctlr->ch_detach = ata_pci_ch_detach; 236 ctlr->setmode = ata_promise_setmode; 237 return 0; 238 239 case PR_TX: 240 ctlr->ch_attach = ata_promise_tx2_ch_attach; 241 ctlr->ch_detach = ata_pci_ch_detach; 242 ctlr->setmode = ata_promise_setmode; 243 return 0; 244 245 case PR_MIO: 246 ctlr->r_type1 = SYS_RES_MEMORY; 247 ctlr->r_rid1 = PCIR_BAR(4); 248 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 249 &ctlr->r_rid1, RF_ACTIVE))) 250 goto failnfree; 251 252 ctlr->r_type2 = SYS_RES_MEMORY; 253 ctlr->r_rid2 = PCIR_BAR(3); 254 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 255 &ctlr->r_rid2, RF_ACTIVE))) 256 goto failnfree; 257 258 if (ctlr->chip->cfg2 == PR_SX4X) { 259 struct ata_promise_sx4 *hpkt; 260 u_int32_t dimm = ATA_INL(ctlr->r_res2, 0x000c0080); 261 262 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) || 263 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, NULL, 264 ata_promise_sx4_intr, ctlr, &ctlr->handle)) { 265 device_printf(dev, "unable to setup interrupt\n"); 266 goto failnfree; 267 } 268 269 /* print info about cache memory */ 270 device_printf(dev, "DIMM size %dMB @ 0x%08x%s\n", 271 (((dimm >> 16) & 0xff)-((dimm >> 24) & 0xff)+1) << 4, 272 ((dimm >> 24) & 0xff), 273 ATA_INL(ctlr->r_res2, 0x000c0088) & (1<<16) ? 274 " ECC enabled" : "" ); 275 276 /* adjust cache memory parameters */ 277 ATA_OUTL(ctlr->r_res2, 0x000c000c, 278 (ATA_INL(ctlr->r_res2, 0x000c000c) & 0xffff0000)); 279 280 /* setup host packet controls */ 281 hpkt = malloc(sizeof(struct ata_promise_sx4), 282 M_TEMP, M_NOWAIT | M_ZERO); 283 mtx_init(&hpkt->mtx, "ATA promise HPKT lock", NULL, MTX_DEF); 284 TAILQ_INIT(&hpkt->queue); 285 hpkt->busy = 0; 286 device_set_ivars(dev, hpkt); 287 ctlr->ch_attach = ata_promise_mio_ch_attach; 288 ctlr->ch_detach = ata_promise_mio_ch_detach; 289 ctlr->reset = ata_promise_mio_reset; 290 ctlr->setmode = ata_promise_setmode; 291 ctlr->channels = 4; 292 return 0; 293 } 294 295 /* mio type controllers need an interrupt intercept */ 296 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) || 297 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, NULL, 298 ata_promise_mio_intr, ctlr, &ctlr->handle)) { 299 device_printf(dev, "unable to setup interrupt\n"); 300 goto failnfree; 301 } 302 303 switch (ctlr->chip->cfg2) { 304 case PR_PATA: 305 ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x01) > 0) + 306 ((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 2; 307 goto sata150; 308 case PR_CMBO: 309 ctlr->channels = 3; 310 goto sata150; 311 case PR_SATA: 312 ctlr->channels = 4; 313 sata150: 314 fake_reg = 0x60; 315 stat_reg = 0x6c; 316 break; 317 318 case PR_CMBO2: 319 ctlr->channels = 3; 320 goto sataii; 321 case PR_SATA2: 322 default: 323 ctlr->channels = 4; 324 sataii: 325 fake_reg = 0x54; 326 stat_reg = 0x60; 327 break; 328 } 329 330 /* prime fake interrupt register */ 331 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff); 332 333 /* clear SATA status and unmask interrupts */ 334 ATA_OUTL(ctlr->r_res2, stat_reg, 0x000000ff); 335 336 /* enable "long burst length" on gen2 chips */ 337 if ((ctlr->chip->cfg2 == PR_SATA2) || (ctlr->chip->cfg2 == PR_CMBO2)) 338 ATA_OUTL(ctlr->r_res2, 0x44, ATA_INL(ctlr->r_res2, 0x44) | 0x2000); 339 340 ctlr->ch_attach = ata_promise_mio_ch_attach; 341 ctlr->ch_detach = ata_promise_mio_ch_detach; 342 ctlr->reset = ata_promise_mio_reset; 343 ctlr->setmode = ata_promise_mio_setmode; 344 345 return 0; 346 } 347 348 failnfree: 349 if (ctlr->r_res2) 350 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2); 351 if (ctlr->r_res1) 352 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1, ctlr->r_res1); 353 return ENXIO; 354 } 355 356 static int 357 ata_promise_ch_attach(device_t dev) 358 { 359 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 360 struct ata_channel *ch = device_get_softc(dev); 361 362 if (ata_pci_ch_attach(dev)) 363 return ENXIO; 364 365 if (ctlr->chip->cfg1 == PR_NEW) { 366 ch->dma.start = ata_promise_dmastart; 367 ch->dma.stop = ata_promise_dmastop; 368 ch->dma.reset = ata_promise_dmareset; 369 } 370 371 ch->hw.status = ata_promise_status; 372 return 0; 373 } 374 375 static int 376 ata_promise_status(device_t dev) 377 { 378 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 379 struct ata_channel *ch = device_get_softc(dev); 380 381 if (ATA_INL(ctlr->r_res1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)) { 382 return ata_pci_status(dev); 383 } 384 return 0; 385 } 386 387 static int 388 ata_promise_dmastart(struct ata_request *request) 389 { 390 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 391 struct ata_channel *ch = device_get_softc(request->parent); 392 struct ata_device *atadev = device_get_softc(request->dev); 393 394 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 395 ATA_OUTB(ctlr->r_res1, 0x11, 396 ATA_INB(ctlr->r_res1, 0x11) | (ch->unit ? 0x08 : 0x02)); 397 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 398 ((request->flags & ATA_R_READ) ? 0x05000000 : 0x06000000) | 399 (request->bytecount >> 1)); 400 } 401 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) | 402 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 403 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, request->dma->sg_bus); 404 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 405 ((request->flags & ATA_R_READ) ? ATA_BMCMD_WRITE_READ : 0) | 406 ATA_BMCMD_START_STOP); 407 ch->dma.flags |= ATA_DMA_ACTIVE; 408 return 0; 409 } 410 411 static int 412 ata_promise_dmastop(struct ata_request *request) 413 { 414 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 415 struct ata_channel *ch = device_get_softc(request->parent); 416 struct ata_device *atadev = device_get_softc(request->dev); 417 int error; 418 419 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 420 ATA_OUTB(ctlr->r_res1, 0x11, 421 ATA_INB(ctlr->r_res1, 0x11) & ~(ch->unit ? 0x08 : 0x02)); 422 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 0); 423 } 424 error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT); 425 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 426 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 427 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 428 ch->dma.flags &= ~ATA_DMA_ACTIVE; 429 return error; 430 } 431 432 static void 433 ata_promise_dmareset(device_t dev) 434 { 435 struct ata_channel *ch = device_get_softc(dev); 436 437 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 438 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 439 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 440 ch->flags &= ~ATA_DMA_ACTIVE; 441 } 442 443 static void 444 ata_promise_setmode(device_t dev, int mode) 445 { 446 device_t gparent = GRANDPARENT(dev); 447 struct ata_pci_controller *ctlr = device_get_softc(gparent); 448 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 449 struct ata_device *atadev = device_get_softc(dev); 450 int devno = (ch->unit << 1) + atadev->unit; 451 int error; 452 u_int32_t timings[][2] = { 453 /* PR_OLD PR_NEW mode */ 454 { 0x004ff329, 0x004fff2f }, /* PIO 0 */ 455 { 0x004fec25, 0x004ff82a }, /* PIO 1 */ 456 { 0x004fe823, 0x004ff026 }, /* PIO 2 */ 457 { 0x004fe622, 0x004fec24 }, /* PIO 3 */ 458 { 0x004fe421, 0x004fe822 }, /* PIO 4 */ 459 { 0x004567f3, 0x004acef6 }, /* MWDMA 0 */ 460 { 0x004467f3, 0x0048cef6 }, /* MWDMA 1 */ 461 { 0x004367f3, 0x0046cef6 }, /* MWDMA 2 */ 462 { 0x004367f3, 0x0046cef6 }, /* UDMA 0 */ 463 { 0x004247f3, 0x00448ef6 }, /* UDMA 1 */ 464 { 0x004127f3, 0x00436ef6 }, /* UDMA 2 */ 465 { 0, 0x00424ef6 }, /* UDMA 3 */ 466 { 0, 0x004127f3 }, /* UDMA 4 */ 467 { 0, 0x004127f3 } /* UDMA 5 */ 468 }; 469 470 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 471 472 switch (ctlr->chip->cfg1) { 473 case PR_OLD: 474 case PR_NEW: 475 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x50, 2) & 476 (ch->unit ? 1 << 11 : 1 << 10))) { 477 ata_print_cable(dev, "controller"); 478 mode = ATA_UDMA2; 479 } 480 if (ata_atapi(dev) && mode > ATA_PIO_MAX) 481 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX); 482 break; 483 484 case PR_TX: 485 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b); 486 if (mode > ATA_UDMA2 && 487 ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x04) { 488 ata_print_cable(dev, "controller"); 489 mode = ATA_UDMA2; 490 } 491 break; 492 493 case PR_MIO: 494 if (mode > ATA_UDMA2 && 495 (ATA_INL(ctlr->r_res2, 496 (ctlr->chip->cfg2 & PR_SX4X ? 0x000c0260 : 0x0260) + 497 (ch->unit << 7)) & 0x01000000)) { 498 ata_print_cable(dev, "controller"); 499 mode = ATA_UDMA2; 500 } 501 break; 502 } 503 504 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 505 506 if (bootverbose) 507 device_printf(dev, "%ssetting %s on %s chip\n", 508 (error) ? "FAILURE " : "", 509 ata_mode2str(mode), ctlr->chip->text); 510 if (!error) { 511 if (ctlr->chip->cfg1 < PR_TX) 512 pci_write_config(gparent, 0x60 + (devno << 2), 513 timings[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); 514 atadev->mode = mode; 515 } 516 return; 517 } 518 519 static int 520 ata_promise_tx2_ch_attach(device_t dev) 521 { 522 struct ata_channel *ch = device_get_softc(dev); 523 524 if (ata_pci_ch_attach(dev)) 525 return ENXIO; 526 527 ch->hw.status = ata_promise_tx2_status; 528 return 0; 529 } 530 531 static int 532 ata_promise_tx2_status(device_t dev) 533 { 534 struct ata_channel *ch = device_get_softc(dev); 535 536 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b); 537 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) { 538 return ata_pci_status(dev); 539 } 540 return 0; 541 } 542 543 static int 544 ata_promise_mio_ch_attach(device_t dev) 545 { 546 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 547 struct ata_channel *ch = device_get_softc(dev); 548 int offset = (ctlr->chip->cfg2 & PR_SX4X) ? 0x000c0000 : 0; 549 int i; 550 551 ata_promise_mio_dmainit(dev); 552 553 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 554 ch->r_io[i].res = ctlr->r_res2; 555 ch->r_io[i].offset = offset + 0x0200 + (i << 2) + (ch->unit << 7); 556 } 557 ch->r_io[ATA_CONTROL].res = ctlr->r_res2; 558 ch->r_io[ATA_CONTROL].offset = offset + 0x0238 + (ch->unit << 7); 559 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 560 ata_default_registers(dev); 561 if ((ctlr->chip->cfg2 & (PR_SATA | PR_SATA2)) || 562 ((ctlr->chip->cfg2 & (PR_CMBO | PR_CMBO2)) && ch->unit < 2)) { 563 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 564 ch->r_io[ATA_SSTATUS].offset = 0x400 + (ch->unit << 8); 565 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 566 ch->r_io[ATA_SERROR].offset = 0x404 + (ch->unit << 8); 567 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 568 ch->r_io[ATA_SCONTROL].offset = 0x408 + (ch->unit << 8); 569 ch->flags |= ATA_NO_SLAVE; 570 } 571 ch->flags |= ATA_USE_16BIT; 572 573 ata_generic_hw(dev); 574 if (ctlr->chip->cfg2 & PR_SX4X) { 575 ch->hw.command = ata_promise_sx4_command; 576 } 577 else { 578 ch->hw.command = ata_promise_mio_command; 579 ch->hw.status = ata_promise_mio_status; 580 ch->hw.softreset = ata_promise_mio_softreset; 581 ch->hw.pm_read = ata_promise_mio_pm_read; 582 ch->hw.pm_write = ata_promise_mio_pm_write; 583 } 584 return 0; 585 } 586 587 static int 588 ata_promise_mio_ch_detach(device_t dev) 589 { 590 591 ata_dmafini(dev); 592 return (0); 593 } 594 595 static void 596 ata_promise_mio_intr(void *data) 597 { 598 struct ata_pci_controller *ctlr = data; 599 struct ata_channel *ch; 600 u_int32_t vector; 601 int unit, fake_reg; 602 603 switch (ctlr->chip->cfg2) { 604 case PR_PATA: 605 case PR_CMBO: 606 case PR_SATA: 607 fake_reg = 0x60; 608 break; 609 case PR_CMBO2: 610 case PR_SATA2: 611 default: 612 fake_reg = 0x54; 613 break; 614 } 615 616 /* 617 * since reading interrupt status register on early "mio" chips 618 * clears the status bits we cannot read it for each channel later on 619 * in the generic interrupt routine. 620 * store the bits in an unused register in the chip so we can read 621 * it from there safely to get around this "feature". 622 */ 623 vector = ATA_INL(ctlr->r_res2, 0x040); 624 ATA_OUTL(ctlr->r_res2, 0x040, vector); 625 ATA_OUTL(ctlr->r_res2, fake_reg, vector); 626 627 for (unit = 0; unit < ctlr->channels; unit++) { 628 if ((ch = ctlr->interrupt[unit].argument)) 629 ctlr->interrupt[unit].function(ch); 630 } 631 632 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff); 633 } 634 635 static int 636 ata_promise_mio_status(device_t dev) 637 { 638 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 639 struct ata_channel *ch = device_get_softc(dev); 640 u_int32_t fake_reg, stat_reg, vector, status; 641 642 switch (ctlr->chip->cfg2) { 643 case PR_PATA: 644 case PR_CMBO: 645 case PR_SATA: 646 fake_reg = 0x60; 647 stat_reg = 0x6c; 648 break; 649 case PR_CMBO2: 650 case PR_SATA2: 651 default: 652 fake_reg = 0x54; 653 stat_reg = 0x60; 654 break; 655 } 656 657 /* read and acknowledge interrupt */ 658 vector = ATA_INL(ctlr->r_res2, fake_reg); 659 660 /* read and clear interface status */ 661 status = ATA_INL(ctlr->r_res2, stat_reg); 662 ATA_OUTL(ctlr->r_res2, stat_reg, status & (0x00000011 << ch->unit)); 663 664 /* check for and handle disconnect events */ 665 if (status & (0x00000001 << ch->unit)) { 666 if (bootverbose) 667 device_printf(dev, "DISCONNECT requested\n"); 668 taskqueue_enqueue(taskqueue_thread, &ch->conntask); 669 } 670 671 /* check for and handle connect events */ 672 if (status & (0x00000010 << ch->unit)) { 673 if (bootverbose) 674 device_printf(dev, "CONNECT requested\n"); 675 taskqueue_enqueue(taskqueue_thread, &ch->conntask); 676 } 677 678 /* do we have any device action ? */ 679 return (vector & (1 << (ch->unit + 1))); 680 } 681 682 static int 683 ata_promise_mio_command(struct ata_request *request) 684 { 685 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 686 struct ata_channel *ch = device_get_softc(request->parent); 687 struct ata_device *atadev = device_get_softc(request->dev); 688 689 u_int32_t *wordp = (u_int32_t *)ch->dma.work; 690 691 ATA_OUTL(ctlr->r_res2, (ch->unit + 1) << 2, 0x00000001); 692 693 /* set portmultiplier port */ 694 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), atadev->unit & 0x0f); 695 696 /* XXX SOS add ATAPI commands support later */ 697 switch (request->u.ata.command) { 698 default: 699 return ata_generic_command(request); 700 701 case ATA_READ_DMA: 702 case ATA_READ_DMA48: 703 wordp[0] = htole32(0x04 | ((ch->unit + 1) << 16) | (0x00 << 24)); 704 break; 705 706 case ATA_WRITE_DMA: 707 case ATA_WRITE_DMA48: 708 wordp[0] = htole32(0x00 | ((ch->unit + 1) << 16) | (0x00 << 24)); 709 break; 710 } 711 wordp[1] = htole32(request->dma->sg_bus); 712 wordp[2] = 0; 713 ata_promise_apkt((u_int8_t*)wordp, request); 714 715 ATA_OUTL(ctlr->r_res2, 0x0240 + (ch->unit << 7), ch->dma.work_bus); 716 return 0; 717 } 718 719 static void 720 ata_promise_mio_reset(device_t dev) 721 { 722 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 723 struct ata_channel *ch = device_get_softc(dev); 724 struct ata_promise_sx4 *hpktp; 725 726 switch (ctlr->chip->cfg2) { 727 case PR_SX4X: 728 729 /* softreset channel ATA module */ 730 hpktp = device_get_ivars(ctlr->dev); 731 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), ch->unit + 1); 732 ata_udelay(1000); 733 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), 734 (ATA_INL(ctlr->r_res2, 0xc0260 + (ch->unit << 7)) & 735 ~0x00003f9f) | (ch->unit + 1)); 736 737 /* softreset HOST module */ /* XXX SOS what about other outstandings */ 738 mtx_lock(&hpktp->mtx); 739 ATA_OUTL(ctlr->r_res2, 0xc012c, 740 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f) | (1 << 11)); 741 DELAY(10); 742 ATA_OUTL(ctlr->r_res2, 0xc012c, 743 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f)); 744 hpktp->busy = 0; 745 mtx_unlock(&hpktp->mtx); 746 ata_generic_reset(dev); 747 break; 748 749 case PR_PATA: 750 case PR_CMBO: 751 case PR_SATA: 752 if ((ctlr->chip->cfg2 == PR_SATA) || 753 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2))) { 754 755 /* mask plug/unplug intr */ 756 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00110000 << ch->unit)); 757 } 758 759 /* softreset channels ATA module */ 760 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11)); 761 ata_udelay(10000); 762 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), 763 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) & 764 ~0x00003f9f) | (ch->unit + 1)); 765 766 if ((ctlr->chip->cfg2 == PR_SATA) || 767 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2))) { 768 769 if (ata_sata_phy_reset(dev)) 770 ata_generic_reset(dev); 771 772 /* reset and enable plug/unplug intr */ 773 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00000011 << ch->unit)); 774 } 775 else 776 ata_generic_reset(dev); 777 break; 778 779 case PR_CMBO2: 780 case PR_SATA2: 781 if ((ctlr->chip->cfg2 == PR_SATA2) || 782 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) { 783 /* set portmultiplier port */ 784 //ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f); 785 786 /* mask plug/unplug intr */ 787 ATA_OUTL(ctlr->r_res2, 0x060, (0x00110000 << ch->unit)); 788 } 789 790 /* softreset channels ATA module */ 791 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11)); 792 ata_udelay(10000); 793 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), 794 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) & 795 ~0x00003f9f) | (ch->unit + 1)); 796 797 if ((ctlr->chip->cfg2 == PR_SATA2) || 798 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) { 799 800 /* set PHY mode to "improved" */ 801 ATA_OUTL(ctlr->r_res2, 0x414 + (ch->unit << 8), 802 (ATA_INL(ctlr->r_res2, 0x414 + (ch->unit << 8)) & 803 ~0x00000003) | 0x00000001); 804 805 if (ata_sata_phy_reset(dev)) { 806 u_int32_t signature = ch->hw.softreset(dev, ATA_PM); 807 808 if (1 | bootverbose) 809 device_printf(dev, "SIGNATURE: %08x\n", signature); 810 811 switch (signature >> 16) { 812 case 0x0000: 813 ch->devices = ATA_ATA_MASTER; 814 break; 815 case 0x9669: 816 ch->devices = ATA_PORTMULTIPLIER; 817 ata_pm_identify(dev); 818 break; 819 case 0xeb14: 820 ch->devices = ATA_ATAPI_MASTER; 821 break; 822 default: /* SOS XXX */ 823 if (bootverbose) 824 device_printf(dev, 825 "No signature, assuming disk device\n"); 826 ch->devices = ATA_ATA_MASTER; 827 } 828 if (bootverbose) 829 device_printf(dev, "promise_mio_reset devices=%08x\n", 830 ch->devices); 831 832 } 833 834 /* reset and enable plug/unplug intr */ 835 ATA_OUTL(ctlr->r_res2, 0x060, (0x00000011 << ch->unit)); 836 837 ///* set portmultiplier port */ 838 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x00); 839 } 840 else 841 ata_generic_reset(dev); 842 break; 843 844 } 845 } 846 847 static int 848 ata_promise_mio_pm_read(device_t dev, int port, int reg, u_int32_t *result) 849 { 850 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 851 struct ata_channel *ch = device_get_softc(dev); 852 int timeout = 0; 853 854 /* set portmultiplier port */ 855 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f); 856 857 ATA_IDX_OUTB(ch, ATA_FEATURE, reg); 858 ATA_IDX_OUTB(ch, ATA_DRIVE, port); 859 860 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_READ_PM); 861 862 while (timeout < 1000000) { 863 u_int8_t status = ATA_IDX_INB(ch, ATA_STATUS); 864 if (!(status & ATA_S_BUSY)) 865 break; 866 timeout += 1000; 867 DELAY(1000); 868 } 869 if (timeout >= 1000000) 870 return ATA_E_ABORT; 871 872 *result = ATA_IDX_INB(ch, ATA_COUNT) | 873 (ATA_IDX_INB(ch, ATA_SECTOR) << 8) | 874 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 16) | 875 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 24); 876 return 0; 877 } 878 879 static int 880 ata_promise_mio_pm_write(device_t dev, int port, int reg, u_int32_t value) 881 { 882 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 883 struct ata_channel *ch = device_get_softc(dev); 884 int timeout = 0; 885 886 /* set portmultiplier port */ 887 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f); 888 889 ATA_IDX_OUTB(ch, ATA_FEATURE, reg); 890 ATA_IDX_OUTB(ch, ATA_DRIVE, port); 891 ATA_IDX_OUTB(ch, ATA_COUNT, value & 0xff); 892 ATA_IDX_OUTB(ch, ATA_SECTOR, (value >> 8) & 0xff); 893 ATA_IDX_OUTB(ch, ATA_CYL_LSB, (value >> 16) & 0xff); 894 ATA_IDX_OUTB(ch, ATA_CYL_MSB, (value >> 24) & 0xff); 895 896 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_WRITE_PM); 897 898 while (timeout < 1000000) { 899 u_int8_t status = ATA_IDX_INB(ch, ATA_STATUS); 900 if (!(status & ATA_S_BUSY)) 901 break; 902 timeout += 1000; 903 DELAY(1000); 904 } 905 if (timeout >= 1000000) 906 return ATA_E_ABORT; 907 908 return ATA_IDX_INB(ch, ATA_ERROR); 909 } 910 911 /* must be called with ATA channel locked and state_mtx held */ 912 static u_int32_t 913 ata_promise_mio_softreset(device_t dev, int port) 914 { 915 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 916 struct ata_channel *ch = device_get_softc(dev); 917 int timeout; 918 919 /* set portmultiplier port */ 920 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), port & 0x0f); 921 922 /* softreset device on this channel */ 923 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_MASTER)); 924 DELAY(10); 925 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS | ATA_A_RESET); 926 ata_udelay(10000); 927 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS); 928 ata_udelay(150000); 929 ATA_IDX_INB(ch, ATA_ERROR); 930 931 /* wait for BUSY to go inactive */ 932 for (timeout = 0; timeout < 100; timeout++) { 933 u_int8_t err, stat; 934 935 err = ATA_IDX_INB(ch, ATA_ERROR); 936 stat = ATA_IDX_INB(ch, ATA_STATUS); 937 938 //if (stat == err && timeout > (stat & ATA_S_BUSY ? 100 : 10)) 939 //break; 940 941 if (!(stat & ATA_S_BUSY)) { 942 //if ((err & 0x7f) == ATA_E_ILI) { 943 return ATA_IDX_INB(ch, ATA_COUNT) | 944 (ATA_IDX_INB(ch, ATA_SECTOR) << 8) | 945 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 16) | 946 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 24); 947 //} 948 //else if (stat & 0x0f) { 949 //stat |= ATA_S_BUSY; 950 //} 951 } 952 953 if (!(stat & ATA_S_BUSY) || (stat == 0xff && timeout > 10)) 954 break; 955 ata_udelay(100000); 956 } 957 return -1; 958 } 959 960 static void 961 ata_promise_mio_dmainit(device_t dev) 962 { 963 struct ata_channel *ch = device_get_softc(dev); 964 965 ata_dmainit(dev); 966 /* note start and stop are not used here */ 967 ch->dma.setprd = ata_promise_mio_setprd; 968 } 969 970 971 #define MAXLASTSGSIZE (32 * sizeof(u_int32_t)) 972 static void 973 ata_promise_mio_setprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 974 { 975 struct ata_dmasetprd_args *args = xsc; 976 struct ata_dma_prdentry *prd = args->dmatab; 977 int i; 978 979 if ((args->error = error)) 980 return; 981 982 for (i = 0; i < nsegs; i++) { 983 prd[i].addr = htole32(segs[i].ds_addr); 984 prd[i].count = htole32(segs[i].ds_len); 985 } 986 if (segs[i - 1].ds_len > MAXLASTSGSIZE) { 987 //printf("split last SG element of %u\n", segs[i - 1].ds_len); 988 prd[i - 1].count = htole32(segs[i - 1].ds_len - MAXLASTSGSIZE); 989 prd[i].count = htole32(MAXLASTSGSIZE); 990 prd[i].addr = htole32(segs[i - 1].ds_addr + 991 (segs[i - 1].ds_len - MAXLASTSGSIZE)); 992 nsegs++; 993 i++; 994 } 995 prd[i - 1].count |= htole32(ATA_DMA_EOT); 996 KASSERT(nsegs <= ATA_DMA_ENTRIES, ("too many DMA segment entries\n")); 997 args->nsegs = nsegs; 998 } 999 1000 static void 1001 ata_promise_mio_setmode(device_t dev, int mode) 1002 { 1003 device_t gparent = GRANDPARENT(dev); 1004 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1005 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1006 1007 if ( (ctlr->chip->cfg2 == PR_SATA) || 1008 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2)) || 1009 (ctlr->chip->cfg2 == PR_SATA2) || 1010 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) 1011 ata_sata_setmode(dev, mode); 1012 else 1013 ata_promise_setmode(dev, mode); 1014 } 1015 1016 static void 1017 ata_promise_sx4_intr(void *data) 1018 { 1019 struct ata_pci_controller *ctlr = data; 1020 struct ata_channel *ch; 1021 u_int32_t vector = ATA_INL(ctlr->r_res2, 0x000c0480); 1022 int unit; 1023 1024 for (unit = 0; unit < ctlr->channels; unit++) { 1025 if (vector & (1 << (unit + 1))) 1026 if ((ch = ctlr->interrupt[unit].argument)) 1027 ctlr->interrupt[unit].function(ch); 1028 if (vector & (1 << (unit + 5))) 1029 if ((ch = ctlr->interrupt[unit].argument)) 1030 ata_promise_queue_hpkt(ctlr, 1031 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + 1032 ATA_PDC_HPKT_OFFSET)); 1033 if (vector & (1 << (unit + 9))) { 1034 ata_promise_next_hpkt(ctlr); 1035 if ((ch = ctlr->interrupt[unit].argument)) 1036 ctlr->interrupt[unit].function(ch); 1037 } 1038 if (vector & (1 << (unit + 13))) { 1039 ata_promise_next_hpkt(ctlr); 1040 if ((ch = ctlr->interrupt[unit].argument)) 1041 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 1042 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + 1043 ATA_PDC_APKT_OFFSET)); 1044 } 1045 } 1046 } 1047 1048 static int 1049 ata_promise_sx4_command(struct ata_request *request) 1050 { 1051 device_t gparent = GRANDPARENT(request->dev); 1052 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1053 struct ata_channel *ch = device_get_softc(request->parent); 1054 struct ata_dma_prdentry *prd = request->dma->sg; 1055 caddr_t window = rman_get_virtual(ctlr->r_res1); 1056 u_int32_t *wordp; 1057 int i, idx, length = 0; 1058 1059 /* XXX SOS add ATAPI commands support later */ 1060 switch (request->u.ata.command) { 1061 1062 default: 1063 return -1; 1064 1065 case ATA_ATA_IDENTIFY: 1066 case ATA_READ: 1067 case ATA_READ48: 1068 case ATA_READ_MUL: 1069 case ATA_READ_MUL48: 1070 case ATA_WRITE: 1071 case ATA_WRITE48: 1072 case ATA_WRITE_MUL: 1073 case ATA_WRITE_MUL48: 1074 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001); 1075 return ata_generic_command(request); 1076 1077 case ATA_SETFEATURES: 1078 case ATA_FLUSHCACHE: 1079 case ATA_FLUSHCACHE48: 1080 case ATA_SLEEP: 1081 case ATA_SET_MULTI: 1082 wordp = (u_int32_t *) 1083 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET); 1084 wordp[0] = htole32(0x08 | ((ch->unit + 1)<<16) | (0x00 << 24)); 1085 wordp[1] = 0; 1086 wordp[2] = 0; 1087 ata_promise_apkt((u_int8_t *)wordp, request); 1088 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001); 1089 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001); 1090 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 1091 htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_APKT_OFFSET)); 1092 return 0; 1093 1094 case ATA_READ_DMA: 1095 case ATA_READ_DMA48: 1096 case ATA_WRITE_DMA: 1097 case ATA_WRITE_DMA48: 1098 wordp = (u_int32_t *) 1099 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HSG_OFFSET); 1100 i = idx = 0; 1101 do { 1102 wordp[idx++] = prd[i].addr; 1103 wordp[idx++] = prd[i].count; 1104 length += (prd[i].count & ~ATA_DMA_EOT); 1105 } while (!(prd[i++].count & ATA_DMA_EOT)); 1106 1107 wordp = (u_int32_t *) 1108 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_LSG_OFFSET); 1109 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE); 1110 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT); 1111 1112 wordp = (u_int32_t *) 1113 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_ASG_OFFSET); 1114 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE); 1115 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT); 1116 1117 wordp = (u_int32_t *) 1118 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET); 1119 if (request->flags & ATA_R_READ) 1120 wordp[0] = htole32(0x14 | ((ch->unit+9)<<16) | ((ch->unit+5)<<24)); 1121 if (request->flags & ATA_R_WRITE) 1122 wordp[0] = htole32(0x00 | ((ch->unit+13)<<16) | (0x00<<24)); 1123 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_HSG_OFFSET); 1124 wordp[2] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_LSG_OFFSET); 1125 wordp[3] = 0; 1126 1127 wordp = (u_int32_t *) 1128 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET); 1129 if (request->flags & ATA_R_READ) 1130 wordp[0] = htole32(0x04 | ((ch->unit+5)<<16) | (0x00<<24)); 1131 if (request->flags & ATA_R_WRITE) 1132 wordp[0] = htole32(0x10 | ((ch->unit+1)<<16) | ((ch->unit+13)<<24)); 1133 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_ASG_OFFSET); 1134 wordp[2] = 0; 1135 ata_promise_apkt((u_int8_t *)wordp, request); 1136 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001); 1137 1138 if (request->flags & ATA_R_READ) { 1139 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+5)<<2), 0x00000001); 1140 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+9)<<2), 0x00000001); 1141 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 1142 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET)); 1143 } 1144 if (request->flags & ATA_R_WRITE) { 1145 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+1)<<2), 0x00000001); 1146 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+13)<<2), 0x00000001); 1147 ata_promise_queue_hpkt(ctlr, 1148 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET)); 1149 } 1150 return 0; 1151 } 1152 } 1153 1154 static int 1155 ata_promise_apkt(u_int8_t *bytep, struct ata_request *request) 1156 { 1157 struct ata_device *atadev = device_get_softc(request->dev); 1158 int i = 12; 1159 1160 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_PDC_WAIT_NBUSY|ATA_DRIVE; 1161 bytep[i++] = ATA_D_IBM | ATA_D_LBA | ATA_DEV(atadev->unit); 1162 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_CTL; 1163 bytep[i++] = ATA_A_4BIT; 1164 1165 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 1166 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_FEATURE; 1167 bytep[i++] = request->u.ata.feature >> 8; 1168 bytep[i++] = request->u.ata.feature; 1169 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_COUNT; 1170 bytep[i++] = request->u.ata.count >> 8; 1171 bytep[i++] = request->u.ata.count; 1172 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_SECTOR; 1173 bytep[i++] = request->u.ata.lba >> 24; 1174 bytep[i++] = request->u.ata.lba; 1175 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_LSB; 1176 bytep[i++] = request->u.ata.lba >> 32; 1177 bytep[i++] = request->u.ata.lba >> 8; 1178 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_MSB; 1179 bytep[i++] = request->u.ata.lba >> 40; 1180 bytep[i++] = request->u.ata.lba >> 16; 1181 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE; 1182 bytep[i++] = ATA_D_LBA | ATA_DEV(atadev->unit); 1183 } 1184 else { 1185 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_FEATURE; 1186 bytep[i++] = request->u.ata.feature; 1187 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_COUNT; 1188 bytep[i++] = request->u.ata.count; 1189 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_SECTOR; 1190 bytep[i++] = request->u.ata.lba; 1191 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_LSB; 1192 bytep[i++] = request->u.ata.lba >> 8; 1193 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_MSB; 1194 bytep[i++] = request->u.ata.lba >> 16; 1195 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE; 1196 bytep[i++] = (atadev->flags & ATA_D_USE_CHS ? 0 : ATA_D_LBA) | 1197 ATA_D_IBM | ATA_DEV(atadev->unit) | 1198 ((request->u.ata.lba >> 24)&0xf); 1199 } 1200 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_END | ATA_COMMAND; 1201 bytep[i++] = request->u.ata.command; 1202 return i; 1203 } 1204 1205 static void 1206 ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt) 1207 { 1208 struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev); 1209 1210 mtx_lock(&hpktp->mtx); 1211 if (hpktp->busy) { 1212 struct host_packet *hp = 1213 malloc(sizeof(struct host_packet), M_TEMP, M_NOWAIT | M_ZERO); 1214 hp->addr = hpkt; 1215 TAILQ_INSERT_TAIL(&hpktp->queue, hp, chain); 1216 } 1217 else { 1218 hpktp->busy = 1; 1219 ATA_OUTL(ctlr->r_res2, 0x000c0100, hpkt); 1220 } 1221 mtx_unlock(&hpktp->mtx); 1222 } 1223 1224 static void 1225 ata_promise_next_hpkt(struct ata_pci_controller *ctlr) 1226 { 1227 struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev); 1228 struct host_packet *hp; 1229 1230 mtx_lock(&hpktp->mtx); 1231 if ((hp = TAILQ_FIRST(&hpktp->queue))) { 1232 TAILQ_REMOVE(&hpktp->queue, hp, chain); 1233 ATA_OUTL(ctlr->r_res2, 0x000c0100, hp->addr); 1234 free(hp, M_TEMP); 1235 } 1236 else 1237 hpktp->busy = 0; 1238 mtx_unlock(&hpktp->mtx); 1239 } 1240 1241 ATA_DECLARE_DRIVER(ata_promise); 1242