1 /*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ata.h" 31 #include <sys/param.h> 32 #include <sys/module.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/ata.h> 36 #include <sys/bus.h> 37 #include <sys/endian.h> 38 #include <sys/malloc.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/sema.h> 42 #include <sys/taskqueue.h> 43 #include <vm/uma.h> 44 #include <machine/stdarg.h> 45 #include <machine/resource.h> 46 #include <machine/bus.h> 47 #include <sys/rman.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/ata/ata-all.h> 51 #include <dev/ata/ata-pci.h> 52 #include <ata_if.h> 53 54 /* local prototypes */ 55 static int ata_promise_chipinit(device_t dev); 56 static int ata_promise_ch_attach(device_t dev); 57 static int ata_promise_status(device_t dev); 58 static int ata_promise_dmastart(struct ata_request *request); 59 static int ata_promise_dmastop(struct ata_request *request); 60 static void ata_promise_dmareset(device_t dev); 61 static int ata_promise_setmode(device_t dev, int target, int mode); 62 static int ata_promise_tx2_ch_attach(device_t dev); 63 static int ata_promise_tx2_status(device_t dev); 64 static int ata_promise_mio_ch_attach(device_t dev); 65 static int ata_promise_mio_ch_detach(device_t dev); 66 static void ata_promise_mio_intr(void *data); 67 static int ata_promise_mio_status(device_t dev); 68 static int ata_promise_mio_command(struct ata_request *request); 69 static void ata_promise_mio_reset(device_t dev); 70 static int ata_promise_mio_pm_read(device_t dev, int port, int reg, u_int32_t *result); 71 static int ata_promise_mio_pm_write(device_t dev, int port, int reg, u_int32_t result); 72 static u_int32_t ata_promise_mio_softreset(device_t dev, int port); 73 static void ata_promise_mio_dmainit(device_t dev); 74 static void ata_promise_mio_setprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 75 static int ata_promise_mio_setmode(device_t dev, int target, int mode); 76 static int ata_promise_mio_getrev(device_t dev, int target); 77 static void ata_promise_sx4_intr(void *data); 78 static int ata_promise_sx4_command(struct ata_request *request); 79 static int ata_promise_apkt(u_int8_t *bytep, struct ata_request *request); 80 static void ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt); 81 static void ata_promise_next_hpkt(struct ata_pci_controller *ctlr); 82 83 /* misc defines */ 84 #define PR_OLD 0 85 #define PR_NEW 1 86 #define PR_TX 2 87 #define PR_MIO 3 88 #define PR_TX4 0x01 89 #define PR_SX4X 0x02 90 #define PR_SX6K 0x04 91 #define PR_PATA 0x08 92 #define PR_CMBO 0x10 93 #define PR_CMBO2 0x20 94 #define PR_SATA 0x40 95 #define PR_SATA2 0x80 96 97 98 /* 99 * Promise chipset support functions 100 */ 101 #define ATA_PDC_APKT_OFFSET 0x00000010 102 #define ATA_PDC_HPKT_OFFSET 0x00000040 103 #define ATA_PDC_ASG_OFFSET 0x00000080 104 #define ATA_PDC_LSG_OFFSET 0x000000c0 105 #define ATA_PDC_HSG_OFFSET 0x00000100 106 #define ATA_PDC_CHN_OFFSET 0x00000400 107 #define ATA_PDC_BUF_BASE 0x00400000 108 #define ATA_PDC_BUF_OFFSET 0x00100000 109 #define ATA_PDC_MAX_HPKT 8 110 #define ATA_PDC_WRITE_REG 0x00 111 #define ATA_PDC_WRITE_CTL 0x0e 112 #define ATA_PDC_WRITE_END 0x08 113 #define ATA_PDC_WAIT_NBUSY 0x10 114 #define ATA_PDC_WAIT_READY 0x18 115 #define ATA_PDC_1B 0x20 116 #define ATA_PDC_2B 0x40 117 118 struct host_packet { 119 u_int32_t addr; 120 TAILQ_ENTRY(host_packet) chain; 121 }; 122 123 struct ata_promise_sx4 { 124 struct mtx mtx; 125 TAILQ_HEAD(, host_packet) queue; 126 int busy; 127 }; 128 129 static int 130 ata_promise_probe(device_t dev) 131 { 132 struct ata_pci_controller *ctlr = device_get_softc(dev); 133 struct ata_chip_id *idx; 134 static struct ata_chip_id ids[] = 135 {{ ATA_PDC20246, 0, PR_OLD, 0x00, ATA_UDMA2, "PDC20246" }, 136 { ATA_PDC20262, 0, PR_NEW, 0x00, ATA_UDMA4, "PDC20262" }, 137 { ATA_PDC20263, 0, PR_NEW, 0x00, ATA_UDMA4, "PDC20263" }, 138 { ATA_PDC20265, 0, PR_NEW, 0x00, ATA_UDMA5, "PDC20265" }, 139 { ATA_PDC20267, 0, PR_NEW, 0x00, ATA_UDMA5, "PDC20267" }, 140 { ATA_PDC20268, 0, PR_TX, PR_TX4, ATA_UDMA5, "PDC20268" }, 141 { ATA_PDC20269, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20269" }, 142 { ATA_PDC20270, 0, PR_TX, PR_TX4, ATA_UDMA5, "PDC20270" }, 143 { ATA_PDC20271, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20271" }, 144 { ATA_PDC20275, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20275" }, 145 { ATA_PDC20276, 0, PR_TX, PR_SX6K, ATA_UDMA6, "PDC20276" }, 146 { ATA_PDC20277, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20277" }, 147 { ATA_PDC20318, 0, PR_MIO, PR_SATA, ATA_SA150, "PDC20318" }, 148 { ATA_PDC20319, 0, PR_MIO, PR_SATA, ATA_SA150, "PDC20319" }, 149 { ATA_PDC20371, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20371" }, 150 { ATA_PDC20375, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20375" }, 151 { ATA_PDC20376, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20376" }, 152 { ATA_PDC20377, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20377" }, 153 { ATA_PDC20378, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20378" }, 154 { ATA_PDC20379, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20379" }, 155 { ATA_PDC20571, 0, PR_MIO, PR_CMBO2, ATA_SA150, "PDC20571" }, 156 { ATA_PDC20575, 0, PR_MIO, PR_CMBO2, ATA_SA150, "PDC20575" }, 157 { ATA_PDC20579, 0, PR_MIO, PR_CMBO2, ATA_SA150, "PDC20579" }, 158 { ATA_PDC20771, 0, PR_MIO, PR_CMBO2, ATA_SA300, "PDC20771" }, 159 { ATA_PDC40775, 0, PR_MIO, PR_CMBO2, ATA_SA300, "PDC40775" }, 160 { ATA_PDC20617, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20617" }, 161 { ATA_PDC20618, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20618" }, 162 { ATA_PDC20619, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20619" }, 163 { ATA_PDC20620, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20620" }, 164 { ATA_PDC20621, 0, PR_MIO, PR_SX4X, ATA_UDMA5, "PDC20621" }, 165 { ATA_PDC20622, 0, PR_MIO, PR_SX4X, ATA_SA150, "PDC20622" }, 166 { ATA_PDC40518, 0, PR_MIO, PR_SATA2, ATA_SA150, "PDC40518" }, 167 { ATA_PDC40519, 0, PR_MIO, PR_SATA2, ATA_SA150, "PDC40519" }, 168 { ATA_PDC40718, 0, PR_MIO, PR_SATA2, ATA_SA300, "PDC40718" }, 169 { ATA_PDC40719, 0, PR_MIO, PR_SATA2, ATA_SA300, "PDC40719" }, 170 { ATA_PDC40779, 0, PR_MIO, PR_SATA2, ATA_SA300, "PDC40779" }, 171 { 0, 0, 0, 0, 0, 0}}; 172 char buffer[64]; 173 uintptr_t devid = 0; 174 175 if (pci_get_vendor(dev) != ATA_PROMISE_ID) 176 return ENXIO; 177 178 if (!(idx = ata_match_chip(dev, ids))) 179 return ENXIO; 180 181 /* if we are on a SuperTrak SX6000 dont attach */ 182 if ((idx->cfg2 & PR_SX6K) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE && 183 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), 184 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && 185 devid == ATA_I960RM) 186 return ENXIO; 187 188 strcpy(buffer, "Promise "); 189 strcat(buffer, idx->text); 190 191 /* if we are on a FastTrak TX4, adjust the interrupt resource */ 192 if ((idx->cfg2 & PR_TX4) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE && 193 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), 194 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && 195 ((devid == ATA_DEC_21150) || (devid == ATA_DEC_21150_1))) { 196 static long start = 0, end = 0; 197 198 if (pci_get_slot(dev) == 1) { 199 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end); 200 strcat(buffer, " (channel 0+1)"); 201 } 202 else if (pci_get_slot(dev) == 2 && start && end) { 203 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end); 204 strcat(buffer, " (channel 2+3)"); 205 } 206 else { 207 start = end = 0; 208 } 209 } 210 sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma)); 211 device_set_desc_copy(dev, buffer); 212 ctlr->chip = idx; 213 ctlr->chipinit = ata_promise_chipinit; 214 return (BUS_PROBE_DEFAULT); 215 } 216 217 static int 218 ata_promise_chipinit(device_t dev) 219 { 220 struct ata_pci_controller *ctlr = device_get_softc(dev); 221 int stat_reg; 222 223 if (ata_setup_interrupt(dev, ata_generic_intr)) 224 return ENXIO; 225 226 switch (ctlr->chip->cfg1) { 227 case PR_NEW: 228 /* setup clocks */ 229 ATA_OUTB(ctlr->r_res1, 0x11, ATA_INB(ctlr->r_res1, 0x11) | 0x0a); 230 /* FALLTHROUGH */ 231 232 case PR_OLD: 233 /* enable burst mode */ 234 ATA_OUTB(ctlr->r_res1, 0x1f, ATA_INB(ctlr->r_res1, 0x1f) | 0x01); 235 ctlr->ch_attach = ata_promise_ch_attach; 236 ctlr->ch_detach = ata_pci_ch_detach; 237 ctlr->setmode = ata_promise_setmode; 238 return 0; 239 240 case PR_TX: 241 ctlr->ch_attach = ata_promise_tx2_ch_attach; 242 ctlr->ch_detach = ata_pci_ch_detach; 243 ctlr->setmode = ata_promise_setmode; 244 return 0; 245 246 case PR_MIO: 247 ctlr->r_type1 = SYS_RES_MEMORY; 248 ctlr->r_rid1 = PCIR_BAR(4); 249 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 250 &ctlr->r_rid1, RF_ACTIVE))) 251 goto failnfree; 252 253 ctlr->r_type2 = SYS_RES_MEMORY; 254 ctlr->r_rid2 = PCIR_BAR(3); 255 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 256 &ctlr->r_rid2, RF_ACTIVE))) 257 goto failnfree; 258 259 if (ctlr->chip->cfg2 == PR_SX4X) { 260 struct ata_promise_sx4 *hpkt; 261 u_int32_t dimm = ATA_INL(ctlr->r_res2, 0x000c0080); 262 263 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) || 264 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, NULL, 265 ata_promise_sx4_intr, ctlr, &ctlr->handle)) { 266 device_printf(dev, "unable to setup interrupt\n"); 267 goto failnfree; 268 } 269 270 /* print info about cache memory */ 271 device_printf(dev, "DIMM size %dMB @ 0x%08x%s\n", 272 (((dimm >> 16) & 0xff)-((dimm >> 24) & 0xff)+1) << 4, 273 ((dimm >> 24) & 0xff), 274 ATA_INL(ctlr->r_res2, 0x000c0088) & (1<<16) ? 275 " ECC enabled" : "" ); 276 277 /* adjust cache memory parameters */ 278 ATA_OUTL(ctlr->r_res2, 0x000c000c, 279 (ATA_INL(ctlr->r_res2, 0x000c000c) & 0xffff0000)); 280 281 /* setup host packet controls */ 282 hpkt = malloc(sizeof(struct ata_promise_sx4), 283 M_TEMP, M_NOWAIT | M_ZERO); 284 mtx_init(&hpkt->mtx, "ATA promise HPKT lock", NULL, MTX_DEF); 285 TAILQ_INIT(&hpkt->queue); 286 hpkt->busy = 0; 287 ctlr->chipset_data = hpkt; 288 ctlr->ch_attach = ata_promise_mio_ch_attach; 289 ctlr->ch_detach = ata_promise_mio_ch_detach; 290 ctlr->reset = ata_promise_mio_reset; 291 ctlr->setmode = ata_promise_setmode; 292 ctlr->channels = 4; 293 return 0; 294 } 295 296 /* mio type controllers need an interrupt intercept */ 297 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) || 298 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, NULL, 299 ata_promise_mio_intr, ctlr, &ctlr->handle)) { 300 device_printf(dev, "unable to setup interrupt\n"); 301 goto failnfree; 302 } 303 304 switch (ctlr->chip->cfg2) { 305 case PR_PATA: 306 ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x01) > 0) + 307 ((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 2; 308 goto sata150; 309 case PR_CMBO: 310 ctlr->channels = 3; 311 goto sata150; 312 case PR_SATA: 313 ctlr->channels = 4; 314 sata150: 315 stat_reg = 0x6c; 316 break; 317 318 case PR_CMBO2: 319 ctlr->channels = 3; 320 goto sataii; 321 case PR_SATA2: 322 default: 323 ctlr->channels = 4; 324 sataii: 325 stat_reg = 0x60; 326 break; 327 } 328 329 /* prime fake interrupt register */ 330 ctlr->chipset_data = (void *)(uintptr_t)0xffffffff; 331 332 /* clear SATA status and unmask interrupts */ 333 ATA_OUTL(ctlr->r_res2, stat_reg, 0x000000ff); 334 335 /* enable "long burst length" on gen2 chips */ 336 if ((ctlr->chip->cfg2 == PR_SATA2) || (ctlr->chip->cfg2 == PR_CMBO2)) 337 ATA_OUTL(ctlr->r_res2, 0x44, ATA_INL(ctlr->r_res2, 0x44) | 0x2000); 338 339 ctlr->ch_attach = ata_promise_mio_ch_attach; 340 ctlr->ch_detach = ata_promise_mio_ch_detach; 341 ctlr->reset = ata_promise_mio_reset; 342 ctlr->setmode = ata_promise_mio_setmode; 343 ctlr->getrev = ata_promise_mio_getrev; 344 345 return 0; 346 } 347 348 failnfree: 349 if (ctlr->r_res2) 350 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2); 351 if (ctlr->r_res1) 352 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1, ctlr->r_res1); 353 return ENXIO; 354 } 355 356 static int 357 ata_promise_ch_attach(device_t dev) 358 { 359 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 360 struct ata_channel *ch = device_get_softc(dev); 361 362 if (ata_pci_ch_attach(dev)) 363 return ENXIO; 364 365 if (ctlr->chip->cfg1 == PR_NEW) { 366 ch->dma.start = ata_promise_dmastart; 367 ch->dma.stop = ata_promise_dmastop; 368 ch->dma.reset = ata_promise_dmareset; 369 } 370 371 ch->hw.status = ata_promise_status; 372 ch->flags |= ATA_NO_ATAPI_DMA; 373 ch->flags |= ATA_CHECKS_CABLE; 374 return 0; 375 } 376 377 static int 378 ata_promise_status(device_t dev) 379 { 380 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 381 struct ata_channel *ch = device_get_softc(dev); 382 383 if (ATA_INL(ctlr->r_res1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)) { 384 return ata_pci_status(dev); 385 } 386 return 0; 387 } 388 389 static int 390 ata_promise_dmastart(struct ata_request *request) 391 { 392 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 393 struct ata_channel *ch = device_get_softc(request->parent); 394 395 if (request->flags & ATA_R_48BIT) { 396 ATA_OUTB(ctlr->r_res1, 0x11, 397 ATA_INB(ctlr->r_res1, 0x11) | (ch->unit ? 0x08 : 0x02)); 398 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 399 ((request->flags & ATA_R_READ) ? 0x05000000 : 0x06000000) | 400 (request->bytecount >> 1)); 401 } 402 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) | 403 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 404 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, request->dma->sg_bus); 405 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 406 ((request->flags & ATA_R_READ) ? ATA_BMCMD_WRITE_READ : 0) | 407 ATA_BMCMD_START_STOP); 408 ch->dma.flags |= ATA_DMA_ACTIVE; 409 return 0; 410 } 411 412 static int 413 ata_promise_dmastop(struct ata_request *request) 414 { 415 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 416 struct ata_channel *ch = device_get_softc(request->parent); 417 int error; 418 419 if (request->flags & ATA_R_48BIT) { 420 ATA_OUTB(ctlr->r_res1, 0x11, 421 ATA_INB(ctlr->r_res1, 0x11) & ~(ch->unit ? 0x08 : 0x02)); 422 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 0); 423 } 424 error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT); 425 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 426 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 427 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 428 ch->dma.flags &= ~ATA_DMA_ACTIVE; 429 return error; 430 } 431 432 static void 433 ata_promise_dmareset(device_t dev) 434 { 435 struct ata_channel *ch = device_get_softc(dev); 436 437 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 438 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 439 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 440 ch->flags &= ~ATA_DMA_ACTIVE; 441 } 442 443 static int 444 ata_promise_setmode(device_t dev, int target, int mode) 445 { 446 device_t parent = device_get_parent(dev); 447 struct ata_pci_controller *ctlr = device_get_softc(parent); 448 struct ata_channel *ch = device_get_softc(dev); 449 int devno = (ch->unit << 1) + target; 450 u_int32_t timings[][2] = { 451 /* PR_OLD PR_NEW mode */ 452 { 0x004ff329, 0x004fff2f }, /* PIO 0 */ 453 { 0x004fec25, 0x004ff82a }, /* PIO 1 */ 454 { 0x004fe823, 0x004ff026 }, /* PIO 2 */ 455 { 0x004fe622, 0x004fec24 }, /* PIO 3 */ 456 { 0x004fe421, 0x004fe822 }, /* PIO 4 */ 457 { 0x004567f3, 0x004acef6 }, /* MWDMA 0 */ 458 { 0x004467f3, 0x0048cef6 }, /* MWDMA 1 */ 459 { 0x004367f3, 0x0046cef6 }, /* MWDMA 2 */ 460 { 0x004367f3, 0x0046cef6 }, /* UDMA 0 */ 461 { 0x004247f3, 0x00448ef6 }, /* UDMA 1 */ 462 { 0x004127f3, 0x00436ef6 }, /* UDMA 2 */ 463 { 0, 0x00424ef6 }, /* UDMA 3 */ 464 { 0, 0x004127f3 }, /* UDMA 4 */ 465 { 0, 0x004127f3 } /* UDMA 5 */ 466 }; 467 468 mode = min(mode, ctlr->chip->max_dma); 469 470 switch (ctlr->chip->cfg1) { 471 case PR_OLD: 472 case PR_NEW: 473 if (mode > ATA_UDMA2 && (pci_read_config(parent, 0x50, 2) & 474 (ch->unit ? 1 << 11 : 1 << 10))) { 475 ata_print_cable(dev, "controller"); 476 mode = ATA_UDMA2; 477 } 478 break; 479 480 case PR_TX: 481 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b); 482 if (mode > ATA_UDMA2 && 483 ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x04) { 484 ata_print_cable(dev, "controller"); 485 mode = ATA_UDMA2; 486 } 487 break; 488 489 case PR_MIO: 490 if (mode > ATA_UDMA2 && 491 (ATA_INL(ctlr->r_res2, 492 (ctlr->chip->cfg2 & PR_SX4X ? 0x000c0260 : 0x0260) + 493 (ch->unit << 7)) & 0x01000000)) { 494 ata_print_cable(dev, "controller"); 495 mode = ATA_UDMA2; 496 } 497 break; 498 } 499 500 if (ctlr->chip->cfg1 < PR_TX) 501 pci_write_config(parent, 0x60 + (devno << 2), 502 timings[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); 503 return (mode); 504 } 505 506 static int 507 ata_promise_tx2_ch_attach(device_t dev) 508 { 509 struct ata_channel *ch = device_get_softc(dev); 510 511 if (ata_pci_ch_attach(dev)) 512 return ENXIO; 513 514 ch->hw.status = ata_promise_tx2_status; 515 ch->flags |= ATA_CHECKS_CABLE; 516 return 0; 517 } 518 519 static int 520 ata_promise_tx2_status(device_t dev) 521 { 522 struct ata_channel *ch = device_get_softc(dev); 523 524 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b); 525 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) { 526 return ata_pci_status(dev); 527 } 528 return 0; 529 } 530 531 static int 532 ata_promise_mio_ch_attach(device_t dev) 533 { 534 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 535 struct ata_channel *ch = device_get_softc(dev); 536 int offset = (ctlr->chip->cfg2 & PR_SX4X) ? 0x000c0000 : 0; 537 int i; 538 539 ata_promise_mio_dmainit(dev); 540 541 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 542 ch->r_io[i].res = ctlr->r_res2; 543 ch->r_io[i].offset = offset + 0x0200 + (i << 2) + (ch->unit << 7); 544 } 545 ch->r_io[ATA_CONTROL].res = ctlr->r_res2; 546 ch->r_io[ATA_CONTROL].offset = offset + 0x0238 + (ch->unit << 7); 547 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 548 ata_default_registers(dev); 549 if ((ctlr->chip->cfg2 & (PR_SATA | PR_SATA2)) || 550 ((ctlr->chip->cfg2 & (PR_CMBO | PR_CMBO2)) && ch->unit < 2)) { 551 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 552 ch->r_io[ATA_SSTATUS].offset = 0x400 + (ch->unit << 8); 553 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 554 ch->r_io[ATA_SERROR].offset = 0x404 + (ch->unit << 8); 555 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 556 ch->r_io[ATA_SCONTROL].offset = 0x408 + (ch->unit << 8); 557 ch->flags |= ATA_NO_SLAVE; 558 ch->flags |= ATA_SATA; 559 } 560 ch->flags |= ATA_USE_16BIT; 561 ch->flags |= ATA_CHECKS_CABLE; 562 563 ata_generic_hw(dev); 564 if (ctlr->chip->cfg2 & PR_SX4X) { 565 ch->hw.command = ata_promise_sx4_command; 566 } 567 else { 568 ch->hw.command = ata_promise_mio_command; 569 ch->hw.status = ata_promise_mio_status; 570 ch->hw.softreset = ata_promise_mio_softreset; 571 ch->hw.pm_read = ata_promise_mio_pm_read; 572 ch->hw.pm_write = ata_promise_mio_pm_write; 573 } 574 return 0; 575 } 576 577 static int 578 ata_promise_mio_ch_detach(device_t dev) 579 { 580 581 ata_dmafini(dev); 582 return (0); 583 } 584 585 static void 586 ata_promise_mio_intr(void *data) 587 { 588 struct ata_pci_controller *ctlr = data; 589 struct ata_channel *ch; 590 u_int32_t vector; 591 int unit; 592 593 /* 594 * since reading interrupt status register on early "mio" chips 595 * clears the status bits we cannot read it for each channel later on 596 * in the generic interrupt routine. 597 */ 598 vector = ATA_INL(ctlr->r_res2, 0x040); 599 ATA_OUTL(ctlr->r_res2, 0x040, vector); 600 ctlr->chipset_data = (void *)(uintptr_t)vector; 601 602 for (unit = 0; unit < ctlr->channels; unit++) { 603 if ((ch = ctlr->interrupt[unit].argument)) 604 ctlr->interrupt[unit].function(ch); 605 } 606 607 ctlr->chipset_data = (void *)(uintptr_t)0xffffffff; 608 } 609 610 static int 611 ata_promise_mio_status(device_t dev) 612 { 613 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 614 struct ata_channel *ch = device_get_softc(dev); 615 u_int32_t stat_reg, vector, status; 616 617 switch (ctlr->chip->cfg2) { 618 case PR_PATA: 619 case PR_CMBO: 620 case PR_SATA: 621 stat_reg = 0x6c; 622 break; 623 case PR_CMBO2: 624 case PR_SATA2: 625 default: 626 stat_reg = 0x60; 627 break; 628 } 629 630 /* read and acknowledge interrupt */ 631 vector = (uint32_t)(uintptr_t)ctlr->chipset_data; 632 633 /* read and clear interface status */ 634 status = ATA_INL(ctlr->r_res2, stat_reg); 635 ATA_OUTL(ctlr->r_res2, stat_reg, status & (0x00000011 << ch->unit)); 636 637 /* check for and handle disconnect events */ 638 if (status & (0x00000001 << ch->unit)) { 639 if (bootverbose) 640 device_printf(dev, "DISCONNECT requested\n"); 641 taskqueue_enqueue(taskqueue_thread, &ch->conntask); 642 } 643 644 /* check for and handle connect events */ 645 if (status & (0x00000010 << ch->unit)) { 646 if (bootverbose) 647 device_printf(dev, "CONNECT requested\n"); 648 taskqueue_enqueue(taskqueue_thread, &ch->conntask); 649 } 650 651 /* do we have any device action ? */ 652 return (vector & (1 << (ch->unit + 1))); 653 } 654 655 static int 656 ata_promise_mio_command(struct ata_request *request) 657 { 658 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 659 struct ata_channel *ch = device_get_softc(request->parent); 660 661 u_int32_t *wordp = (u_int32_t *)ch->dma.work; 662 663 ATA_OUTL(ctlr->r_res2, (ch->unit + 1) << 2, 0x00000001); 664 665 if ((ctlr->chip->cfg2 == PR_SATA2) || 666 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) { 667 /* set portmultiplier port */ 668 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), request->unit & 0x0f); 669 } 670 671 /* XXX SOS add ATAPI commands support later */ 672 switch (request->u.ata.command) { 673 default: 674 return ata_generic_command(request); 675 676 case ATA_READ_DMA: 677 case ATA_READ_DMA48: 678 wordp[0] = htole32(0x04 | ((ch->unit + 1) << 16) | (0x00 << 24)); 679 break; 680 681 case ATA_WRITE_DMA: 682 case ATA_WRITE_DMA48: 683 wordp[0] = htole32(0x00 | ((ch->unit + 1) << 16) | (0x00 << 24)); 684 break; 685 } 686 wordp[1] = htole32(request->dma->sg_bus); 687 wordp[2] = 0; 688 ata_promise_apkt((u_int8_t*)wordp, request); 689 690 ATA_OUTL(ctlr->r_res2, 0x0240 + (ch->unit << 7), ch->dma.work_bus); 691 return 0; 692 } 693 694 static void 695 ata_promise_mio_reset(device_t dev) 696 { 697 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 698 struct ata_channel *ch = device_get_softc(dev); 699 struct ata_promise_sx4 *hpktp; 700 701 switch (ctlr->chip->cfg2) { 702 case PR_SX4X: 703 704 /* softreset channel ATA module */ 705 hpktp = ctlr->chipset_data; 706 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), ch->unit + 1); 707 ata_udelay(1000); 708 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), 709 (ATA_INL(ctlr->r_res2, 0xc0260 + (ch->unit << 7)) & 710 ~0x00003f9f) | (ch->unit + 1)); 711 712 /* softreset HOST module */ /* XXX SOS what about other outstandings */ 713 mtx_lock(&hpktp->mtx); 714 ATA_OUTL(ctlr->r_res2, 0xc012c, 715 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f) | (1 << 11)); 716 DELAY(10); 717 ATA_OUTL(ctlr->r_res2, 0xc012c, 718 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f)); 719 hpktp->busy = 0; 720 mtx_unlock(&hpktp->mtx); 721 ata_generic_reset(dev); 722 break; 723 724 case PR_PATA: 725 case PR_CMBO: 726 case PR_SATA: 727 if ((ctlr->chip->cfg2 == PR_SATA) || 728 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2))) { 729 730 /* mask plug/unplug intr */ 731 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00110000 << ch->unit)); 732 } 733 734 /* softreset channels ATA module */ 735 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11)); 736 ata_udelay(10000); 737 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), 738 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) & 739 ~0x00003f9f) | (ch->unit + 1)); 740 741 if ((ctlr->chip->cfg2 == PR_SATA) || 742 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2))) { 743 744 if (ata_sata_phy_reset(dev, -1, 1)) 745 ata_generic_reset(dev); 746 747 /* reset and enable plug/unplug intr */ 748 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00000011 << ch->unit)); 749 } 750 else 751 ata_generic_reset(dev); 752 break; 753 754 case PR_CMBO2: 755 case PR_SATA2: 756 if ((ctlr->chip->cfg2 == PR_SATA2) || 757 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) { 758 /* set portmultiplier port */ 759 //ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f); 760 761 /* mask plug/unplug intr */ 762 ATA_OUTL(ctlr->r_res2, 0x060, (0x00110000 << ch->unit)); 763 } 764 765 /* softreset channels ATA module */ 766 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11)); 767 ata_udelay(10000); 768 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), 769 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) & 770 ~0x00003f9f) | (ch->unit + 1)); 771 772 if ((ctlr->chip->cfg2 == PR_SATA2) || 773 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) { 774 775 /* set PHY mode to "improved" */ 776 ATA_OUTL(ctlr->r_res2, 0x414 + (ch->unit << 8), 777 (ATA_INL(ctlr->r_res2, 0x414 + (ch->unit << 8)) & 778 ~0x00000003) | 0x00000001); 779 780 if (ata_sata_phy_reset(dev, -1, 1)) { 781 u_int32_t signature = ch->hw.softreset(dev, ATA_PM); 782 783 if (1 | bootverbose) 784 device_printf(dev, "SIGNATURE: %08x\n", signature); 785 786 switch (signature >> 16) { 787 case 0x0000: 788 ch->devices = ATA_ATA_MASTER; 789 break; 790 case 0x9669: 791 ch->devices = ATA_PORTMULTIPLIER; 792 ata_pm_identify(dev); 793 break; 794 case 0xeb14: 795 ch->devices = ATA_ATAPI_MASTER; 796 break; 797 default: /* SOS XXX */ 798 if (bootverbose) 799 device_printf(dev, 800 "No signature, assuming disk device\n"); 801 ch->devices = ATA_ATA_MASTER; 802 } 803 if (bootverbose) 804 device_printf(dev, "promise_mio_reset devices=%08x\n", 805 ch->devices); 806 807 } else 808 ch->devices = 0; 809 810 /* reset and enable plug/unplug intr */ 811 ATA_OUTL(ctlr->r_res2, 0x060, (0x00000011 << ch->unit)); 812 813 ///* set portmultiplier port */ 814 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x00); 815 } 816 else 817 ata_generic_reset(dev); 818 break; 819 820 } 821 } 822 823 static int 824 ata_promise_mio_pm_read(device_t dev, int port, int reg, u_int32_t *result) 825 { 826 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 827 struct ata_channel *ch = device_get_softc(dev); 828 int timeout = 0; 829 830 /* set portmultiplier port */ 831 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f); 832 833 ATA_IDX_OUTB(ch, ATA_FEATURE, reg); 834 ATA_IDX_OUTB(ch, ATA_DRIVE, port); 835 836 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_READ_PM); 837 838 while (timeout < 1000000) { 839 u_int8_t status = ATA_IDX_INB(ch, ATA_STATUS); 840 if (!(status & ATA_S_BUSY)) 841 break; 842 timeout += 1000; 843 DELAY(1000); 844 } 845 if (timeout >= 1000000) 846 return ATA_E_ABORT; 847 848 *result = ATA_IDX_INB(ch, ATA_COUNT) | 849 (ATA_IDX_INB(ch, ATA_SECTOR) << 8) | 850 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 16) | 851 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 24); 852 return 0; 853 } 854 855 static int 856 ata_promise_mio_pm_write(device_t dev, int port, int reg, u_int32_t value) 857 { 858 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 859 struct ata_channel *ch = device_get_softc(dev); 860 int timeout = 0; 861 862 /* set portmultiplier port */ 863 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f); 864 865 ATA_IDX_OUTB(ch, ATA_FEATURE, reg); 866 ATA_IDX_OUTB(ch, ATA_DRIVE, port); 867 ATA_IDX_OUTB(ch, ATA_COUNT, value & 0xff); 868 ATA_IDX_OUTB(ch, ATA_SECTOR, (value >> 8) & 0xff); 869 ATA_IDX_OUTB(ch, ATA_CYL_LSB, (value >> 16) & 0xff); 870 ATA_IDX_OUTB(ch, ATA_CYL_MSB, (value >> 24) & 0xff); 871 872 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_WRITE_PM); 873 874 while (timeout < 1000000) { 875 u_int8_t status = ATA_IDX_INB(ch, ATA_STATUS); 876 if (!(status & ATA_S_BUSY)) 877 break; 878 timeout += 1000; 879 DELAY(1000); 880 } 881 if (timeout >= 1000000) 882 return ATA_E_ABORT; 883 884 return ATA_IDX_INB(ch, ATA_ERROR); 885 } 886 887 /* must be called with ATA channel locked and state_mtx held */ 888 static u_int32_t 889 ata_promise_mio_softreset(device_t dev, int port) 890 { 891 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 892 struct ata_channel *ch = device_get_softc(dev); 893 int timeout; 894 895 /* set portmultiplier port */ 896 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), port & 0x0f); 897 898 /* softreset device on this channel */ 899 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_MASTER)); 900 DELAY(10); 901 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS | ATA_A_RESET); 902 ata_udelay(10000); 903 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS); 904 ata_udelay(150000); 905 ATA_IDX_INB(ch, ATA_ERROR); 906 907 /* wait for BUSY to go inactive */ 908 for (timeout = 0; timeout < 100; timeout++) { 909 u_int8_t err, stat; 910 911 err = ATA_IDX_INB(ch, ATA_ERROR); 912 stat = ATA_IDX_INB(ch, ATA_STATUS); 913 914 //if (stat == err && timeout > (stat & ATA_S_BUSY ? 100 : 10)) 915 //break; 916 917 if (!(stat & ATA_S_BUSY)) { 918 //if ((err & 0x7f) == ATA_E_ILI) { 919 return ATA_IDX_INB(ch, ATA_COUNT) | 920 (ATA_IDX_INB(ch, ATA_SECTOR) << 8) | 921 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 16) | 922 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 24); 923 //} 924 //else if (stat & 0x0f) { 925 //stat |= ATA_S_BUSY; 926 //} 927 } 928 929 if (!(stat & ATA_S_BUSY) || (stat == 0xff && timeout > 10)) 930 break; 931 ata_udelay(100000); 932 } 933 return -1; 934 } 935 936 static void 937 ata_promise_mio_dmainit(device_t dev) 938 { 939 struct ata_channel *ch = device_get_softc(dev); 940 941 ata_dmainit(dev); 942 /* note start and stop are not used here */ 943 ch->dma.setprd = ata_promise_mio_setprd; 944 ch->dma.max_iosize = 65536; 945 } 946 947 948 #define MAXLASTSGSIZE (32 * sizeof(u_int32_t)) 949 static void 950 ata_promise_mio_setprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 951 { 952 struct ata_dmasetprd_args *args = xsc; 953 struct ata_dma_prdentry *prd = args->dmatab; 954 int i; 955 956 if ((args->error = error)) 957 return; 958 959 for (i = 0; i < nsegs; i++) { 960 prd[i].addr = htole32(segs[i].ds_addr); 961 prd[i].count = htole32(segs[i].ds_len); 962 } 963 if (segs[i - 1].ds_len > MAXLASTSGSIZE) { 964 //printf("split last SG element of %u\n", segs[i - 1].ds_len); 965 prd[i - 1].count = htole32(segs[i - 1].ds_len - MAXLASTSGSIZE); 966 prd[i].count = htole32(MAXLASTSGSIZE); 967 prd[i].addr = htole32(segs[i - 1].ds_addr + 968 (segs[i - 1].ds_len - MAXLASTSGSIZE)); 969 nsegs++; 970 i++; 971 } 972 prd[i - 1].count |= htole32(ATA_DMA_EOT); 973 KASSERT(nsegs <= ATA_DMA_ENTRIES, ("too many DMA segment entries\n")); 974 args->nsegs = nsegs; 975 } 976 977 static int 978 ata_promise_mio_setmode(device_t dev, int target, int mode) 979 { 980 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 981 struct ata_channel *ch = device_get_softc(dev); 982 983 if ( (ctlr->chip->cfg2 == PR_SATA) || 984 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2)) || 985 (ctlr->chip->cfg2 == PR_SATA2) || 986 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) 987 mode = ata_sata_setmode(dev, target, mode); 988 else 989 mode = ata_promise_setmode(dev, target, mode); 990 return (mode); 991 } 992 993 static int 994 ata_promise_mio_getrev(device_t dev, int target) 995 { 996 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 997 struct ata_channel *ch = device_get_softc(dev); 998 999 if ( (ctlr->chip->cfg2 == PR_SATA) || 1000 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2)) || 1001 (ctlr->chip->cfg2 == PR_SATA2) || 1002 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) 1003 return (ata_sata_getrev(dev, target)); 1004 else 1005 return (0); 1006 } 1007 1008 static void 1009 ata_promise_sx4_intr(void *data) 1010 { 1011 struct ata_pci_controller *ctlr = data; 1012 struct ata_channel *ch; 1013 u_int32_t vector = ATA_INL(ctlr->r_res2, 0x000c0480); 1014 int unit; 1015 1016 for (unit = 0; unit < ctlr->channels; unit++) { 1017 if (vector & (1 << (unit + 1))) 1018 if ((ch = ctlr->interrupt[unit].argument)) 1019 ctlr->interrupt[unit].function(ch); 1020 if (vector & (1 << (unit + 5))) 1021 if ((ch = ctlr->interrupt[unit].argument)) 1022 ata_promise_queue_hpkt(ctlr, 1023 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + 1024 ATA_PDC_HPKT_OFFSET)); 1025 if (vector & (1 << (unit + 9))) { 1026 ata_promise_next_hpkt(ctlr); 1027 if ((ch = ctlr->interrupt[unit].argument)) 1028 ctlr->interrupt[unit].function(ch); 1029 } 1030 if (vector & (1 << (unit + 13))) { 1031 ata_promise_next_hpkt(ctlr); 1032 if ((ch = ctlr->interrupt[unit].argument)) 1033 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 1034 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + 1035 ATA_PDC_APKT_OFFSET)); 1036 } 1037 } 1038 } 1039 1040 static int 1041 ata_promise_sx4_command(struct ata_request *request) 1042 { 1043 device_t gparent = device_get_parent(request->parent); 1044 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1045 struct ata_channel *ch = device_get_softc(request->parent); 1046 struct ata_dma_prdentry *prd; 1047 caddr_t window = rman_get_virtual(ctlr->r_res1); 1048 u_int32_t *wordp; 1049 int i, idx, length = 0; 1050 1051 /* XXX SOS add ATAPI commands support later */ 1052 switch (request->u.ata.command) { 1053 1054 default: 1055 return -1; 1056 1057 case ATA_ATA_IDENTIFY: 1058 case ATA_READ: 1059 case ATA_READ48: 1060 case ATA_READ_MUL: 1061 case ATA_READ_MUL48: 1062 case ATA_WRITE: 1063 case ATA_WRITE48: 1064 case ATA_WRITE_MUL: 1065 case ATA_WRITE_MUL48: 1066 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001); 1067 return ata_generic_command(request); 1068 1069 case ATA_SETFEATURES: 1070 case ATA_FLUSHCACHE: 1071 case ATA_FLUSHCACHE48: 1072 case ATA_SLEEP: 1073 case ATA_SET_MULTI: 1074 wordp = (u_int32_t *) 1075 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET); 1076 wordp[0] = htole32(0x08 | ((ch->unit + 1)<<16) | (0x00 << 24)); 1077 wordp[1] = 0; 1078 wordp[2] = 0; 1079 ata_promise_apkt((u_int8_t *)wordp, request); 1080 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001); 1081 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001); 1082 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 1083 htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_APKT_OFFSET)); 1084 return 0; 1085 1086 case ATA_READ_DMA: 1087 case ATA_READ_DMA48: 1088 case ATA_WRITE_DMA: 1089 case ATA_WRITE_DMA48: 1090 prd = request->dma->sg; 1091 wordp = (u_int32_t *) 1092 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HSG_OFFSET); 1093 i = idx = 0; 1094 do { 1095 wordp[idx++] = prd[i].addr; 1096 wordp[idx++] = prd[i].count; 1097 length += (prd[i].count & ~ATA_DMA_EOT); 1098 } while (!(prd[i++].count & ATA_DMA_EOT)); 1099 1100 wordp = (u_int32_t *) 1101 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_LSG_OFFSET); 1102 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE); 1103 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT); 1104 1105 wordp = (u_int32_t *) 1106 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_ASG_OFFSET); 1107 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE); 1108 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT); 1109 1110 wordp = (u_int32_t *) 1111 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET); 1112 if (request->flags & ATA_R_READ) 1113 wordp[0] = htole32(0x14 | ((ch->unit+9)<<16) | ((ch->unit+5)<<24)); 1114 if (request->flags & ATA_R_WRITE) 1115 wordp[0] = htole32(0x00 | ((ch->unit+13)<<16) | (0x00<<24)); 1116 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_HSG_OFFSET); 1117 wordp[2] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_LSG_OFFSET); 1118 wordp[3] = 0; 1119 1120 wordp = (u_int32_t *) 1121 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET); 1122 if (request->flags & ATA_R_READ) 1123 wordp[0] = htole32(0x04 | ((ch->unit+5)<<16) | (0x00<<24)); 1124 if (request->flags & ATA_R_WRITE) 1125 wordp[0] = htole32(0x10 | ((ch->unit+1)<<16) | ((ch->unit+13)<<24)); 1126 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_ASG_OFFSET); 1127 wordp[2] = 0; 1128 ata_promise_apkt((u_int8_t *)wordp, request); 1129 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001); 1130 1131 if (request->flags & ATA_R_READ) { 1132 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+5)<<2), 0x00000001); 1133 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+9)<<2), 0x00000001); 1134 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 1135 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET)); 1136 } 1137 if (request->flags & ATA_R_WRITE) { 1138 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+1)<<2), 0x00000001); 1139 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+13)<<2), 0x00000001); 1140 ata_promise_queue_hpkt(ctlr, 1141 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET)); 1142 } 1143 return 0; 1144 } 1145 } 1146 1147 static int 1148 ata_promise_apkt(u_int8_t *bytep, struct ata_request *request) 1149 { 1150 int i = 12; 1151 1152 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_PDC_WAIT_NBUSY|ATA_DRIVE; 1153 bytep[i++] = ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit); 1154 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_CTL; 1155 bytep[i++] = ATA_A_4BIT; 1156 1157 if (request->flags & ATA_R_48BIT) { 1158 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_FEATURE; 1159 bytep[i++] = request->u.ata.feature >> 8; 1160 bytep[i++] = request->u.ata.feature; 1161 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_COUNT; 1162 bytep[i++] = request->u.ata.count >> 8; 1163 bytep[i++] = request->u.ata.count; 1164 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_SECTOR; 1165 bytep[i++] = request->u.ata.lba >> 24; 1166 bytep[i++] = request->u.ata.lba; 1167 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_LSB; 1168 bytep[i++] = request->u.ata.lba >> 32; 1169 bytep[i++] = request->u.ata.lba >> 8; 1170 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_MSB; 1171 bytep[i++] = request->u.ata.lba >> 40; 1172 bytep[i++] = request->u.ata.lba >> 16; 1173 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE; 1174 bytep[i++] = ATA_D_LBA | ATA_DEV(request->unit); 1175 } 1176 else { 1177 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_FEATURE; 1178 bytep[i++] = request->u.ata.feature; 1179 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_COUNT; 1180 bytep[i++] = request->u.ata.count; 1181 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_SECTOR; 1182 bytep[i++] = request->u.ata.lba; 1183 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_LSB; 1184 bytep[i++] = request->u.ata.lba >> 8; 1185 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_MSB; 1186 bytep[i++] = request->u.ata.lba >> 16; 1187 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE; 1188 bytep[i++] = ATA_D_LBA | ATA_D_IBM | ATA_DEV(request->unit) | 1189 ((request->u.ata.lba >> 24)&0xf); 1190 } 1191 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_END | ATA_COMMAND; 1192 bytep[i++] = request->u.ata.command; 1193 return i; 1194 } 1195 1196 static void 1197 ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt) 1198 { 1199 struct ata_promise_sx4 *hpktp = ctlr->chipset_data; 1200 1201 mtx_lock(&hpktp->mtx); 1202 if (hpktp->busy) { 1203 struct host_packet *hp = 1204 malloc(sizeof(struct host_packet), M_TEMP, M_NOWAIT | M_ZERO); 1205 hp->addr = hpkt; 1206 TAILQ_INSERT_TAIL(&hpktp->queue, hp, chain); 1207 } 1208 else { 1209 hpktp->busy = 1; 1210 ATA_OUTL(ctlr->r_res2, 0x000c0100, hpkt); 1211 } 1212 mtx_unlock(&hpktp->mtx); 1213 } 1214 1215 static void 1216 ata_promise_next_hpkt(struct ata_pci_controller *ctlr) 1217 { 1218 struct ata_promise_sx4 *hpktp = ctlr->chipset_data; 1219 struct host_packet *hp; 1220 1221 mtx_lock(&hpktp->mtx); 1222 if ((hp = TAILQ_FIRST(&hpktp->queue))) { 1223 TAILQ_REMOVE(&hpktp->queue, hp, chain); 1224 ATA_OUTL(ctlr->r_res2, 0x000c0100, hp->addr); 1225 free(hp, M_TEMP); 1226 } 1227 else 1228 hpktp->busy = 0; 1229 mtx_unlock(&hpktp->mtx); 1230 } 1231 1232 ATA_DECLARE_DRIVER(ata_promise); 1233