1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification, immediately at the beginning of the file. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 #include <sys/param.h> 31 #include <sys/module.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/ata.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/malloc.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 #include <sys/sema.h> 41 #include <sys/taskqueue.h> 42 #include <vm/uma.h> 43 #include <machine/stdarg.h> 44 #include <machine/resource.h> 45 #include <machine/bus.h> 46 #include <sys/rman.h> 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcireg.h> 49 #include <dev/ata/ata-all.h> 50 #include <dev/ata/ata-pci.h> 51 #include <ata_if.h> 52 53 /* local prototypes */ 54 static int ata_promise_chipinit(device_t dev); 55 static int ata_promise_ch_attach(device_t dev); 56 static int ata_promise_status(device_t dev); 57 static int ata_promise_dmastart(struct ata_request *request); 58 static int ata_promise_dmastop(struct ata_request *request); 59 static void ata_promise_dmareset(device_t dev); 60 static int ata_promise_setmode(device_t dev, int target, int mode); 61 static int ata_promise_tx2_ch_attach(device_t dev); 62 static int ata_promise_tx2_status(device_t dev); 63 static int ata_promise_mio_ch_attach(device_t dev); 64 static int ata_promise_mio_ch_detach(device_t dev); 65 static void ata_promise_mio_intr(void *data); 66 static int ata_promise_mio_status(device_t dev); 67 static int ata_promise_mio_command(struct ata_request *request); 68 static void ata_promise_mio_reset(device_t dev); 69 static int ata_promise_mio_pm_read(device_t dev, int port, int reg, u_int32_t *result); 70 static int ata_promise_mio_pm_write(device_t dev, int port, int reg, u_int32_t result); 71 static u_int32_t ata_promise_mio_softreset(device_t dev, int port); 72 static void ata_promise_mio_dmainit(device_t dev); 73 static void ata_promise_mio_setprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 74 static int ata_promise_mio_setmode(device_t dev, int target, int mode); 75 static int ata_promise_mio_getrev(device_t dev, int target); 76 static void ata_promise_sx4_intr(void *data); 77 static int ata_promise_sx4_command(struct ata_request *request); 78 static int ata_promise_apkt(u_int8_t *bytep, struct ata_request *request); 79 static void ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt); 80 static void ata_promise_next_hpkt(struct ata_pci_controller *ctlr); 81 82 /* misc defines */ 83 #define PR_OLD 0 84 #define PR_NEW 1 85 #define PR_TX 2 86 #define PR_MIO 3 87 #define PR_TX4 0x01 88 #define PR_SX4X 0x02 89 #define PR_SX6K 0x04 90 #define PR_PATA 0x08 91 #define PR_CMBO 0x10 92 #define PR_CMBO2 0x20 93 #define PR_SATA 0x40 94 #define PR_SATA2 0x80 95 96 /* 97 * Promise chipset support functions 98 */ 99 #define ATA_PDC_APKT_OFFSET 0x00000010 100 #define ATA_PDC_HPKT_OFFSET 0x00000040 101 #define ATA_PDC_ASG_OFFSET 0x00000080 102 #define ATA_PDC_LSG_OFFSET 0x000000c0 103 #define ATA_PDC_HSG_OFFSET 0x00000100 104 #define ATA_PDC_CHN_OFFSET 0x00000400 105 #define ATA_PDC_BUF_BASE 0x00400000 106 #define ATA_PDC_BUF_OFFSET 0x00100000 107 #define ATA_PDC_MAX_HPKT 8 108 #define ATA_PDC_WRITE_REG 0x00 109 #define ATA_PDC_WRITE_CTL 0x0e 110 #define ATA_PDC_WRITE_END 0x08 111 #define ATA_PDC_WAIT_NBUSY 0x10 112 #define ATA_PDC_WAIT_READY 0x18 113 #define ATA_PDC_1B 0x20 114 #define ATA_PDC_2B 0x40 115 116 struct host_packet { 117 u_int32_t addr; 118 TAILQ_ENTRY(host_packet) chain; 119 }; 120 121 struct ata_promise_sx4 { 122 struct mtx mtx; 123 TAILQ_HEAD(, host_packet) queue; 124 int busy; 125 }; 126 127 static int 128 ata_promise_probe(device_t dev) 129 { 130 struct ata_pci_controller *ctlr = device_get_softc(dev); 131 const struct ata_chip_id *idx; 132 static const struct ata_chip_id ids[] = 133 {{ ATA_PDC20246, 0, PR_OLD, 0x00, ATA_UDMA2, "PDC20246" }, 134 { ATA_PDC20262, 0, PR_NEW, 0x00, ATA_UDMA4, "PDC20262" }, 135 { ATA_PDC20263, 0, PR_NEW, 0x00, ATA_UDMA4, "PDC20263" }, 136 { ATA_PDC20265, 0, PR_NEW, 0x00, ATA_UDMA5, "PDC20265" }, 137 { ATA_PDC20267, 0, PR_NEW, 0x00, ATA_UDMA5, "PDC20267" }, 138 { ATA_PDC20268, 0, PR_TX, PR_TX4, ATA_UDMA5, "PDC20268" }, 139 { ATA_PDC20269, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20269" }, 140 { ATA_PDC20270, 0, PR_TX, PR_TX4, ATA_UDMA5, "PDC20270" }, 141 { ATA_PDC20271, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20271" }, 142 { ATA_PDC20275, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20275" }, 143 { ATA_PDC20276, 0, PR_TX, PR_SX6K, ATA_UDMA6, "PDC20276" }, 144 { ATA_PDC20277, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20277" }, 145 { ATA_PDC20318, 0, PR_MIO, PR_SATA, ATA_SA150, "PDC20318" }, 146 { ATA_PDC20319, 0, PR_MIO, PR_SATA, ATA_SA150, "PDC20319" }, 147 { ATA_PDC20371, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20371" }, 148 { ATA_PDC20375, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20375" }, 149 { ATA_PDC20376, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20376" }, 150 { ATA_PDC20377, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20377" }, 151 { ATA_PDC20378, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20378" }, 152 { ATA_PDC20379, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20379" }, 153 { ATA_PDC20571, 0, PR_MIO, PR_CMBO2, ATA_SA150, "PDC20571" }, 154 { ATA_PDC20575, 0, PR_MIO, PR_CMBO2, ATA_SA150, "PDC20575" }, 155 { ATA_PDC20579, 0, PR_MIO, PR_CMBO2, ATA_SA150, "PDC20579" }, 156 { ATA_PDC20771, 0, PR_MIO, PR_CMBO2, ATA_SA300, "PDC20771" }, 157 { ATA_PDC40775, 0, PR_MIO, PR_CMBO2, ATA_SA300, "PDC40775" }, 158 { ATA_PDC20617, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20617" }, 159 { ATA_PDC20618, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20618" }, 160 { ATA_PDC20619, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20619" }, 161 { ATA_PDC20620, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20620" }, 162 { ATA_PDC20621, 0, PR_MIO, PR_SX4X, ATA_UDMA5, "PDC20621" }, 163 { ATA_PDC20622, 0, PR_MIO, PR_SX4X, ATA_SA150, "PDC20622" }, 164 { ATA_PDC40518, 0, PR_MIO, PR_SATA2, ATA_SA150, "PDC40518" }, 165 { ATA_PDC40519, 0, PR_MIO, PR_SATA2, ATA_SA150, "PDC40519" }, 166 { ATA_PDC40718, 0, PR_MIO, PR_SATA2, ATA_SA300, "PDC40718" }, 167 { ATA_PDC40719, 0, PR_MIO, PR_SATA2, ATA_SA300, "PDC40719" }, 168 { ATA_PDC40779, 0, PR_MIO, PR_SATA2, ATA_SA300, "PDC40779" }, 169 { 0, 0, 0, 0, 0, 0}}; 170 char buffer[64]; 171 uintptr_t devid = 0; 172 173 if (pci_get_vendor(dev) != ATA_PROMISE_ID) 174 return ENXIO; 175 176 if (!(idx = ata_match_chip(dev, ids))) 177 return ENXIO; 178 179 /* if we are on a SuperTrak SX6000 dont attach */ 180 if ((idx->cfg2 & PR_SX6K) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE && 181 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), 182 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && 183 devid == ATA_I960RM) 184 return ENXIO; 185 186 strcpy(buffer, "Promise "); 187 strcat(buffer, idx->text); 188 189 /* if we are on a FastTrak TX4, adjust the interrupt resource */ 190 if ((idx->cfg2 & PR_TX4) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE && 191 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), 192 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && 193 ((devid == ATA_DEC_21150) || (devid == ATA_DEC_21150_1))) { 194 static rman_res_t start = 0, end = 0; 195 196 if (pci_get_slot(dev) == 1) { 197 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end); 198 strcat(buffer, " (channel 0+1)"); 199 } 200 else if (pci_get_slot(dev) == 2 && start && end) { 201 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end); 202 strcat(buffer, " (channel 2+3)"); 203 } 204 else { 205 start = end = 0; 206 } 207 } 208 sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma)); 209 device_set_desc_copy(dev, buffer); 210 ctlr->chip = idx; 211 ctlr->chipinit = ata_promise_chipinit; 212 return (BUS_PROBE_LOW_PRIORITY); 213 } 214 215 static int 216 ata_promise_chipinit(device_t dev) 217 { 218 struct ata_pci_controller *ctlr = device_get_softc(dev); 219 int stat_reg; 220 221 if (ata_setup_interrupt(dev, ata_generic_intr)) 222 return ENXIO; 223 224 switch (ctlr->chip->cfg1) { 225 case PR_NEW: 226 /* setup clocks */ 227 ATA_OUTB(ctlr->r_res1, 0x11, ATA_INB(ctlr->r_res1, 0x11) | 0x0a); 228 /* FALLTHROUGH */ 229 230 case PR_OLD: 231 /* enable burst mode */ 232 ATA_OUTB(ctlr->r_res1, 0x1f, ATA_INB(ctlr->r_res1, 0x1f) | 0x01); 233 ctlr->ch_attach = ata_promise_ch_attach; 234 ctlr->ch_detach = ata_pci_ch_detach; 235 ctlr->setmode = ata_promise_setmode; 236 return 0; 237 238 case PR_TX: 239 ctlr->ch_attach = ata_promise_tx2_ch_attach; 240 ctlr->ch_detach = ata_pci_ch_detach; 241 ctlr->setmode = ata_promise_setmode; 242 return 0; 243 244 case PR_MIO: 245 ctlr->r_type1 = SYS_RES_MEMORY; 246 ctlr->r_rid1 = PCIR_BAR(4); 247 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 248 &ctlr->r_rid1, RF_ACTIVE))) 249 goto failnfree; 250 251 ctlr->r_type2 = SYS_RES_MEMORY; 252 ctlr->r_rid2 = PCIR_BAR(3); 253 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 254 &ctlr->r_rid2, RF_ACTIVE))) 255 goto failnfree; 256 257 if (ctlr->chip->cfg2 == PR_SX4X) { 258 struct ata_promise_sx4 *hpkt; 259 u_int32_t dimm = ATA_INL(ctlr->r_res2, 0x000c0080); 260 261 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) || 262 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, NULL, 263 ata_promise_sx4_intr, ctlr, &ctlr->handle)) { 264 device_printf(dev, "unable to setup interrupt\n"); 265 goto failnfree; 266 } 267 268 /* print info about cache memory */ 269 device_printf(dev, "DIMM size %dMB @ 0x%08x%s\n", 270 (((dimm >> 16) & 0xff)-((dimm >> 24) & 0xff)+1) << 4, 271 ((dimm >> 24) & 0xff), 272 ATA_INL(ctlr->r_res2, 0x000c0088) & (1<<16) ? 273 " ECC enabled" : "" ); 274 275 /* adjust cache memory parameters */ 276 ATA_OUTL(ctlr->r_res2, 0x000c000c, 277 (ATA_INL(ctlr->r_res2, 0x000c000c) & 0xffff0000)); 278 279 /* setup host packet controls */ 280 hpkt = malloc(sizeof(struct ata_promise_sx4), 281 M_ATAPCI, M_NOWAIT | M_ZERO); 282 if (hpkt == NULL) { 283 device_printf(dev, "Cannot allocate HPKT\n"); 284 goto failnfree; 285 } 286 mtx_init(&hpkt->mtx, "ATA promise HPKT lock", NULL, MTX_DEF); 287 TAILQ_INIT(&hpkt->queue); 288 hpkt->busy = 0; 289 ctlr->chipset_data = hpkt; 290 ctlr->ch_attach = ata_promise_mio_ch_attach; 291 ctlr->ch_detach = ata_promise_mio_ch_detach; 292 ctlr->reset = ata_promise_mio_reset; 293 ctlr->setmode = ata_promise_setmode; 294 ctlr->channels = 4; 295 return 0; 296 } 297 298 /* mio type controllers need an interrupt intercept */ 299 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) || 300 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, NULL, 301 ata_promise_mio_intr, ctlr, &ctlr->handle)) { 302 device_printf(dev, "unable to setup interrupt\n"); 303 goto failnfree; 304 } 305 306 switch (ctlr->chip->cfg2) { 307 case PR_PATA: 308 ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x01) > 0) + 309 ((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 2; 310 goto sata150; 311 case PR_CMBO: 312 ctlr->channels = 3; 313 goto sata150; 314 case PR_SATA: 315 ctlr->channels = 4; 316 sata150: 317 stat_reg = 0x6c; 318 break; 319 320 case PR_CMBO2: 321 ctlr->channels = 3; 322 goto sataii; 323 case PR_SATA2: 324 default: 325 ctlr->channels = 4; 326 sataii: 327 stat_reg = 0x60; 328 break; 329 } 330 331 /* prime fake interrupt register */ 332 ctlr->chipset_data = (void *)(uintptr_t)0xffffffff; 333 334 /* clear SATA status and unmask interrupts */ 335 ATA_OUTL(ctlr->r_res2, stat_reg, 0x000000ff); 336 337 /* enable "long burst length" on gen2 chips */ 338 if ((ctlr->chip->cfg2 == PR_SATA2) || (ctlr->chip->cfg2 == PR_CMBO2)) 339 ATA_OUTL(ctlr->r_res2, 0x44, ATA_INL(ctlr->r_res2, 0x44) | 0x2000); 340 341 ctlr->ch_attach = ata_promise_mio_ch_attach; 342 ctlr->ch_detach = ata_promise_mio_ch_detach; 343 ctlr->reset = ata_promise_mio_reset; 344 ctlr->setmode = ata_promise_mio_setmode; 345 ctlr->getrev = ata_promise_mio_getrev; 346 347 return 0; 348 } 349 350 failnfree: 351 if (ctlr->r_res2) 352 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2); 353 if (ctlr->r_res1) 354 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1, ctlr->r_res1); 355 return ENXIO; 356 } 357 358 static int 359 ata_promise_ch_attach(device_t dev) 360 { 361 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 362 struct ata_channel *ch = device_get_softc(dev); 363 364 if (ata_pci_ch_attach(dev)) 365 return ENXIO; 366 367 if (ctlr->chip->cfg1 == PR_NEW) { 368 ch->dma.start = ata_promise_dmastart; 369 ch->dma.stop = ata_promise_dmastop; 370 ch->dma.reset = ata_promise_dmareset; 371 } 372 373 ch->hw.status = ata_promise_status; 374 ch->flags |= ATA_NO_ATAPI_DMA; 375 ch->flags |= ATA_CHECKS_CABLE; 376 return 0; 377 } 378 379 static int 380 ata_promise_status(device_t dev) 381 { 382 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 383 struct ata_channel *ch = device_get_softc(dev); 384 385 if (ATA_INL(ctlr->r_res1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)) { 386 return ata_pci_status(dev); 387 } 388 return 0; 389 } 390 391 static int 392 ata_promise_dmastart(struct ata_request *request) 393 { 394 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 395 struct ata_channel *ch = device_get_softc(request->parent); 396 397 if (request->flags & ATA_R_48BIT) { 398 ATA_OUTB(ctlr->r_res1, 0x11, 399 ATA_INB(ctlr->r_res1, 0x11) | (ch->unit ? 0x08 : 0x02)); 400 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 401 ((request->flags & ATA_R_READ) ? 0x05000000 : 0x06000000) | 402 (request->bytecount >> 1)); 403 } 404 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) | 405 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 406 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, request->dma->sg_bus); 407 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 408 ((request->flags & ATA_R_READ) ? ATA_BMCMD_WRITE_READ : 0) | 409 ATA_BMCMD_START_STOP); 410 ch->dma.flags |= ATA_DMA_ACTIVE; 411 return 0; 412 } 413 414 static int 415 ata_promise_dmastop(struct ata_request *request) 416 { 417 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 418 struct ata_channel *ch = device_get_softc(request->parent); 419 int error; 420 421 if (request->flags & ATA_R_48BIT) { 422 ATA_OUTB(ctlr->r_res1, 0x11, 423 ATA_INB(ctlr->r_res1, 0x11) & ~(ch->unit ? 0x08 : 0x02)); 424 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 0); 425 } 426 error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT); 427 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 428 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 429 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 430 ch->dma.flags &= ~ATA_DMA_ACTIVE; 431 return error; 432 } 433 434 static void 435 ata_promise_dmareset(device_t dev) 436 { 437 struct ata_channel *ch = device_get_softc(dev); 438 439 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 440 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 441 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 442 ch->flags &= ~ATA_DMA_ACTIVE; 443 } 444 445 static int 446 ata_promise_setmode(device_t dev, int target, int mode) 447 { 448 device_t parent = device_get_parent(dev); 449 struct ata_pci_controller *ctlr = device_get_softc(parent); 450 struct ata_channel *ch = device_get_softc(dev); 451 int devno = (ch->unit << 1) + target; 452 static const uint32_t timings[][2] = { 453 /* PR_OLD PR_NEW mode */ 454 { 0x004ff329, 0x004fff2f }, /* PIO 0 */ 455 { 0x004fec25, 0x004ff82a }, /* PIO 1 */ 456 { 0x004fe823, 0x004ff026 }, /* PIO 2 */ 457 { 0x004fe622, 0x004fec24 }, /* PIO 3 */ 458 { 0x004fe421, 0x004fe822 }, /* PIO 4 */ 459 { 0x004567f3, 0x004acef6 }, /* MWDMA 0 */ 460 { 0x004467f3, 0x0048cef6 }, /* MWDMA 1 */ 461 { 0x004367f3, 0x0046cef6 }, /* MWDMA 2 */ 462 { 0x004367f3, 0x0046cef6 }, /* UDMA 0 */ 463 { 0x004247f3, 0x00448ef6 }, /* UDMA 1 */ 464 { 0x004127f3, 0x00436ef6 }, /* UDMA 2 */ 465 { 0, 0x00424ef6 }, /* UDMA 3 */ 466 { 0, 0x004127f3 }, /* UDMA 4 */ 467 { 0, 0x004127f3 } /* UDMA 5 */ 468 }; 469 470 mode = min(mode, ctlr->chip->max_dma); 471 472 switch (ctlr->chip->cfg1) { 473 case PR_OLD: 474 case PR_NEW: 475 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 476 (pci_read_config(parent, 0x50, 2) & 477 (ch->unit ? 1 << 11 : 1 << 10))) { 478 ata_print_cable(dev, "controller"); 479 mode = ATA_UDMA2; 480 } 481 break; 482 483 case PR_TX: 484 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b); 485 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 486 ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x04) { 487 ata_print_cable(dev, "controller"); 488 mode = ATA_UDMA2; 489 } 490 break; 491 492 case PR_MIO: 493 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 494 (ATA_INL(ctlr->r_res2, 495 (ctlr->chip->cfg2 & PR_SX4X ? 0x000c0260 : 0x0260) + 496 (ch->unit << 7)) & 0x01000000)) { 497 ata_print_cable(dev, "controller"); 498 mode = ATA_UDMA2; 499 } 500 break; 501 } 502 503 if (ctlr->chip->cfg1 < PR_TX) 504 pci_write_config(parent, 0x60 + (devno << 2), 505 timings[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); 506 return (mode); 507 } 508 509 static int 510 ata_promise_tx2_ch_attach(device_t dev) 511 { 512 struct ata_channel *ch = device_get_softc(dev); 513 514 if (ata_pci_ch_attach(dev)) 515 return ENXIO; 516 517 ch->hw.status = ata_promise_tx2_status; 518 ch->flags |= ATA_CHECKS_CABLE; 519 return 0; 520 } 521 522 static int 523 ata_promise_tx2_status(device_t dev) 524 { 525 struct ata_channel *ch = device_get_softc(dev); 526 527 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b); 528 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) { 529 return ata_pci_status(dev); 530 } 531 return 0; 532 } 533 534 static int 535 ata_promise_mio_ch_attach(device_t dev) 536 { 537 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 538 struct ata_channel *ch = device_get_softc(dev); 539 int offset = (ctlr->chip->cfg2 & PR_SX4X) ? 0x000c0000 : 0; 540 int i; 541 542 ata_promise_mio_dmainit(dev); 543 544 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 545 ch->r_io[i].res = ctlr->r_res2; 546 ch->r_io[i].offset = offset + 0x0200 + (i << 2) + (ch->unit << 7); 547 } 548 ch->r_io[ATA_CONTROL].res = ctlr->r_res2; 549 ch->r_io[ATA_CONTROL].offset = offset + 0x0238 + (ch->unit << 7); 550 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 551 ata_default_registers(dev); 552 if ((ctlr->chip->cfg2 & (PR_SATA | PR_SATA2)) || 553 ((ctlr->chip->cfg2 & (PR_CMBO | PR_CMBO2)) && ch->unit < 2)) { 554 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 555 ch->r_io[ATA_SSTATUS].offset = 0x400 + (ch->unit << 8); 556 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 557 ch->r_io[ATA_SERROR].offset = 0x404 + (ch->unit << 8); 558 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 559 ch->r_io[ATA_SCONTROL].offset = 0x408 + (ch->unit << 8); 560 ch->flags |= ATA_NO_SLAVE; 561 ch->flags |= ATA_SATA; 562 } 563 ch->flags |= ATA_USE_16BIT; 564 ch->flags |= ATA_CHECKS_CABLE; 565 566 ata_generic_hw(dev); 567 if (ctlr->chip->cfg2 & PR_SX4X) { 568 ch->hw.command = ata_promise_sx4_command; 569 } 570 else { 571 ch->hw.command = ata_promise_mio_command; 572 ch->hw.status = ata_promise_mio_status; 573 ch->hw.softreset = ata_promise_mio_softreset; 574 ch->hw.pm_read = ata_promise_mio_pm_read; 575 ch->hw.pm_write = ata_promise_mio_pm_write; 576 } 577 return 0; 578 } 579 580 static int 581 ata_promise_mio_ch_detach(device_t dev) 582 { 583 584 ata_dmafini(dev); 585 return (0); 586 } 587 588 static void 589 ata_promise_mio_intr(void *data) 590 { 591 struct ata_pci_controller *ctlr = data; 592 struct ata_channel *ch; 593 u_int32_t vector; 594 int unit; 595 596 /* 597 * since reading interrupt status register on early "mio" chips 598 * clears the status bits we cannot read it for each channel later on 599 * in the generic interrupt routine. 600 */ 601 vector = ATA_INL(ctlr->r_res2, 0x040); 602 ATA_OUTL(ctlr->r_res2, 0x040, vector); 603 ctlr->chipset_data = (void *)(uintptr_t)vector; 604 605 for (unit = 0; unit < ctlr->channels; unit++) { 606 if ((ch = ctlr->interrupt[unit].argument)) 607 ctlr->interrupt[unit].function(ch); 608 } 609 610 ctlr->chipset_data = (void *)(uintptr_t)0xffffffff; 611 } 612 613 static int 614 ata_promise_mio_status(device_t dev) 615 { 616 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 617 struct ata_channel *ch = device_get_softc(dev); 618 u_int32_t stat_reg, vector, status; 619 620 switch (ctlr->chip->cfg2) { 621 case PR_PATA: 622 case PR_CMBO: 623 case PR_SATA: 624 stat_reg = 0x6c; 625 break; 626 case PR_CMBO2: 627 case PR_SATA2: 628 default: 629 stat_reg = 0x60; 630 break; 631 } 632 633 /* read and acknowledge interrupt */ 634 vector = (uint32_t)(uintptr_t)ctlr->chipset_data; 635 636 /* read and clear interface status */ 637 status = ATA_INL(ctlr->r_res2, stat_reg); 638 ATA_OUTL(ctlr->r_res2, stat_reg, status & (0x00000011 << ch->unit)); 639 640 /* check for and handle disconnect events */ 641 if (status & (0x00000001 << ch->unit)) { 642 if (bootverbose) 643 device_printf(dev, "DISCONNECT requested\n"); 644 taskqueue_enqueue(taskqueue_thread, &ch->conntask); 645 } 646 647 /* check for and handle connect events */ 648 if (status & (0x00000010 << ch->unit)) { 649 if (bootverbose) 650 device_printf(dev, "CONNECT requested\n"); 651 taskqueue_enqueue(taskqueue_thread, &ch->conntask); 652 } 653 654 /* do we have any device action ? */ 655 return (vector & (1 << (ch->unit + 1))); 656 } 657 658 static int 659 ata_promise_mio_command(struct ata_request *request) 660 { 661 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 662 struct ata_channel *ch = device_get_softc(request->parent); 663 664 u_int32_t *wordp = (u_int32_t *)ch->dma.work; 665 666 ATA_OUTL(ctlr->r_res2, (ch->unit + 1) << 2, 0x00000001); 667 668 if ((ctlr->chip->cfg2 == PR_SATA2) || 669 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) { 670 /* set portmultiplier port */ 671 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), request->unit & 0x0f); 672 } 673 674 /* XXX SOS add ATAPI commands support later */ 675 switch (request->u.ata.command) { 676 default: 677 return ata_generic_command(request); 678 679 case ATA_READ_DMA: 680 case ATA_READ_DMA48: 681 wordp[0] = htole32(0x04 | ((ch->unit + 1) << 16) | (0x00 << 24)); 682 break; 683 684 case ATA_WRITE_DMA: 685 case ATA_WRITE_DMA48: 686 wordp[0] = htole32(0x00 | ((ch->unit + 1) << 16) | (0x00 << 24)); 687 break; 688 } 689 wordp[1] = htole32(request->dma->sg_bus); 690 wordp[2] = 0; 691 ata_promise_apkt((u_int8_t*)wordp, request); 692 693 ATA_OUTL(ctlr->r_res2, 0x0240 + (ch->unit << 7), ch->dma.work_bus); 694 return 0; 695 } 696 697 static void 698 ata_promise_mio_reset(device_t dev) 699 { 700 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 701 struct ata_channel *ch = device_get_softc(dev); 702 struct ata_promise_sx4 *hpktp; 703 704 switch (ctlr->chip->cfg2) { 705 case PR_SX4X: 706 707 /* softreset channel ATA module */ 708 hpktp = ctlr->chipset_data; 709 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), ch->unit + 1); 710 ata_udelay(1000); 711 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), 712 (ATA_INL(ctlr->r_res2, 0xc0260 + (ch->unit << 7)) & 713 ~0x00003f9f) | (ch->unit + 1)); 714 715 /* softreset HOST module */ /* XXX SOS what about other outstandings */ 716 mtx_lock(&hpktp->mtx); 717 ATA_OUTL(ctlr->r_res2, 0xc012c, 718 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f) | (1 << 11)); 719 DELAY(10); 720 ATA_OUTL(ctlr->r_res2, 0xc012c, 721 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f)); 722 hpktp->busy = 0; 723 mtx_unlock(&hpktp->mtx); 724 ata_generic_reset(dev); 725 break; 726 727 case PR_PATA: 728 case PR_CMBO: 729 case PR_SATA: 730 if ((ctlr->chip->cfg2 == PR_SATA) || 731 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2))) { 732 /* mask plug/unplug intr */ 733 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00110000 << ch->unit)); 734 } 735 736 /* softreset channels ATA module */ 737 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11)); 738 ata_udelay(10000); 739 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), 740 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) & 741 ~0x00003f9f) | (ch->unit + 1)); 742 743 if ((ctlr->chip->cfg2 == PR_SATA) || 744 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2))) { 745 if (ata_sata_phy_reset(dev, -1, 1)) 746 ata_generic_reset(dev); 747 else 748 ch->devices = 0; 749 750 /* reset and enable plug/unplug intr */ 751 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00000011 << ch->unit)); 752 } 753 else 754 ata_generic_reset(dev); 755 break; 756 757 case PR_CMBO2: 758 case PR_SATA2: 759 if ((ctlr->chip->cfg2 == PR_SATA2) || 760 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) { 761 /* set portmultiplier port */ 762 //ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f); 763 764 /* mask plug/unplug intr */ 765 ATA_OUTL(ctlr->r_res2, 0x060, (0x00110000 << ch->unit)); 766 } 767 768 /* softreset channels ATA module */ 769 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11)); 770 ata_udelay(10000); 771 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), 772 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) & 773 ~0x00003f9f) | (ch->unit + 1)); 774 775 if ((ctlr->chip->cfg2 == PR_SATA2) || 776 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) { 777 /* set PHY mode to "improved" */ 778 ATA_OUTL(ctlr->r_res2, 0x414 + (ch->unit << 8), 779 (ATA_INL(ctlr->r_res2, 0x414 + (ch->unit << 8)) & 780 ~0x00000003) | 0x00000001); 781 782 if (ata_sata_phy_reset(dev, -1, 1)) { 783 u_int32_t signature = ch->hw.softreset(dev, ATA_PM); 784 785 if (bootverbose) 786 device_printf(dev, "SIGNATURE: %08x\n", signature); 787 788 switch (signature >> 16) { 789 case 0x0000: 790 ch->devices = ATA_ATA_MASTER; 791 break; 792 case 0x9669: 793 ch->devices = ATA_PORTMULTIPLIER; 794 ata_pm_identify(dev); 795 break; 796 case 0xeb14: 797 ch->devices = ATA_ATAPI_MASTER; 798 break; 799 default: /* SOS XXX */ 800 if (bootverbose) 801 device_printf(dev, 802 "No signature, assuming disk device\n"); 803 ch->devices = ATA_ATA_MASTER; 804 } 805 if (bootverbose) 806 device_printf(dev, "promise_mio_reset devices=%08x\n", 807 ch->devices); 808 809 } else 810 ch->devices = 0; 811 812 /* reset and enable plug/unplug intr */ 813 ATA_OUTL(ctlr->r_res2, 0x060, (0x00000011 << ch->unit)); 814 815 ///* set portmultiplier port */ 816 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x00); 817 } 818 else 819 ata_generic_reset(dev); 820 break; 821 } 822 } 823 824 static int 825 ata_promise_mio_pm_read(device_t dev, int port, int reg, u_int32_t *result) 826 { 827 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 828 struct ata_channel *ch = device_get_softc(dev); 829 int timeout = 0; 830 831 if (port < 0) { 832 *result = ATA_IDX_INL(ch, reg); 833 return (0); 834 } 835 if (port < ATA_PM) { 836 switch (reg) { 837 case ATA_SSTATUS: 838 reg = 0; 839 break; 840 case ATA_SERROR: 841 reg = 1; 842 break; 843 case ATA_SCONTROL: 844 reg = 2; 845 break; 846 default: 847 return (EINVAL); 848 } 849 } 850 /* set portmultiplier port */ 851 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f); 852 853 ATA_IDX_OUTB(ch, ATA_FEATURE, reg); 854 ATA_IDX_OUTB(ch, ATA_DRIVE, port); 855 856 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_READ_PM); 857 858 while (timeout < 1000000) { 859 u_int8_t status = ATA_IDX_INB(ch, ATA_STATUS); 860 if (!(status & ATA_S_BUSY)) 861 break; 862 timeout += 1000; 863 DELAY(1000); 864 } 865 if (timeout >= 1000000) 866 return ATA_E_ABORT; 867 868 *result = ATA_IDX_INB(ch, ATA_COUNT) | 869 (ATA_IDX_INB(ch, ATA_SECTOR) << 8) | 870 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 16) | 871 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 24); 872 return 0; 873 } 874 875 static int 876 ata_promise_mio_pm_write(device_t dev, int port, int reg, u_int32_t value) 877 { 878 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 879 struct ata_channel *ch = device_get_softc(dev); 880 int timeout = 0; 881 882 if (port < 0) { 883 ATA_IDX_OUTL(ch, reg, value); 884 return (0); 885 } 886 if (port < ATA_PM) { 887 switch (reg) { 888 case ATA_SSTATUS: 889 reg = 0; 890 break; 891 case ATA_SERROR: 892 reg = 1; 893 break; 894 case ATA_SCONTROL: 895 reg = 2; 896 break; 897 default: 898 return (EINVAL); 899 } 900 } 901 /* set portmultiplier port */ 902 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f); 903 904 ATA_IDX_OUTB(ch, ATA_FEATURE, reg); 905 ATA_IDX_OUTB(ch, ATA_DRIVE, port); 906 ATA_IDX_OUTB(ch, ATA_COUNT, value & 0xff); 907 ATA_IDX_OUTB(ch, ATA_SECTOR, (value >> 8) & 0xff); 908 ATA_IDX_OUTB(ch, ATA_CYL_LSB, (value >> 16) & 0xff); 909 ATA_IDX_OUTB(ch, ATA_CYL_MSB, (value >> 24) & 0xff); 910 911 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_WRITE_PM); 912 913 while (timeout < 1000000) { 914 u_int8_t status = ATA_IDX_INB(ch, ATA_STATUS); 915 if (!(status & ATA_S_BUSY)) 916 break; 917 timeout += 1000; 918 DELAY(1000); 919 } 920 if (timeout >= 1000000) 921 return ATA_E_ABORT; 922 923 return ATA_IDX_INB(ch, ATA_ERROR); 924 } 925 926 /* must be called with ATA channel locked and state_mtx held */ 927 static u_int32_t 928 ata_promise_mio_softreset(device_t dev, int port) 929 { 930 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 931 struct ata_channel *ch = device_get_softc(dev); 932 int timeout; 933 934 /* set portmultiplier port */ 935 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), port & 0x0f); 936 937 /* softreset device on this channel */ 938 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_MASTER)); 939 DELAY(10); 940 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS | ATA_A_RESET); 941 ata_udelay(10000); 942 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS); 943 ata_udelay(150000); 944 ATA_IDX_INB(ch, ATA_ERROR); 945 946 /* wait for BUSY to go inactive */ 947 for (timeout = 0; timeout < 100; timeout++) { 948 u_int8_t /* err, */ stat; 949 950 /* err = */ ATA_IDX_INB(ch, ATA_ERROR); 951 stat = ATA_IDX_INB(ch, ATA_STATUS); 952 953 //if (stat == err && timeout > (stat & ATA_S_BUSY ? 100 : 10)) 954 //break; 955 956 if (!(stat & ATA_S_BUSY)) { 957 //if ((err & 0x7f) == ATA_E_ILI) { 958 return ATA_IDX_INB(ch, ATA_COUNT) | 959 (ATA_IDX_INB(ch, ATA_SECTOR) << 8) | 960 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 16) | 961 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 24); 962 //} 963 //else if (stat & 0x0f) { 964 //stat |= ATA_S_BUSY; 965 //} 966 } 967 968 if (!(stat & ATA_S_BUSY) || (stat == 0xff && timeout > 10)) 969 break; 970 ata_udelay(100000); 971 } 972 return -1; 973 } 974 975 static void 976 ata_promise_mio_dmainit(device_t dev) 977 { 978 struct ata_channel *ch = device_get_softc(dev); 979 980 /* note start and stop are not used here */ 981 ch->dma.setprd = ata_promise_mio_setprd; 982 ch->dma.max_iosize = 65536; 983 ata_dmainit(dev); 984 } 985 986 #define MAXLASTSGSIZE (32 * sizeof(u_int32_t)) 987 static void 988 ata_promise_mio_setprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 989 { 990 struct ata_dmasetprd_args *args = xsc; 991 struct ata_dma_prdentry *prd = args->dmatab; 992 int i; 993 994 if ((args->error = error)) 995 return; 996 997 for (i = 0; i < nsegs; i++) { 998 prd[i].addr = htole32(segs[i].ds_addr); 999 prd[i].count = htole32(segs[i].ds_len); 1000 } 1001 if (segs[i - 1].ds_len > MAXLASTSGSIZE) { 1002 //printf("split last SG element of %u\n", segs[i - 1].ds_len); 1003 prd[i - 1].count = htole32(segs[i - 1].ds_len - MAXLASTSGSIZE); 1004 prd[i].count = htole32(MAXLASTSGSIZE); 1005 prd[i].addr = htole32(segs[i - 1].ds_addr + 1006 (segs[i - 1].ds_len - MAXLASTSGSIZE)); 1007 nsegs++; 1008 i++; 1009 } 1010 prd[i - 1].count |= htole32(ATA_DMA_EOT); 1011 KASSERT(nsegs <= ATA_DMA_ENTRIES, ("too many DMA segment entries\n")); 1012 args->nsegs = nsegs; 1013 } 1014 1015 static int 1016 ata_promise_mio_setmode(device_t dev, int target, int mode) 1017 { 1018 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1019 struct ata_channel *ch = device_get_softc(dev); 1020 1021 if ( (ctlr->chip->cfg2 == PR_SATA) || 1022 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2)) || 1023 (ctlr->chip->cfg2 == PR_SATA2) || 1024 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) 1025 mode = ata_sata_setmode(dev, target, mode); 1026 else 1027 mode = ata_promise_setmode(dev, target, mode); 1028 return (mode); 1029 } 1030 1031 static int 1032 ata_promise_mio_getrev(device_t dev, int target) 1033 { 1034 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1035 struct ata_channel *ch = device_get_softc(dev); 1036 1037 if ( (ctlr->chip->cfg2 == PR_SATA) || 1038 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2)) || 1039 (ctlr->chip->cfg2 == PR_SATA2) || 1040 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) 1041 return (ata_sata_getrev(dev, target)); 1042 else 1043 return (0); 1044 } 1045 1046 static void 1047 ata_promise_sx4_intr(void *data) 1048 { 1049 struct ata_pci_controller *ctlr = data; 1050 struct ata_channel *ch; 1051 u_int32_t vector = ATA_INL(ctlr->r_res2, 0x000c0480); 1052 int unit; 1053 1054 for (unit = 0; unit < ctlr->channels; unit++) { 1055 if (vector & (1 << (unit + 1))) 1056 if ((ch = ctlr->interrupt[unit].argument)) 1057 ctlr->interrupt[unit].function(ch); 1058 if (vector & (1 << (unit + 5))) 1059 if ((ch = ctlr->interrupt[unit].argument)) 1060 ata_promise_queue_hpkt(ctlr, 1061 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + 1062 ATA_PDC_HPKT_OFFSET)); 1063 if (vector & (1 << (unit + 9))) { 1064 ata_promise_next_hpkt(ctlr); 1065 if ((ch = ctlr->interrupt[unit].argument)) 1066 ctlr->interrupt[unit].function(ch); 1067 } 1068 if (vector & (1 << (unit + 13))) { 1069 ata_promise_next_hpkt(ctlr); 1070 if ((ch = ctlr->interrupt[unit].argument)) 1071 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 1072 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + 1073 ATA_PDC_APKT_OFFSET)); 1074 } 1075 } 1076 } 1077 1078 static int 1079 ata_promise_sx4_command(struct ata_request *request) 1080 { 1081 device_t gparent = device_get_parent(request->parent); 1082 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1083 struct ata_channel *ch = device_get_softc(request->parent); 1084 struct ata_dma_prdentry *prd; 1085 caddr_t window = rman_get_virtual(ctlr->r_res1); 1086 u_int32_t *wordp; 1087 int i, idx; 1088 1089 /* XXX SOS add ATAPI commands support later */ 1090 switch (request->u.ata.command) { 1091 1092 default: 1093 return -1; 1094 1095 case ATA_ATA_IDENTIFY: 1096 case ATA_READ: 1097 case ATA_READ48: 1098 case ATA_READ_MUL: 1099 case ATA_READ_MUL48: 1100 case ATA_WRITE: 1101 case ATA_WRITE48: 1102 case ATA_WRITE_MUL: 1103 case ATA_WRITE_MUL48: 1104 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001); 1105 return ata_generic_command(request); 1106 1107 case ATA_SETFEATURES: 1108 case ATA_FLUSHCACHE: 1109 case ATA_FLUSHCACHE48: 1110 case ATA_SLEEP: 1111 case ATA_SET_MULTI: 1112 wordp = (u_int32_t *) 1113 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET); 1114 wordp[0] = htole32(0x08 | ((ch->unit + 1)<<16) | (0x00 << 24)); 1115 wordp[1] = 0; 1116 wordp[2] = 0; 1117 ata_promise_apkt((u_int8_t *)wordp, request); 1118 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001); 1119 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001); 1120 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 1121 htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_APKT_OFFSET)); 1122 return 0; 1123 1124 case ATA_READ_DMA: 1125 case ATA_READ_DMA48: 1126 case ATA_WRITE_DMA: 1127 case ATA_WRITE_DMA48: 1128 prd = request->dma->sg; 1129 wordp = (u_int32_t *) 1130 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HSG_OFFSET); 1131 i = idx = 0; 1132 do { 1133 wordp[idx++] = prd[i].addr; 1134 wordp[idx++] = prd[i].count; 1135 } while (!(prd[i++].count & ATA_DMA_EOT)); 1136 1137 wordp = (u_int32_t *) 1138 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_LSG_OFFSET); 1139 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE); 1140 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT); 1141 1142 wordp = (u_int32_t *) 1143 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_ASG_OFFSET); 1144 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE); 1145 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT); 1146 1147 wordp = (u_int32_t *) 1148 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET); 1149 if (request->flags & ATA_R_READ) 1150 wordp[0] = htole32(0x14 | ((ch->unit+9)<<16) | ((ch->unit+5)<<24)); 1151 if (request->flags & ATA_R_WRITE) 1152 wordp[0] = htole32(0x00 | ((ch->unit+13)<<16) | (0x00<<24)); 1153 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_HSG_OFFSET); 1154 wordp[2] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_LSG_OFFSET); 1155 wordp[3] = 0; 1156 1157 wordp = (u_int32_t *) 1158 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET); 1159 if (request->flags & ATA_R_READ) 1160 wordp[0] = htole32(0x04 | ((ch->unit+5)<<16) | (0x00<<24)); 1161 if (request->flags & ATA_R_WRITE) 1162 wordp[0] = htole32(0x10 | ((ch->unit+1)<<16) | ((ch->unit+13)<<24)); 1163 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_ASG_OFFSET); 1164 wordp[2] = 0; 1165 ata_promise_apkt((u_int8_t *)wordp, request); 1166 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001); 1167 1168 if (request->flags & ATA_R_READ) { 1169 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+5)<<2), 0x00000001); 1170 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+9)<<2), 0x00000001); 1171 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 1172 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET)); 1173 } 1174 if (request->flags & ATA_R_WRITE) { 1175 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+1)<<2), 0x00000001); 1176 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+13)<<2), 0x00000001); 1177 ata_promise_queue_hpkt(ctlr, 1178 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET)); 1179 } 1180 return 0; 1181 } 1182 } 1183 1184 static int 1185 ata_promise_apkt(u_int8_t *bytep, struct ata_request *request) 1186 { 1187 int i = 12; 1188 1189 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_PDC_WAIT_NBUSY|ATA_DRIVE; 1190 bytep[i++] = ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit); 1191 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_CTL; 1192 bytep[i++] = ATA_A_4BIT; 1193 1194 if (request->flags & ATA_R_48BIT) { 1195 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_FEATURE; 1196 bytep[i++] = request->u.ata.feature >> 8; 1197 bytep[i++] = request->u.ata.feature; 1198 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_COUNT; 1199 bytep[i++] = request->u.ata.count >> 8; 1200 bytep[i++] = request->u.ata.count; 1201 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_SECTOR; 1202 bytep[i++] = request->u.ata.lba >> 24; 1203 bytep[i++] = request->u.ata.lba; 1204 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_LSB; 1205 bytep[i++] = request->u.ata.lba >> 32; 1206 bytep[i++] = request->u.ata.lba >> 8; 1207 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_MSB; 1208 bytep[i++] = request->u.ata.lba >> 40; 1209 bytep[i++] = request->u.ata.lba >> 16; 1210 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE; 1211 bytep[i++] = ATA_D_LBA | ATA_DEV(request->unit); 1212 } 1213 else { 1214 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_FEATURE; 1215 bytep[i++] = request->u.ata.feature; 1216 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_COUNT; 1217 bytep[i++] = request->u.ata.count; 1218 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_SECTOR; 1219 bytep[i++] = request->u.ata.lba; 1220 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_LSB; 1221 bytep[i++] = request->u.ata.lba >> 8; 1222 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_MSB; 1223 bytep[i++] = request->u.ata.lba >> 16; 1224 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE; 1225 bytep[i++] = ATA_D_LBA | ATA_D_IBM | ATA_DEV(request->unit) | 1226 ((request->u.ata.lba >> 24)&0xf); 1227 } 1228 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_END | ATA_COMMAND; 1229 bytep[i++] = request->u.ata.command; 1230 return i; 1231 } 1232 1233 static void 1234 ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt) 1235 { 1236 struct ata_promise_sx4 *hpktp = ctlr->chipset_data; 1237 1238 mtx_lock(&hpktp->mtx); 1239 if (hpktp->busy) { 1240 struct host_packet *hp = 1241 malloc(sizeof(struct host_packet), M_TEMP, M_NOWAIT | M_ZERO); 1242 hp->addr = hpkt; 1243 TAILQ_INSERT_TAIL(&hpktp->queue, hp, chain); 1244 } 1245 else { 1246 hpktp->busy = 1; 1247 ATA_OUTL(ctlr->r_res2, 0x000c0100, hpkt); 1248 } 1249 mtx_unlock(&hpktp->mtx); 1250 } 1251 1252 static void 1253 ata_promise_next_hpkt(struct ata_pci_controller *ctlr) 1254 { 1255 struct ata_promise_sx4 *hpktp = ctlr->chipset_data; 1256 struct host_packet *hp; 1257 1258 mtx_lock(&hpktp->mtx); 1259 if ((hp = TAILQ_FIRST(&hpktp->queue))) { 1260 TAILQ_REMOVE(&hpktp->queue, hp, chain); 1261 ATA_OUTL(ctlr->r_res2, 0x000c0100, hp->addr); 1262 free(hp, M_TEMP); 1263 } 1264 else 1265 hpktp->busy = 0; 1266 mtx_unlock(&hpktp->mtx); 1267 } 1268 1269 ATA_DECLARE_DRIVER(ata_promise); 1270