1 /*- 2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/module.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/ata.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/malloc.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 #include <sys/sema.h> 41 #include <sys/taskqueue.h> 42 #include <vm/uma.h> 43 #include <machine/stdarg.h> 44 #include <machine/resource.h> 45 #include <machine/bus.h> 46 #include <sys/rman.h> 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcireg.h> 49 #include <dev/ata/ata-all.h> 50 #include <dev/ata/ata-pci.h> 51 #include <ata_if.h> 52 53 /* local prototypes */ 54 static int ata_intel_chipinit(device_t dev); 55 static int ata_intel_chipdeinit(device_t dev); 56 static int ata_intel_ch_attach(device_t dev); 57 static void ata_intel_reset(device_t dev); 58 static int ata_intel_old_setmode(device_t dev, int target, int mode); 59 static int ata_intel_new_setmode(device_t dev, int target, int mode); 60 static int ata_intel_sch_setmode(device_t dev, int target, int mode); 61 static int ata_intel_sata_getrev(device_t dev, int target); 62 static int ata_intel_sata_status(device_t dev); 63 static int ata_intel_sata_ahci_read(device_t dev, int port, 64 int reg, u_int32_t *result); 65 static int ata_intel_sata_cscr_read(device_t dev, int port, 66 int reg, u_int32_t *result); 67 static int ata_intel_sata_sidpr_read(device_t dev, int port, 68 int reg, u_int32_t *result); 69 static int ata_intel_sata_ahci_write(device_t dev, int port, 70 int reg, u_int32_t result); 71 static int ata_intel_sata_cscr_write(device_t dev, int port, 72 int reg, u_int32_t result); 73 static int ata_intel_sata_sidpr_write(device_t dev, int port, 74 int reg, u_int32_t result); 75 static int ata_intel_sata_sidpr_test(device_t dev); 76 static int ata_intel_31244_ch_attach(device_t dev); 77 static int ata_intel_31244_ch_detach(device_t dev); 78 static int ata_intel_31244_status(device_t dev); 79 static void ata_intel_31244_tf_write(struct ata_request *request); 80 static void ata_intel_31244_reset(device_t dev); 81 82 /* misc defines */ 83 #define INTEL_ICH5 2 84 #define INTEL_6CH 4 85 #define INTEL_6CH2 8 86 #define INTEL_ICH7 16 87 88 struct ata_intel_data { 89 struct mtx lock; 90 u_char smap[4]; 91 }; 92 93 #define ATA_INTEL_SMAP(ctlr, ch) \ 94 &((struct ata_intel_data *)((ctlr)->chipset_data))->smap[(ch)->unit * 2] 95 #define ATA_INTEL_LOCK(ctlr) \ 96 mtx_lock(&((struct ata_intel_data *)((ctlr)->chipset_data))->lock) 97 #define ATA_INTEL_UNLOCK(ctlr) \ 98 mtx_unlock(&((struct ata_intel_data *)((ctlr)->chipset_data))->lock) 99 100 /* 101 * Intel chipset support functions 102 */ 103 static int 104 ata_intel_probe(device_t dev) 105 { 106 struct ata_pci_controller *ctlr = device_get_softc(dev); 107 static const struct ata_chip_id ids[] = 108 {{ ATA_I82371FB, 0, 0, 2, ATA_WDMA2, "PIIX" }, 109 { ATA_I82371SB, 0, 0, 2, ATA_WDMA2, "PIIX3" }, 110 { ATA_I82371AB, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 111 { ATA_I82443MX, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 112 { ATA_I82451NX, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 113 { ATA_I82801AB, 0, 0, 2, ATA_UDMA2, "ICH0" }, 114 { ATA_I82801AA, 0, 0, 2, ATA_UDMA4, "ICH" }, 115 { ATA_I82372FB, 0, 0, 2, ATA_UDMA4, "ICH" }, 116 { ATA_I82801BA, 0, 0, 2, ATA_UDMA5, "ICH2" }, 117 { ATA_I82801BA_1, 0, 0, 2, ATA_UDMA5, "ICH2" }, 118 { ATA_I82801CA, 0, 0, 2, ATA_UDMA5, "ICH3" }, 119 { ATA_I82801CA_1, 0, 0, 2, ATA_UDMA5, "ICH3" }, 120 { ATA_I82801DB, 0, 0, 2, ATA_UDMA5, "ICH4" }, 121 { ATA_I82801DB_1, 0, 0, 2, ATA_UDMA5, "ICH4" }, 122 { ATA_I82801EB, 0, 0, 2, ATA_UDMA5, "ICH5" }, 123 { ATA_I82801EB_S1, 0, INTEL_ICH5, 2, ATA_SA150, "ICH5" }, 124 { ATA_I82801EB_R1, 0, INTEL_ICH5, 2, ATA_SA150, "ICH5" }, 125 { ATA_I6300ESB, 0, 0, 2, ATA_UDMA5, "6300ESB" }, 126 { ATA_I6300ESB_S1, 0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" }, 127 { ATA_I6300ESB_R1, 0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" }, 128 { ATA_I82801FB, 0, 0, 2, ATA_UDMA5, "ICH6" }, 129 { ATA_I82801FB_S1, 0, 0, 0, ATA_SA150, "ICH6" }, 130 { ATA_I82801FB_R1, 0, 0, 0, ATA_SA150, "ICH6" }, 131 { ATA_I82801FBM, 0, 0, 0, ATA_SA150, "ICH6M" }, 132 { ATA_I82801GB, 0, 0, 1, ATA_UDMA5, "ICH7" }, 133 { ATA_I82801GB_S1, 0, INTEL_ICH7, 0, ATA_SA300, "ICH7" }, 134 { ATA_I82801GBM_S1, 0, INTEL_ICH7, 0, ATA_SA150, "ICH7M" }, 135 { ATA_I63XXESB2, 0, 0, 1, ATA_UDMA5, "63XXESB2" }, 136 { ATA_I63XXESB2_S1, 0, 0, 0, ATA_SA300, "63XXESB2" }, 137 { ATA_I82801HB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH8" }, 138 { ATA_I82801HB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH8" }, 139 { ATA_I82801HBM, 0, 0, 1, ATA_UDMA5, "ICH8M" }, 140 { ATA_I82801HBM_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH8M" }, 141 { ATA_I82801IB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH9" }, 142 { ATA_I82801IB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9" }, 143 { ATA_I82801IB_S3, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9" }, 144 { ATA_I82801IBM_S1, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9M" }, 145 { ATA_I82801IBM_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9M" }, 146 { ATA_I82801JIB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, 147 { ATA_I82801JIB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, 148 { ATA_I82801JD_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, 149 { ATA_I82801JD_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, 150 { ATA_I82801JI_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, 151 { ATA_I82801JI_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, 152 { ATA_5Series_S1, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 153 { ATA_5Series_S2, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 154 { ATA_5Series_S3, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 155 { ATA_5Series_S4, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 156 { ATA_5Series_S5, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 157 { ATA_5Series_S6, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 158 { ATA_CPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Cougar Point" }, 159 { ATA_CPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Cougar Point" }, 160 { ATA_CPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" }, 161 { ATA_CPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" }, 162 { ATA_PBG_S1, 0, INTEL_6CH, 0, ATA_SA300, "Patsburg" }, 163 { ATA_PBG_S2, 0, INTEL_6CH2, 0, ATA_SA300, "Patsburg" }, 164 { ATA_PPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Panther Point" }, 165 { ATA_PPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Panther Point" }, 166 { ATA_PPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Panther Point" }, 167 { ATA_PPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Panther Point" }, 168 { ATA_AVOTON_S1, 0, INTEL_6CH, 0, ATA_SA300, "Avoton" }, 169 { ATA_AVOTON_S2, 0, INTEL_6CH, 0, ATA_SA300, "Avoton" }, 170 { ATA_AVOTON_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Avoton" }, 171 { ATA_AVOTON_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Avoton" }, 172 { ATA_LPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Lynx Point" }, 173 { ATA_LPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Lynx Point" }, 174 { ATA_LPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point" }, 175 { ATA_LPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point" }, 176 { ATA_WCPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Wildcat Point" }, 177 { ATA_WCPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Wildcat Point" }, 178 { ATA_WCPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Wildcat Point" }, 179 { ATA_WCPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Wildcat Point" }, 180 { ATA_WELLS_S1, 0, INTEL_6CH, 0, ATA_SA300, "Wellsburg" }, 181 { ATA_WELLS_S2, 0, INTEL_6CH2, 0, ATA_SA300, "Wellsburg" }, 182 { ATA_WELLS_S3, 0, INTEL_6CH, 0, ATA_SA300, "Wellsburg" }, 183 { ATA_WELLS_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Wellsburg" }, 184 { ATA_LPTLP_S1, 0, INTEL_6CH, 0, ATA_SA300, "Lynx Point-LP" }, 185 { ATA_LPTLP_S2, 0, INTEL_6CH, 0, ATA_SA300, "Lynx Point-LP" }, 186 { ATA_LPTLP_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point-LP" }, 187 { ATA_LPTLP_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point-LP" }, 188 { ATA_I31244, 0, 0, 2, ATA_SA150, "31244" }, 189 { ATA_ISCH, 0, 0, 1, ATA_UDMA5, "SCH" }, 190 { ATA_COLETOCRK_S1, 0, INTEL_6CH2, 0, ATA_SA300, "COLETOCRK" }, 191 { ATA_COLETOCRK_S2, 0, INTEL_6CH2, 0, ATA_SA300, "COLETOCRK" }, 192 { 0, 0, 0, 0, 0, 0}}; 193 194 if (pci_get_vendor(dev) != ATA_INTEL_ID) 195 return ENXIO; 196 197 if (!(ctlr->chip = ata_match_chip(dev, ids))) 198 return ENXIO; 199 200 ata_set_desc(dev); 201 ctlr->chipinit = ata_intel_chipinit; 202 ctlr->chipdeinit = ata_intel_chipdeinit; 203 return (BUS_PROBE_LOW_PRIORITY); 204 } 205 206 static int 207 ata_intel_chipinit(device_t dev) 208 { 209 struct ata_pci_controller *ctlr = device_get_softc(dev); 210 struct ata_intel_data *data; 211 212 if (ata_setup_interrupt(dev, ata_generic_intr)) 213 return ENXIO; 214 215 data = malloc(sizeof(struct ata_intel_data), M_ATAPCI, M_WAITOK | M_ZERO); 216 mtx_init(&data->lock, "Intel SATA lock", NULL, MTX_DEF); 217 ctlr->chipset_data = (void *)data; 218 219 /* good old PIIX needs special treatment (not implemented) */ 220 if (ctlr->chip->chipid == ATA_I82371FB) { 221 ctlr->setmode = ata_intel_old_setmode; 222 } 223 224 /* the intel 31244 needs special care if in DPA mode */ 225 else if (ctlr->chip->chipid == ATA_I31244) { 226 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) { 227 ctlr->r_type2 = SYS_RES_MEMORY; 228 ctlr->r_rid2 = PCIR_BAR(0); 229 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 230 &ctlr->r_rid2, 231 RF_ACTIVE))) 232 return ENXIO; 233 ctlr->channels = 4; 234 ctlr->ch_attach = ata_intel_31244_ch_attach; 235 ctlr->ch_detach = ata_intel_31244_ch_detach; 236 ctlr->reset = ata_intel_31244_reset; 237 } 238 ctlr->setmode = ata_sata_setmode; 239 ctlr->getrev = ata_sata_getrev; 240 } 241 /* SCH */ 242 else if (ctlr->chip->chipid == ATA_ISCH) { 243 ctlr->channels = 1; 244 ctlr->ch_attach = ata_intel_ch_attach; 245 ctlr->ch_detach = ata_pci_ch_detach; 246 ctlr->setmode = ata_intel_sch_setmode; 247 } 248 /* non SATA intel chips goes here */ 249 else if (ctlr->chip->max_dma < ATA_SA150) { 250 ctlr->channels = ctlr->chip->cfg2; 251 ctlr->ch_attach = ata_intel_ch_attach; 252 ctlr->ch_detach = ata_pci_ch_detach; 253 ctlr->setmode = ata_intel_new_setmode; 254 } 255 256 /* SATA parts can be either compat or AHCI */ 257 else { 258 /* force all ports active "the legacy way" */ 259 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f, 2); 260 261 ctlr->ch_attach = ata_intel_ch_attach; 262 ctlr->ch_detach = ata_pci_ch_detach; 263 ctlr->reset = ata_intel_reset; 264 265 /* BAR(5) may point to SATA interface registers */ 266 if ((ctlr->chip->cfg1 & INTEL_ICH7)) { 267 ctlr->r_type2 = SYS_RES_MEMORY; 268 ctlr->r_rid2 = PCIR_BAR(5); 269 ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 270 &ctlr->r_rid2, RF_ACTIVE); 271 if (ctlr->r_res2 != NULL) { 272 /* Set SCRAE bit to enable registers access. */ 273 pci_write_config(dev, 0x94, 274 pci_read_config(dev, 0x94, 4) | (1 << 9), 4); 275 /* Set Ports Implemented register bits. */ 276 ATA_OUTL(ctlr->r_res2, 0x0C, 277 ATA_INL(ctlr->r_res2, 0x0C) | 0xf); 278 } 279 /* Skip BAR(5) on ICH8M Apples, system locks up on access. */ 280 } else if (ctlr->chip->chipid != ATA_I82801HBM_S1 || 281 pci_get_subvendor(dev) != 0x106b) { 282 ctlr->r_type2 = SYS_RES_IOPORT; 283 ctlr->r_rid2 = PCIR_BAR(5); 284 ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 285 &ctlr->r_rid2, RF_ACTIVE); 286 } 287 if (ctlr->r_res2 != NULL || 288 (ctlr->chip->cfg1 & INTEL_ICH5)) 289 ctlr->getrev = ata_intel_sata_getrev; 290 ctlr->setmode = ata_sata_setmode; 291 } 292 return 0; 293 } 294 295 static int 296 ata_intel_chipdeinit(device_t dev) 297 { 298 struct ata_pci_controller *ctlr = device_get_softc(dev); 299 struct ata_intel_data *data; 300 301 data = ctlr->chipset_data; 302 mtx_destroy(&data->lock); 303 free(data, M_ATAPCI); 304 ctlr->chipset_data = NULL; 305 return (0); 306 } 307 308 static int 309 ata_intel_ch_attach(device_t dev) 310 { 311 struct ata_pci_controller *ctlr; 312 struct ata_channel *ch; 313 u_char *smap; 314 u_int map; 315 316 /* setup the usual register normal pci style */ 317 if (ata_pci_ch_attach(dev)) 318 return (ENXIO); 319 320 ctlr = device_get_softc(device_get_parent(dev)); 321 ch = device_get_softc(dev); 322 323 /* if r_res2 is valid it points to SATA interface registers */ 324 if (ctlr->r_res2) { 325 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 326 ch->r_io[ATA_IDX_ADDR].offset = 0x00; 327 ch->r_io[ATA_IDX_DATA].res = ctlr->r_res2; 328 ch->r_io[ATA_IDX_DATA].offset = 0x04; 329 } 330 331 ch->flags |= ATA_ALWAYS_DMASTAT; 332 if (ctlr->chip->max_dma >= ATA_SA150) { 333 smap = ATA_INTEL_SMAP(ctlr, ch); 334 map = pci_read_config(device_get_parent(dev), 0x90, 1); 335 if (ctlr->chip->cfg1 & INTEL_ICH5) { 336 map &= 0x07; 337 if ((map & 0x04) == 0) { 338 ch->flags |= ATA_SATA; 339 ch->flags |= ATA_NO_SLAVE; 340 smap[0] = (map & 0x01) ^ ch->unit; 341 smap[1] = 0; 342 } else if ((map & 0x02) == 0 && ch->unit == 0) { 343 ch->flags |= ATA_SATA; 344 smap[0] = (map & 0x01) ? 1 : 0; 345 smap[1] = (map & 0x01) ? 0 : 1; 346 } else if ((map & 0x02) != 0 && ch->unit == 1) { 347 ch->flags |= ATA_SATA; 348 smap[0] = (map & 0x01) ? 1 : 0; 349 smap[1] = (map & 0x01) ? 0 : 1; 350 } 351 } else if (ctlr->chip->cfg1 & INTEL_6CH2) { 352 ch->flags |= ATA_SATA; 353 ch->flags |= ATA_NO_SLAVE; 354 smap[0] = (ch->unit == 0) ? 0 : 1; 355 smap[1] = 0; 356 } else { 357 map &= 0x03; 358 if (map == 0x00) { 359 ch->flags |= ATA_SATA; 360 smap[0] = (ch->unit == 0) ? 0 : 1; 361 smap[1] = (ch->unit == 0) ? 2 : 3; 362 } else if (map == 0x02 && ch->unit == 0) { 363 ch->flags |= ATA_SATA; 364 smap[0] = 0; 365 smap[1] = 2; 366 } else if (map == 0x01 && ch->unit == 1) { 367 ch->flags |= ATA_SATA; 368 smap[0] = 1; 369 smap[1] = 3; 370 } 371 } 372 if (ch->flags & ATA_SATA) { 373 if ((ctlr->chip->cfg1 & INTEL_ICH5)) { 374 ch->hw.pm_read = ata_intel_sata_cscr_read; 375 ch->hw.pm_write = ata_intel_sata_cscr_write; 376 } else if (ctlr->r_res2) { 377 if ((ctlr->chip->cfg1 & INTEL_ICH7)) { 378 ch->hw.pm_read = ata_intel_sata_ahci_read; 379 ch->hw.pm_write = ata_intel_sata_ahci_write; 380 } else if (ata_intel_sata_sidpr_test(dev)) { 381 ch->hw.pm_read = ata_intel_sata_sidpr_read; 382 ch->hw.pm_write = ata_intel_sata_sidpr_write; 383 }; 384 } 385 if (ch->hw.pm_write != NULL) { 386 ch->flags |= ATA_PERIODIC_POLL; 387 ch->hw.status = ata_intel_sata_status; 388 ata_sata_scr_write(ch, 0, 389 ATA_SERROR, 0xffffffff); 390 if ((ch->flags & ATA_NO_SLAVE) == 0) { 391 ata_sata_scr_write(ch, 1, 392 ATA_SERROR, 0xffffffff); 393 } 394 } 395 } else 396 ctlr->setmode = ata_intel_new_setmode; 397 } else if (ctlr->chip->chipid != ATA_ISCH) 398 ch->flags |= ATA_CHECKS_CABLE; 399 return (0); 400 } 401 402 static void 403 ata_intel_reset(device_t dev) 404 { 405 device_t parent = device_get_parent(dev); 406 struct ata_pci_controller *ctlr = device_get_softc(parent); 407 struct ata_channel *ch = device_get_softc(dev); 408 int mask, pshift, timeout, devs; 409 u_char *smap; 410 uint16_t pcs; 411 412 /* In combined mode, skip SATA stuff for PATA channel. */ 413 if ((ch->flags & ATA_SATA) == 0) 414 return (ata_generic_reset(dev)); 415 416 /* Do hard-reset on respective SATA ports. */ 417 smap = ATA_INTEL_SMAP(ctlr, ch); 418 mask = 1 << smap[0]; 419 if ((ch->flags & ATA_NO_SLAVE) == 0) 420 mask |= (1 << smap[1]); 421 pci_write_config(parent, 0x92, 422 pci_read_config(parent, 0x92, 2) & ~mask, 2); 423 DELAY(10); 424 pci_write_config(parent, 0x92, 425 pci_read_config(parent, 0x92, 2) | mask, 2); 426 427 /* Wait up to 1 sec for "connect well". */ 428 if (ctlr->chip->cfg1 & (INTEL_6CH | INTEL_6CH2)) 429 pshift = 8; 430 else 431 pshift = 4; 432 for (timeout = 0; timeout < 100 ; timeout++) { 433 pcs = (pci_read_config(parent, 0x92, 2) >> pshift) & mask; 434 if ((pcs == mask) && (ATA_IDX_INB(ch, ATA_STATUS) != 0xff)) 435 break; 436 ata_udelay(10000); 437 } 438 439 if (bootverbose) 440 device_printf(dev, "SATA reset: ports status=0x%02x\n", pcs); 441 /* If any device found, do soft-reset. */ 442 if (ch->hw.pm_read != NULL) { 443 devs = ata_sata_phy_reset(dev, 0, 2) ? ATA_ATA_MASTER : 0; 444 if ((ch->flags & ATA_NO_SLAVE) == 0) 445 devs |= ata_sata_phy_reset(dev, 1, 2) ? 446 ATA_ATA_SLAVE : 0; 447 } else { 448 devs = (pcs & (1 << smap[0])) ? ATA_ATA_MASTER : 0; 449 if ((ch->flags & ATA_NO_SLAVE) == 0) 450 devs |= (pcs & (1 << smap[1])) ? 451 ATA_ATA_SLAVE : 0; 452 } 453 if (devs) { 454 ata_generic_reset(dev); 455 /* Reset may give fake slave when only ATAPI master present. */ 456 ch->devices &= (devs | (devs * ATA_ATAPI_MASTER)); 457 } else 458 ch->devices = 0; 459 } 460 461 static int 462 ata_intel_old_setmode(device_t dev, int target, int mode) 463 { 464 device_t parent = device_get_parent(dev); 465 struct ata_pci_controller *ctlr = device_get_softc(parent); 466 467 mode = min(mode, ctlr->chip->max_dma); 468 return (mode); 469 } 470 471 static int 472 ata_intel_new_setmode(device_t dev, int target, int mode) 473 { 474 device_t parent = device_get_parent(dev); 475 struct ata_pci_controller *ctlr = device_get_softc(parent); 476 struct ata_channel *ch = device_get_softc(dev); 477 int devno = (ch->unit << 1) + target; 478 int piomode; 479 u_int32_t reg40 = pci_read_config(parent, 0x40, 4); 480 u_int8_t reg44 = pci_read_config(parent, 0x44, 1); 481 u_int8_t reg48 = pci_read_config(parent, 0x48, 1); 482 u_int16_t reg4a = pci_read_config(parent, 0x4a, 2); 483 u_int16_t reg54 = pci_read_config(parent, 0x54, 2); 484 u_int32_t mask40 = 0, new40 = 0; 485 u_int8_t mask44 = 0, new44 = 0; 486 static const uint8_t timings[] = 487 { 0x00, 0x00, 0x10, 0x21, 0x23, 0x00, 0x21, 0x23 }; 488 static const uint8_t utimings[] = 489 { 0x00, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02 }; 490 491 /* In combined mode, skip PATA stuff for SATA channel. */ 492 if (ch->flags & ATA_SATA) 493 return (ata_sata_setmode(dev, target, mode)); 494 495 mode = min(mode, ctlr->chip->max_dma); 496 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 497 !(reg54 & (0x10 << devno))) { 498 ata_print_cable(dev, "controller"); 499 mode = ATA_UDMA2; 500 } 501 /* Enable/disable UDMA and set timings. */ 502 if (mode >= ATA_UDMA0) { 503 pci_write_config(parent, 0x48, reg48 | (0x0001 << devno), 2); 504 pci_write_config(parent, 0x4a, 505 (reg4a & ~(0x3 << (devno << 2))) | 506 (utimings[mode & ATA_MODE_MASK] << (devno<<2)), 2); 507 piomode = ATA_PIO4; 508 } else { 509 pci_write_config(parent, 0x48, reg48 & ~(0x0001 << devno), 2); 510 pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (devno << 2))),2); 511 piomode = mode; 512 } 513 reg54 |= 0x0400; 514 /* Set UDMA reference clock (33/66/133MHz). */ 515 reg54 &= ~(0x1001 << devno); 516 if (mode >= ATA_UDMA5) 517 reg54 |= (0x1000 << devno); 518 else if (mode >= ATA_UDMA3) 519 reg54 |= (0x1 << devno); 520 pci_write_config(parent, 0x54, reg54, 2); 521 /* Allow PIO/WDMA timing controls. */ 522 reg40 &= ~0x00ff00ff; 523 reg40 |= 0x40774077; 524 /* Set PIO/WDMA timings. */ 525 if (target == 0) { 526 mask40 = 0x3300; 527 new40 = timings[ata_mode2idx(piomode)] << 8; 528 } else { 529 mask44 = 0x0f; 530 new44 = ((timings[ata_mode2idx(piomode)] & 0x30) >> 2) | 531 (timings[ata_mode2idx(piomode)] & 0x03); 532 } 533 if (ch->unit) { 534 mask40 <<= 16; 535 new40 <<= 16; 536 mask44 <<= 4; 537 new44 <<= 4; 538 } 539 pci_write_config(parent, 0x40, (reg40 & ~mask40) | new40, 4); 540 pci_write_config(parent, 0x44, (reg44 & ~mask44) | new44, 1); 541 return (mode); 542 } 543 544 static int 545 ata_intel_sch_setmode(device_t dev, int target, int mode) 546 { 547 device_t parent = device_get_parent(dev); 548 struct ata_pci_controller *ctlr = device_get_softc(parent); 549 u_int8_t dtim = 0x80 + (target << 2); 550 u_int32_t tim = pci_read_config(parent, dtim, 4); 551 int piomode; 552 553 mode = min(mode, ctlr->chip->max_dma); 554 if (mode >= ATA_UDMA0) { 555 tim |= (0x1 << 31); 556 tim &= ~(0x7 << 16); 557 tim |= ((mode & ATA_MODE_MASK) << 16); 558 piomode = ATA_PIO4; 559 } else if (mode >= ATA_WDMA0) { 560 tim &= ~(0x1 << 31); 561 tim &= ~(0x3 << 8); 562 tim |= ((mode & ATA_MODE_MASK) << 8); 563 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 : 564 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4; 565 } else 566 piomode = mode; 567 tim &= ~(0x7); 568 tim |= (piomode & 0x7); 569 pci_write_config(parent, dtim, tim, 4); 570 return (mode); 571 } 572 573 static int 574 ata_intel_sata_getrev(device_t dev, int target) 575 { 576 struct ata_channel *ch = device_get_softc(dev); 577 uint32_t status; 578 579 if (ata_sata_scr_read(ch, target, ATA_SSTATUS, &status) == 0) 580 return ((status & 0x0f0) >> 4); 581 return (0xff); 582 } 583 584 static int 585 ata_intel_sata_status(device_t dev) 586 { 587 struct ata_channel *ch = device_get_softc(dev); 588 589 ata_sata_phy_check_events(dev, 0); 590 if ((ch->flags & ATA_NO_SLAVE) == 0) 591 ata_sata_phy_check_events(dev, 1); 592 593 return ata_pci_status(dev); 594 } 595 596 static int 597 ata_intel_sata_ahci_read(device_t dev, int port, int reg, u_int32_t *result) 598 { 599 struct ata_pci_controller *ctlr; 600 struct ata_channel *ch; 601 device_t parent; 602 u_char *smap; 603 int offset; 604 605 parent = device_get_parent(dev); 606 ctlr = device_get_softc(parent); 607 ch = device_get_softc(dev); 608 port = (port == 1) ? 1 : 0; 609 smap = ATA_INTEL_SMAP(ctlr, ch); 610 offset = 0x100 + smap[port] * 0x80; 611 switch (reg) { 612 case ATA_SSTATUS: 613 reg = 0x28; 614 break; 615 case ATA_SCONTROL: 616 reg = 0x2c; 617 break; 618 case ATA_SERROR: 619 reg = 0x30; 620 break; 621 default: 622 return (EINVAL); 623 } 624 *result = ATA_INL(ctlr->r_res2, offset + reg); 625 return (0); 626 } 627 628 static int 629 ata_intel_sata_cscr_read(device_t dev, int port, int reg, u_int32_t *result) 630 { 631 struct ata_pci_controller *ctlr; 632 struct ata_channel *ch; 633 device_t parent; 634 u_char *smap; 635 636 parent = device_get_parent(dev); 637 ctlr = device_get_softc(parent); 638 ch = device_get_softc(dev); 639 smap = ATA_INTEL_SMAP(ctlr, ch); 640 port = (port == 1) ? 1 : 0; 641 switch (reg) { 642 case ATA_SSTATUS: 643 reg = 0; 644 break; 645 case ATA_SERROR: 646 reg = 1; 647 break; 648 case ATA_SCONTROL: 649 reg = 2; 650 break; 651 default: 652 return (EINVAL); 653 } 654 ATA_INTEL_LOCK(ctlr); 655 pci_write_config(parent, 0xa0, 656 0x50 + smap[port] * 0x10 + reg * 4, 4); 657 *result = pci_read_config(parent, 0xa4, 4); 658 ATA_INTEL_UNLOCK(ctlr); 659 return (0); 660 } 661 662 static int 663 ata_intel_sata_sidpr_read(device_t dev, int port, int reg, u_int32_t *result) 664 { 665 struct ata_pci_controller *ctlr; 666 struct ata_channel *ch; 667 device_t parent; 668 669 parent = device_get_parent(dev); 670 ctlr = device_get_softc(parent); 671 ch = device_get_softc(dev); 672 port = (port == 1) ? 1 : 0; 673 switch (reg) { 674 case ATA_SSTATUS: 675 reg = 0; 676 break; 677 case ATA_SCONTROL: 678 reg = 1; 679 break; 680 case ATA_SERROR: 681 reg = 2; 682 break; 683 default: 684 return (EINVAL); 685 } 686 ATA_INTEL_LOCK(ctlr); 687 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, ((ch->unit * 2 + port) << 8) + reg); 688 *result = ATA_IDX_INL(ch, ATA_IDX_DATA); 689 ATA_INTEL_UNLOCK(ctlr); 690 return (0); 691 } 692 693 static int 694 ata_intel_sata_ahci_write(device_t dev, int port, int reg, u_int32_t value) 695 { 696 struct ata_pci_controller *ctlr; 697 struct ata_channel *ch; 698 device_t parent; 699 u_char *smap; 700 int offset; 701 702 parent = device_get_parent(dev); 703 ctlr = device_get_softc(parent); 704 ch = device_get_softc(dev); 705 port = (port == 1) ? 1 : 0; 706 smap = ATA_INTEL_SMAP(ctlr, ch); 707 offset = 0x100 + smap[port] * 0x80; 708 switch (reg) { 709 case ATA_SSTATUS: 710 reg = 0x28; 711 break; 712 case ATA_SCONTROL: 713 reg = 0x2c; 714 break; 715 case ATA_SERROR: 716 reg = 0x30; 717 break; 718 default: 719 return (EINVAL); 720 } 721 ATA_OUTL(ctlr->r_res2, offset + reg, value); 722 return (0); 723 } 724 725 static int 726 ata_intel_sata_cscr_write(device_t dev, int port, int reg, u_int32_t value) 727 { 728 struct ata_pci_controller *ctlr; 729 struct ata_channel *ch; 730 device_t parent; 731 u_char *smap; 732 733 parent = device_get_parent(dev); 734 ctlr = device_get_softc(parent); 735 ch = device_get_softc(dev); 736 smap = ATA_INTEL_SMAP(ctlr, ch); 737 port = (port == 1) ? 1 : 0; 738 switch (reg) { 739 case ATA_SSTATUS: 740 reg = 0; 741 break; 742 case ATA_SERROR: 743 reg = 1; 744 break; 745 case ATA_SCONTROL: 746 reg = 2; 747 break; 748 default: 749 return (EINVAL); 750 } 751 ATA_INTEL_LOCK(ctlr); 752 pci_write_config(parent, 0xa0, 753 0x50 + smap[port] * 0x10 + reg * 4, 4); 754 pci_write_config(parent, 0xa4, value, 4); 755 ATA_INTEL_UNLOCK(ctlr); 756 return (0); 757 } 758 759 static int 760 ata_intel_sata_sidpr_write(device_t dev, int port, int reg, u_int32_t value) 761 { 762 struct ata_pci_controller *ctlr; 763 struct ata_channel *ch; 764 device_t parent; 765 766 parent = device_get_parent(dev); 767 ctlr = device_get_softc(parent); 768 ch = device_get_softc(dev); 769 port = (port == 1) ? 1 : 0; 770 switch (reg) { 771 case ATA_SSTATUS: 772 reg = 0; 773 break; 774 case ATA_SCONTROL: 775 reg = 1; 776 break; 777 case ATA_SERROR: 778 reg = 2; 779 break; 780 default: 781 return (EINVAL); 782 } 783 ATA_INTEL_LOCK(ctlr); 784 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, ((ch->unit * 2 + port) << 8) + reg); 785 ATA_IDX_OUTL(ch, ATA_IDX_DATA, value); 786 ATA_INTEL_UNLOCK(ctlr); 787 return (0); 788 } 789 790 static int 791 ata_intel_sata_sidpr_test(device_t dev) 792 { 793 struct ata_channel *ch = device_get_softc(dev); 794 int port; 795 uint32_t val; 796 797 port = (ch->flags & ATA_NO_SLAVE) ? 0 : 1; 798 for (; port >= 0; port--) { 799 ata_intel_sata_sidpr_read(dev, port, ATA_SCONTROL, &val); 800 if ((val & ATA_SC_IPM_MASK) == 801 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER)) 802 return (1); 803 val |= ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER; 804 ata_intel_sata_sidpr_write(dev, port, ATA_SCONTROL, val); 805 ata_intel_sata_sidpr_read(dev, port, ATA_SCONTROL, &val); 806 if ((val & ATA_SC_IPM_MASK) == 807 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER)) 808 return (1); 809 } 810 if (bootverbose) 811 device_printf(dev, 812 "SControl registers are not functional: %08x\n", val); 813 return (0); 814 } 815 816 static int 817 ata_intel_31244_ch_attach(device_t dev) 818 { 819 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 820 struct ata_channel *ch = device_get_softc(dev); 821 int i; 822 int ch_offset; 823 824 ata_pci_dmainit(dev); 825 826 ch_offset = 0x200 + ch->unit * 0x200; 827 828 for (i = ATA_DATA; i < ATA_MAX_RES; i++) 829 ch->r_io[i].res = ctlr->r_res2; 830 831 /* setup ATA registers */ 832 ch->r_io[ATA_DATA].offset = ch_offset + 0x00; 833 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06; 834 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08; 835 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c; 836 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; 837 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14; 838 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18; 839 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d; 840 ch->r_io[ATA_ERROR].offset = ch_offset + 0x04; 841 ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c; 842 ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28; 843 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29; 844 845 /* setup DMA registers */ 846 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100; 847 ch->r_io[ATA_SERROR].offset = ch_offset + 0x104; 848 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108; 849 850 /* setup SATA registers */ 851 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70; 852 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72; 853 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74; 854 855 ch->flags |= ATA_NO_SLAVE; 856 ch->flags |= ATA_SATA; 857 ata_pci_hw(dev); 858 ch->hw.status = ata_intel_31244_status; 859 ch->hw.tf_write = ata_intel_31244_tf_write; 860 861 /* enable PHY state change interrupt */ 862 ATA_OUTL(ctlr->r_res2, 0x4, 863 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3))); 864 return 0; 865 } 866 867 static int 868 ata_intel_31244_ch_detach(device_t dev) 869 { 870 871 ata_pci_dmafini(dev); 872 return (0); 873 } 874 875 static int 876 ata_intel_31244_status(device_t dev) 877 { 878 /* do we have any PHY events ? */ 879 ata_sata_phy_check_events(dev, -1); 880 881 /* any drive action to take care of ? */ 882 return ata_pci_status(dev); 883 } 884 885 static void 886 ata_intel_31244_tf_write(struct ata_request *request) 887 { 888 struct ata_channel *ch = device_get_softc(request->parent); 889 890 if (request->flags & ATA_R_48BIT) { 891 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature); 892 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count); 893 ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) | 894 (request->u.ata.lba & 0x00ff)); 895 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) | 896 ((request->u.ata.lba >> 8) & 0x00ff)); 897 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) | 898 ((request->u.ata.lba >> 16) & 0x00ff)); 899 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit)); 900 } 901 else { 902 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 903 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 904 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 905 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 906 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 907 ATA_IDX_OUTB(ch, ATA_DRIVE, 908 ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) | 909 ((request->u.ata.lba >> 24) & 0x0f)); 910 } 911 } 912 913 static void 914 ata_intel_31244_reset(device_t dev) 915 { 916 struct ata_channel *ch = device_get_softc(dev); 917 918 if (ata_sata_phy_reset(dev, -1, 1)) 919 ata_generic_reset(dev); 920 else 921 ch->devices = 0; 922 } 923 924 ATA_DECLARE_DRIVER(ata_intel); 925