1 /*- 2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/module.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/ata.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/malloc.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 #include <sys/sema.h> 41 #include <sys/taskqueue.h> 42 #include <vm/uma.h> 43 #include <machine/stdarg.h> 44 #include <machine/resource.h> 45 #include <machine/bus.h> 46 #include <sys/rman.h> 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcireg.h> 49 #include <dev/ata/ata-all.h> 50 #include <dev/ata/ata-pci.h> 51 #include <ata_if.h> 52 53 /* local prototypes */ 54 static int ata_intel_chipinit(device_t dev); 55 static int ata_intel_chipdeinit(device_t dev); 56 static int ata_intel_ch_attach(device_t dev); 57 static void ata_intel_reset(device_t dev); 58 static int ata_intel_old_setmode(device_t dev, int target, int mode); 59 static int ata_intel_new_setmode(device_t dev, int target, int mode); 60 static int ata_intel_sch_setmode(device_t dev, int target, int mode); 61 static int ata_intel_sata_getrev(device_t dev, int target); 62 static int ata_intel_sata_status(device_t dev); 63 static int ata_intel_sata_ahci_read(device_t dev, int port, 64 int reg, u_int32_t *result); 65 static int ata_intel_sata_cscr_read(device_t dev, int port, 66 int reg, u_int32_t *result); 67 static int ata_intel_sata_sidpr_read(device_t dev, int port, 68 int reg, u_int32_t *result); 69 static int ata_intel_sata_ahci_write(device_t dev, int port, 70 int reg, u_int32_t result); 71 static int ata_intel_sata_cscr_write(device_t dev, int port, 72 int reg, u_int32_t result); 73 static int ata_intel_sata_sidpr_write(device_t dev, int port, 74 int reg, u_int32_t result); 75 static int ata_intel_sata_sidpr_test(device_t dev); 76 static int ata_intel_31244_ch_attach(device_t dev); 77 static int ata_intel_31244_ch_detach(device_t dev); 78 static int ata_intel_31244_status(device_t dev); 79 static void ata_intel_31244_tf_write(struct ata_request *request); 80 static void ata_intel_31244_reset(device_t dev); 81 82 /* misc defines */ 83 #define INTEL_AHCI 1 84 #define INTEL_ICH5 2 85 #define INTEL_6CH 4 86 #define INTEL_6CH2 8 87 #define INTEL_ICH7 16 88 89 struct ata_intel_data { 90 struct mtx lock; 91 u_char smap[4]; 92 }; 93 94 #define ATA_INTEL_SMAP(ctlr, ch) \ 95 &((struct ata_intel_data *)((ctlr)->chipset_data))->smap[(ch)->unit * 2] 96 #define ATA_INTEL_LOCK(ctlr) \ 97 mtx_lock(&((struct ata_intel_data *)((ctlr)->chipset_data))->lock) 98 #define ATA_INTEL_UNLOCK(ctlr) \ 99 mtx_unlock(&((struct ata_intel_data *)((ctlr)->chipset_data))->lock) 100 101 /* 102 * Intel chipset support functions 103 */ 104 static int 105 ata_intel_probe(device_t dev) 106 { 107 struct ata_pci_controller *ctlr = device_get_softc(dev); 108 static const struct ata_chip_id ids[] = 109 {{ ATA_I82371FB, 0, 0, 2, ATA_WDMA2, "PIIX" }, 110 { ATA_I82371SB, 0, 0, 2, ATA_WDMA2, "PIIX3" }, 111 { ATA_I82371AB, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 112 { ATA_I82443MX, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 113 { ATA_I82451NX, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 114 { ATA_I82801AB, 0, 0, 2, ATA_UDMA2, "ICH0" }, 115 { ATA_I82801AA, 0, 0, 2, ATA_UDMA4, "ICH" }, 116 { ATA_I82372FB, 0, 0, 2, ATA_UDMA4, "ICH" }, 117 { ATA_I82801BA, 0, 0, 2, ATA_UDMA5, "ICH2" }, 118 { ATA_I82801BA_1, 0, 0, 2, ATA_UDMA5, "ICH2" }, 119 { ATA_I82801CA, 0, 0, 2, ATA_UDMA5, "ICH3" }, 120 { ATA_I82801CA_1, 0, 0, 2, ATA_UDMA5, "ICH3" }, 121 { ATA_I82801DB, 0, 0, 2, ATA_UDMA5, "ICH4" }, 122 { ATA_I82801DB_1, 0, 0, 2, ATA_UDMA5, "ICH4" }, 123 { ATA_I82801EB, 0, 0, 2, ATA_UDMA5, "ICH5" }, 124 { ATA_I82801EB_S1, 0, INTEL_ICH5, 2, ATA_SA150, "ICH5" }, 125 { ATA_I82801EB_R1, 0, INTEL_ICH5, 2, ATA_SA150, "ICH5" }, 126 { ATA_I6300ESB, 0, 0, 2, ATA_UDMA5, "6300ESB" }, 127 { ATA_I6300ESB_S1, 0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" }, 128 { ATA_I6300ESB_R1, 0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" }, 129 { ATA_I82801FB, 0, 0, 2, ATA_UDMA5, "ICH6" }, 130 { ATA_I82801FB_S1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6" }, 131 { ATA_I82801FB_R1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6" }, 132 { ATA_I82801FBM, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6M" }, 133 { ATA_I82801GB, 0, 0, 1, ATA_UDMA5, "ICH7" }, 134 { ATA_I82801GB_S1, 0, INTEL_ICH7, 0, ATA_SA300, "ICH7" }, 135 { ATA_I82801GB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" }, 136 { ATA_I82801GB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" }, 137 { ATA_I82801GBM_S1, 0, INTEL_ICH7, 0, ATA_SA150, "ICH7M" }, 138 { ATA_I82801GBM_R1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" }, 139 { ATA_I82801GBM_AH, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" }, 140 { ATA_I63XXESB2, 0, 0, 1, ATA_UDMA5, "63XXESB2" }, 141 { ATA_I63XXESB2_S1, 0, 0, 0, ATA_SA300, "63XXESB2" }, 142 { ATA_I63XXESB2_S2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 143 { ATA_I63XXESB2_R1, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 144 { ATA_I63XXESB2_R2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 145 { ATA_I82801HB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH8" }, 146 { ATA_I82801HB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH8" }, 147 { ATA_I82801HB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 148 { ATA_I82801HB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 149 { ATA_I82801HB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 150 { ATA_I82801HBM, 0, 0, 1, ATA_UDMA5, "ICH8M" }, 151 { ATA_I82801HBM_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH8M" }, 152 { ATA_I82801HBM_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" }, 153 { ATA_I82801HBM_S3, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" }, 154 { ATA_I82801IB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH9" }, 155 { ATA_I82801IB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9" }, 156 { ATA_I82801IB_S3, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9" }, 157 { ATA_I82801IB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 158 { ATA_I82801IB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 159 { ATA_I82801IB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 160 { ATA_I82801IBM_S1, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9M" }, 161 { ATA_I82801IBM_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9M" }, 162 { ATA_I82801IBM_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9M" }, 163 { ATA_I82801IBM_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9M" }, 164 { ATA_I82801JIB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, 165 { ATA_I82801JIB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 166 { ATA_I82801JIB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 167 { ATA_I82801JIB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, 168 { ATA_I82801JD_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, 169 { ATA_I82801JD_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 170 { ATA_I82801JD_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 171 { ATA_I82801JD_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, 172 { ATA_I82801JI_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, 173 { ATA_I82801JI_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 174 { ATA_I82801JI_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 175 { ATA_I82801JI_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, 176 { ATA_5Series_S1, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 177 { ATA_5Series_S2, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 178 { ATA_5Series_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 179 { ATA_5Series_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 180 { ATA_5Series_R1, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 181 { ATA_5Series_S3, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 182 { ATA_5Series_S4, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 183 { ATA_5Series_AH3, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 184 { ATA_5Series_R2, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 185 { ATA_5Series_S5, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 186 { ATA_5Series_S6, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 187 { ATA_5Series_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 188 { ATA_CPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Cougar Point" }, 189 { ATA_CPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Cougar Point" }, 190 { ATA_CPT_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, 191 { ATA_CPT_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, 192 { ATA_CPT_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, 193 { ATA_CPT_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, 194 { ATA_CPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" }, 195 { ATA_CPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" }, 196 { ATA_PBG_S1, 0, INTEL_6CH, 0, ATA_SA300, "Patsburg" }, 197 { ATA_PBG_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" }, 198 { ATA_PBG_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" }, 199 { ATA_PBG_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" }, 200 { ATA_PBG_R3, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" }, 201 { ATA_PBG_S2, 0, INTEL_6CH2, 0, ATA_SA300, "Patsburg" }, 202 { ATA_PPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Panther Point" }, 203 { ATA_PPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Panther Point" }, 204 { ATA_PPT_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 205 { ATA_PPT_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 206 { ATA_PPT_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 207 { ATA_PPT_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 208 { ATA_PPT_R3, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 209 { ATA_PPT_R4, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 210 { ATA_PPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Panther Point" }, 211 { ATA_PPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Panther Point" }, 212 { ATA_PPT_R5, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 213 { ATA_PPT_R6, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 214 { ATA_LPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Lynx Point" }, 215 { ATA_LPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Lynx Point" }, 216 { ATA_LPT_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, 217 { ATA_LPT_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, 218 { ATA_LPT_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, 219 { ATA_LPT_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, 220 { ATA_LPT_R3, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, 221 { ATA_LPT_R4, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, 222 { ATA_LPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point" }, 223 { ATA_LPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point" }, 224 { ATA_LPT_R5, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, 225 { ATA_LPT_R6, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, 226 { ATA_I31244, 0, 0, 2, ATA_SA150, "31244" }, 227 { ATA_ISCH, 0, 0, 1, ATA_UDMA5, "SCH" }, 228 { ATA_DH89XXCC, 0, INTEL_AHCI, 0, ATA_SA300, "DH89xxCC" }, 229 { 0, 0, 0, 0, 0, 0}}; 230 231 if (pci_get_vendor(dev) != ATA_INTEL_ID) 232 return ENXIO; 233 234 if (!(ctlr->chip = ata_match_chip(dev, ids))) 235 return ENXIO; 236 237 ata_set_desc(dev); 238 ctlr->chipinit = ata_intel_chipinit; 239 ctlr->chipdeinit = ata_intel_chipdeinit; 240 return (BUS_PROBE_DEFAULT); 241 } 242 243 static int 244 ata_intel_chipinit(device_t dev) 245 { 246 struct ata_pci_controller *ctlr = device_get_softc(dev); 247 struct ata_intel_data *data; 248 249 if (ata_setup_interrupt(dev, ata_generic_intr)) 250 return ENXIO; 251 252 data = malloc(sizeof(struct ata_intel_data), M_ATAPCI, M_WAITOK | M_ZERO); 253 mtx_init(&data->lock, "Intel SATA lock", NULL, MTX_DEF); 254 ctlr->chipset_data = (void *)data; 255 256 /* good old PIIX needs special treatment (not implemented) */ 257 if (ctlr->chip->chipid == ATA_I82371FB) { 258 ctlr->setmode = ata_intel_old_setmode; 259 } 260 261 /* the intel 31244 needs special care if in DPA mode */ 262 else if (ctlr->chip->chipid == ATA_I31244) { 263 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) { 264 ctlr->r_type2 = SYS_RES_MEMORY; 265 ctlr->r_rid2 = PCIR_BAR(0); 266 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 267 &ctlr->r_rid2, 268 RF_ACTIVE))) 269 return ENXIO; 270 ctlr->channels = 4; 271 ctlr->ch_attach = ata_intel_31244_ch_attach; 272 ctlr->ch_detach = ata_intel_31244_ch_detach; 273 ctlr->reset = ata_intel_31244_reset; 274 } 275 ctlr->setmode = ata_sata_setmode; 276 ctlr->getrev = ata_sata_getrev; 277 } 278 /* SCH */ 279 else if (ctlr->chip->chipid == ATA_ISCH) { 280 ctlr->channels = 1; 281 ctlr->ch_attach = ata_intel_ch_attach; 282 ctlr->ch_detach = ata_pci_ch_detach; 283 ctlr->setmode = ata_intel_sch_setmode; 284 } 285 /* non SATA intel chips goes here */ 286 else if (ctlr->chip->max_dma < ATA_SA150) { 287 ctlr->channels = ctlr->chip->cfg2; 288 ctlr->ch_attach = ata_intel_ch_attach; 289 ctlr->ch_detach = ata_pci_ch_detach; 290 ctlr->setmode = ata_intel_new_setmode; 291 } 292 293 /* SATA parts can be either compat or AHCI */ 294 else { 295 /* force all ports active "the legacy way" */ 296 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f, 2); 297 298 ctlr->ch_attach = ata_intel_ch_attach; 299 ctlr->ch_detach = ata_pci_ch_detach; 300 ctlr->reset = ata_intel_reset; 301 302 /* 303 * if we have AHCI capability and AHCI or RAID mode enabled 304 * in BIOS we try for AHCI mode 305 */ 306 if ((ctlr->chip->cfg1 & INTEL_AHCI) && 307 (pci_read_config(dev, 0x90, 1) & 0xc0) && 308 (ata_ahci_chipinit(dev) != ENXIO)) 309 return 0; 310 311 /* BAR(5) may point to SATA interface registers */ 312 if ((ctlr->chip->cfg1 & INTEL_ICH7)) { 313 ctlr->r_type2 = SYS_RES_MEMORY; 314 ctlr->r_rid2 = PCIR_BAR(5); 315 ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 316 &ctlr->r_rid2, RF_ACTIVE); 317 if (ctlr->r_res2 != NULL) { 318 /* Set SCRAE bit to enable registers access. */ 319 pci_write_config(dev, 0x94, 320 pci_read_config(dev, 0x94, 4) | (1 << 9), 4); 321 /* Set Ports Implemented register bits. */ 322 ATA_OUTL(ctlr->r_res2, 0x0C, 323 ATA_INL(ctlr->r_res2, 0x0C) | 0xf); 324 } 325 /* Skip BAR(5) on ICH8M Apples, system locks up on access. */ 326 } else if (ctlr->chip->chipid != ATA_I82801HBM_S1 || 327 pci_get_subvendor(dev) != 0x106b) { 328 ctlr->r_type2 = SYS_RES_IOPORT; 329 ctlr->r_rid2 = PCIR_BAR(5); 330 ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 331 &ctlr->r_rid2, RF_ACTIVE); 332 } 333 if (ctlr->r_res2 != NULL || 334 (ctlr->chip->cfg1 & INTEL_ICH5)) 335 ctlr->getrev = ata_intel_sata_getrev; 336 ctlr->setmode = ata_sata_setmode; 337 } 338 return 0; 339 } 340 341 static int 342 ata_intel_chipdeinit(device_t dev) 343 { 344 struct ata_pci_controller *ctlr = device_get_softc(dev); 345 struct ata_intel_data *data; 346 347 data = ctlr->chipset_data; 348 mtx_destroy(&data->lock); 349 free(data, M_ATAPCI); 350 ctlr->chipset_data = NULL; 351 return (0); 352 } 353 354 static int 355 ata_intel_ch_attach(device_t dev) 356 { 357 struct ata_pci_controller *ctlr; 358 struct ata_channel *ch; 359 u_char *smap; 360 u_int map; 361 362 /* setup the usual register normal pci style */ 363 if (ata_pci_ch_attach(dev)) 364 return (ENXIO); 365 366 ctlr = device_get_softc(device_get_parent(dev)); 367 ch = device_get_softc(dev); 368 369 /* if r_res2 is valid it points to SATA interface registers */ 370 if (ctlr->r_res2) { 371 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 372 ch->r_io[ATA_IDX_ADDR].offset = 0x00; 373 ch->r_io[ATA_IDX_DATA].res = ctlr->r_res2; 374 ch->r_io[ATA_IDX_DATA].offset = 0x04; 375 } 376 377 ch->flags |= ATA_ALWAYS_DMASTAT; 378 if (ctlr->chip->max_dma >= ATA_SA150) { 379 smap = ATA_INTEL_SMAP(ctlr, ch); 380 map = pci_read_config(device_get_parent(dev), 0x90, 1); 381 if (ctlr->chip->cfg1 & INTEL_ICH5) { 382 map &= 0x07; 383 if ((map & 0x04) == 0) { 384 ch->flags |= ATA_SATA; 385 ch->flags |= ATA_NO_SLAVE; 386 smap[0] = (map & 0x01) ^ ch->unit; 387 smap[1] = 0; 388 } else if ((map & 0x02) == 0 && ch->unit == 0) { 389 ch->flags |= ATA_SATA; 390 smap[0] = (map & 0x01) ? 1 : 0; 391 smap[1] = (map & 0x01) ? 0 : 1; 392 } else if ((map & 0x02) != 0 && ch->unit == 1) { 393 ch->flags |= ATA_SATA; 394 smap[0] = (map & 0x01) ? 1 : 0; 395 smap[1] = (map & 0x01) ? 0 : 1; 396 } 397 } else if (ctlr->chip->cfg1 & INTEL_6CH2) { 398 ch->flags |= ATA_SATA; 399 ch->flags |= ATA_NO_SLAVE; 400 smap[0] = (ch->unit == 0) ? 0 : 1; 401 smap[1] = 0; 402 } else { 403 map &= 0x03; 404 if (map == 0x00) { 405 ch->flags |= ATA_SATA; 406 smap[0] = (ch->unit == 0) ? 0 : 1; 407 smap[1] = (ch->unit == 0) ? 2 : 3; 408 } else if (map == 0x02 && ch->unit == 0) { 409 ch->flags |= ATA_SATA; 410 smap[0] = 0; 411 smap[1] = 2; 412 } else if (map == 0x01 && ch->unit == 1) { 413 ch->flags |= ATA_SATA; 414 smap[0] = 1; 415 smap[1] = 3; 416 } 417 } 418 if (ch->flags & ATA_SATA) { 419 if ((ctlr->chip->cfg1 & INTEL_ICH5)) { 420 ch->hw.pm_read = ata_intel_sata_cscr_read; 421 ch->hw.pm_write = ata_intel_sata_cscr_write; 422 } else if (ctlr->r_res2) { 423 if ((ctlr->chip->cfg1 & INTEL_ICH7)) { 424 ch->hw.pm_read = ata_intel_sata_ahci_read; 425 ch->hw.pm_write = ata_intel_sata_ahci_write; 426 } else if (ata_intel_sata_sidpr_test(dev)) { 427 ch->hw.pm_read = ata_intel_sata_sidpr_read; 428 ch->hw.pm_write = ata_intel_sata_sidpr_write; 429 }; 430 } 431 if (ch->hw.pm_write != NULL) { 432 ch->flags |= ATA_PERIODIC_POLL; 433 ch->hw.status = ata_intel_sata_status; 434 ata_sata_scr_write(ch, 0, 435 ATA_SERROR, 0xffffffff); 436 if ((ch->flags & ATA_NO_SLAVE) == 0) { 437 ata_sata_scr_write(ch, 1, 438 ATA_SERROR, 0xffffffff); 439 } 440 } 441 } else 442 ctlr->setmode = ata_intel_new_setmode; 443 } else if (ctlr->chip->chipid != ATA_ISCH) 444 ch->flags |= ATA_CHECKS_CABLE; 445 return (0); 446 } 447 448 static void 449 ata_intel_reset(device_t dev) 450 { 451 device_t parent = device_get_parent(dev); 452 struct ata_pci_controller *ctlr = device_get_softc(parent); 453 struct ata_channel *ch = device_get_softc(dev); 454 int mask, pshift, timeout, devs; 455 u_char *smap; 456 uint16_t pcs; 457 458 /* In combined mode, skip SATA stuff for PATA channel. */ 459 if ((ch->flags & ATA_SATA) == 0) 460 return (ata_generic_reset(dev)); 461 462 /* Do hard-reset on respective SATA ports. */ 463 smap = ATA_INTEL_SMAP(ctlr, ch); 464 mask = 1 << smap[0]; 465 if ((ch->flags & ATA_NO_SLAVE) == 0) 466 mask |= (1 << smap[1]); 467 pci_write_config(parent, 0x92, 468 pci_read_config(parent, 0x92, 2) & ~mask, 2); 469 DELAY(10); 470 pci_write_config(parent, 0x92, 471 pci_read_config(parent, 0x92, 2) | mask, 2); 472 473 /* Wait up to 1 sec for "connect well". */ 474 if (ctlr->chip->cfg1 & (INTEL_6CH | INTEL_6CH2)) 475 pshift = 8; 476 else 477 pshift = 4; 478 for (timeout = 0; timeout < 100 ; timeout++) { 479 pcs = (pci_read_config(parent, 0x92, 2) >> pshift) & mask; 480 if ((pcs == mask) && (ATA_IDX_INB(ch, ATA_STATUS) != 0xff)) 481 break; 482 ata_udelay(10000); 483 } 484 485 if (bootverbose) 486 device_printf(dev, "SATA reset: ports status=0x%02x\n", pcs); 487 /* If any device found, do soft-reset. */ 488 if (ch->hw.pm_read != NULL) { 489 devs = ata_sata_phy_reset(dev, 0, 2) ? ATA_ATA_MASTER : 0; 490 if ((ch->flags & ATA_NO_SLAVE) == 0) 491 devs |= ata_sata_phy_reset(dev, 1, 2) ? 492 ATA_ATA_SLAVE : 0; 493 } else { 494 devs = (pcs & (1 << smap[0])) ? ATA_ATA_MASTER : 0; 495 if ((ch->flags & ATA_NO_SLAVE) == 0) 496 devs |= (pcs & (1 << smap[1])) ? 497 ATA_ATA_SLAVE : 0; 498 } 499 if (devs) { 500 ata_generic_reset(dev); 501 /* Reset may give fake slave when only ATAPI master present. */ 502 ch->devices &= (devs | (devs * ATA_ATAPI_MASTER)); 503 } else 504 ch->devices = 0; 505 } 506 507 static int 508 ata_intel_old_setmode(device_t dev, int target, int mode) 509 { 510 device_t parent = device_get_parent(dev); 511 struct ata_pci_controller *ctlr = device_get_softc(parent); 512 513 mode = min(mode, ctlr->chip->max_dma); 514 return (mode); 515 } 516 517 static int 518 ata_intel_new_setmode(device_t dev, int target, int mode) 519 { 520 device_t parent = device_get_parent(dev); 521 struct ata_pci_controller *ctlr = device_get_softc(parent); 522 struct ata_channel *ch = device_get_softc(dev); 523 int devno = (ch->unit << 1) + target; 524 int piomode; 525 u_int32_t reg40 = pci_read_config(parent, 0x40, 4); 526 u_int8_t reg44 = pci_read_config(parent, 0x44, 1); 527 u_int8_t reg48 = pci_read_config(parent, 0x48, 1); 528 u_int16_t reg4a = pci_read_config(parent, 0x4a, 2); 529 u_int16_t reg54 = pci_read_config(parent, 0x54, 2); 530 u_int32_t mask40 = 0, new40 = 0; 531 u_int8_t mask44 = 0, new44 = 0; 532 static const uint8_t timings[] = 533 { 0x00, 0x00, 0x10, 0x21, 0x23, 0x00, 0x21, 0x23 }; 534 static const uint8_t utimings[] = 535 { 0x00, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02 }; 536 537 /* In combined mode, skip PATA stuff for SATA channel. */ 538 if (ch->flags & ATA_SATA) 539 return (ata_sata_setmode(dev, target, mode)); 540 541 mode = min(mode, ctlr->chip->max_dma); 542 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 543 !(reg54 & (0x10 << devno))) { 544 ata_print_cable(dev, "controller"); 545 mode = ATA_UDMA2; 546 } 547 /* Enable/disable UDMA and set timings. */ 548 if (mode >= ATA_UDMA0) { 549 pci_write_config(parent, 0x48, reg48 | (0x0001 << devno), 2); 550 pci_write_config(parent, 0x4a, 551 (reg4a & ~(0x3 << (devno << 2))) | 552 (utimings[mode & ATA_MODE_MASK] << (devno<<2)), 2); 553 piomode = ATA_PIO4; 554 } else { 555 pci_write_config(parent, 0x48, reg48 & ~(0x0001 << devno), 2); 556 pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (devno << 2))),2); 557 piomode = mode; 558 } 559 reg54 |= 0x0400; 560 /* Set UDMA reference clock (33/66/133MHz). */ 561 reg54 &= ~(0x1001 << devno); 562 if (mode >= ATA_UDMA5) 563 reg54 |= (0x1000 << devno); 564 else if (mode >= ATA_UDMA3) 565 reg54 |= (0x1 << devno); 566 pci_write_config(parent, 0x54, reg54, 2); 567 /* Allow PIO/WDMA timing controls. */ 568 reg40 &= ~0x00ff00ff; 569 reg40 |= 0x40774077; 570 /* Set PIO/WDMA timings. */ 571 if (target == 0) { 572 mask40 = 0x3300; 573 new40 = timings[ata_mode2idx(piomode)] << 8; 574 } else { 575 mask44 = 0x0f; 576 new44 = ((timings[ata_mode2idx(piomode)] & 0x30) >> 2) | 577 (timings[ata_mode2idx(piomode)] & 0x03); 578 } 579 if (ch->unit) { 580 mask40 <<= 16; 581 new40 <<= 16; 582 mask44 <<= 4; 583 new44 <<= 4; 584 } 585 pci_write_config(parent, 0x40, (reg40 & ~mask40) | new40, 4); 586 pci_write_config(parent, 0x44, (reg44 & ~mask44) | new44, 1); 587 return (mode); 588 } 589 590 static int 591 ata_intel_sch_setmode(device_t dev, int target, int mode) 592 { 593 device_t parent = device_get_parent(dev); 594 struct ata_pci_controller *ctlr = device_get_softc(parent); 595 u_int8_t dtim = 0x80 + (target << 2); 596 u_int32_t tim = pci_read_config(parent, dtim, 4); 597 int piomode; 598 599 mode = min(mode, ctlr->chip->max_dma); 600 if (mode >= ATA_UDMA0) { 601 tim |= (0x1 << 31); 602 tim &= ~(0x7 << 16); 603 tim |= ((mode & ATA_MODE_MASK) << 16); 604 piomode = ATA_PIO4; 605 } else if (mode >= ATA_WDMA0) { 606 tim &= ~(0x1 << 31); 607 tim &= ~(0x3 << 8); 608 tim |= ((mode & ATA_MODE_MASK) << 8); 609 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 : 610 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4; 611 } else 612 piomode = mode; 613 tim &= ~(0x7); 614 tim |= (piomode & 0x7); 615 pci_write_config(parent, dtim, tim, 4); 616 return (mode); 617 } 618 619 static int 620 ata_intel_sata_getrev(device_t dev, int target) 621 { 622 struct ata_channel *ch = device_get_softc(dev); 623 uint32_t status; 624 625 if (ata_sata_scr_read(ch, target, ATA_SSTATUS, &status) == 0) 626 return ((status & 0x0f0) >> 4); 627 return (0xff); 628 } 629 630 static int 631 ata_intel_sata_status(device_t dev) 632 { 633 struct ata_channel *ch = device_get_softc(dev); 634 635 ata_sata_phy_check_events(dev, 0); 636 if ((ch->flags & ATA_NO_SLAVE) == 0) 637 ata_sata_phy_check_events(dev, 1); 638 639 return ata_pci_status(dev); 640 } 641 642 static int 643 ata_intel_sata_ahci_read(device_t dev, int port, int reg, u_int32_t *result) 644 { 645 struct ata_pci_controller *ctlr; 646 struct ata_channel *ch; 647 device_t parent; 648 u_char *smap; 649 int offset; 650 651 parent = device_get_parent(dev); 652 ctlr = device_get_softc(parent); 653 ch = device_get_softc(dev); 654 port = (port == 1) ? 1 : 0; 655 smap = ATA_INTEL_SMAP(ctlr, ch); 656 offset = 0x100 + smap[port] * 0x80; 657 switch (reg) { 658 case ATA_SSTATUS: 659 reg = 0x28; 660 break; 661 case ATA_SCONTROL: 662 reg = 0x2c; 663 break; 664 case ATA_SERROR: 665 reg = 0x30; 666 break; 667 default: 668 return (EINVAL); 669 } 670 *result = ATA_INL(ctlr->r_res2, offset + reg); 671 return (0); 672 } 673 674 static int 675 ata_intel_sata_cscr_read(device_t dev, int port, int reg, u_int32_t *result) 676 { 677 struct ata_pci_controller *ctlr; 678 struct ata_channel *ch; 679 device_t parent; 680 u_char *smap; 681 682 parent = device_get_parent(dev); 683 ctlr = device_get_softc(parent); 684 ch = device_get_softc(dev); 685 smap = ATA_INTEL_SMAP(ctlr, ch); 686 port = (port == 1) ? 1 : 0; 687 switch (reg) { 688 case ATA_SSTATUS: 689 reg = 0; 690 break; 691 case ATA_SERROR: 692 reg = 1; 693 break; 694 case ATA_SCONTROL: 695 reg = 2; 696 break; 697 default: 698 return (EINVAL); 699 } 700 ATA_INTEL_LOCK(ctlr); 701 pci_write_config(parent, 0xa0, 702 0x50 + smap[port] * 0x10 + reg * 4, 4); 703 *result = pci_read_config(parent, 0xa4, 4); 704 ATA_INTEL_UNLOCK(ctlr); 705 return (0); 706 } 707 708 static int 709 ata_intel_sata_sidpr_read(device_t dev, int port, int reg, u_int32_t *result) 710 { 711 struct ata_pci_controller *ctlr; 712 struct ata_channel *ch; 713 device_t parent; 714 715 parent = device_get_parent(dev); 716 ctlr = device_get_softc(parent); 717 ch = device_get_softc(dev); 718 port = (port == 1) ? 1 : 0; 719 switch (reg) { 720 case ATA_SSTATUS: 721 reg = 0; 722 break; 723 case ATA_SCONTROL: 724 reg = 1; 725 break; 726 case ATA_SERROR: 727 reg = 2; 728 break; 729 default: 730 return (EINVAL); 731 } 732 ATA_INTEL_LOCK(ctlr); 733 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, ((ch->unit * 2 + port) << 8) + reg); 734 *result = ATA_IDX_INL(ch, ATA_IDX_DATA); 735 ATA_INTEL_UNLOCK(ctlr); 736 return (0); 737 } 738 739 static int 740 ata_intel_sata_ahci_write(device_t dev, int port, int reg, u_int32_t value) 741 { 742 struct ata_pci_controller *ctlr; 743 struct ata_channel *ch; 744 device_t parent; 745 u_char *smap; 746 int offset; 747 748 parent = device_get_parent(dev); 749 ctlr = device_get_softc(parent); 750 ch = device_get_softc(dev); 751 port = (port == 1) ? 1 : 0; 752 smap = ATA_INTEL_SMAP(ctlr, ch); 753 offset = 0x100 + smap[port] * 0x80; 754 switch (reg) { 755 case ATA_SSTATUS: 756 reg = 0x28; 757 break; 758 case ATA_SCONTROL: 759 reg = 0x2c; 760 break; 761 case ATA_SERROR: 762 reg = 0x30; 763 break; 764 default: 765 return (EINVAL); 766 } 767 ATA_OUTL(ctlr->r_res2, offset + reg, value); 768 return (0); 769 } 770 771 static int 772 ata_intel_sata_cscr_write(device_t dev, int port, int reg, u_int32_t value) 773 { 774 struct ata_pci_controller *ctlr; 775 struct ata_channel *ch; 776 device_t parent; 777 u_char *smap; 778 779 parent = device_get_parent(dev); 780 ctlr = device_get_softc(parent); 781 ch = device_get_softc(dev); 782 smap = ATA_INTEL_SMAP(ctlr, ch); 783 port = (port == 1) ? 1 : 0; 784 switch (reg) { 785 case ATA_SSTATUS: 786 reg = 0; 787 break; 788 case ATA_SERROR: 789 reg = 1; 790 break; 791 case ATA_SCONTROL: 792 reg = 2; 793 break; 794 default: 795 return (EINVAL); 796 } 797 ATA_INTEL_LOCK(ctlr); 798 pci_write_config(parent, 0xa0, 799 0x50 + smap[port] * 0x10 + reg * 4, 4); 800 pci_write_config(parent, 0xa4, value, 4); 801 ATA_INTEL_UNLOCK(ctlr); 802 return (0); 803 } 804 805 static int 806 ata_intel_sata_sidpr_write(device_t dev, int port, int reg, u_int32_t value) 807 { 808 struct ata_pci_controller *ctlr; 809 struct ata_channel *ch; 810 device_t parent; 811 812 parent = device_get_parent(dev); 813 ctlr = device_get_softc(parent); 814 ch = device_get_softc(dev); 815 port = (port == 1) ? 1 : 0; 816 switch (reg) { 817 case ATA_SSTATUS: 818 reg = 0; 819 break; 820 case ATA_SCONTROL: 821 reg = 1; 822 break; 823 case ATA_SERROR: 824 reg = 2; 825 break; 826 default: 827 return (EINVAL); 828 } 829 ATA_INTEL_LOCK(ctlr); 830 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, ((ch->unit * 2 + port) << 8) + reg); 831 ATA_IDX_OUTL(ch, ATA_IDX_DATA, value); 832 ATA_INTEL_UNLOCK(ctlr); 833 return (0); 834 } 835 836 static int 837 ata_intel_sata_sidpr_test(device_t dev) 838 { 839 struct ata_channel *ch = device_get_softc(dev); 840 int port; 841 uint32_t val; 842 843 port = (ch->flags & ATA_NO_SLAVE) ? 0 : 1; 844 for (; port >= 0; port--) { 845 ata_intel_sata_sidpr_read(dev, port, ATA_SCONTROL, &val); 846 if ((val & ATA_SC_IPM_MASK) == 847 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER)) 848 return (1); 849 val |= ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER; 850 ata_intel_sata_sidpr_write(dev, port, ATA_SCONTROL, val); 851 ata_intel_sata_sidpr_read(dev, port, ATA_SCONTROL, &val); 852 if ((val & ATA_SC_IPM_MASK) == 853 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER)) 854 return (1); 855 } 856 if (bootverbose) 857 device_printf(dev, 858 "SControl registers are not functional: %08x\n", val); 859 return (0); 860 } 861 862 static int 863 ata_intel_31244_ch_attach(device_t dev) 864 { 865 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 866 struct ata_channel *ch = device_get_softc(dev); 867 int i; 868 int ch_offset; 869 870 ata_pci_dmainit(dev); 871 872 ch_offset = 0x200 + ch->unit * 0x200; 873 874 for (i = ATA_DATA; i < ATA_MAX_RES; i++) 875 ch->r_io[i].res = ctlr->r_res2; 876 877 /* setup ATA registers */ 878 ch->r_io[ATA_DATA].offset = ch_offset + 0x00; 879 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06; 880 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08; 881 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c; 882 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; 883 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14; 884 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18; 885 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d; 886 ch->r_io[ATA_ERROR].offset = ch_offset + 0x04; 887 ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c; 888 ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28; 889 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29; 890 891 /* setup DMA registers */ 892 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100; 893 ch->r_io[ATA_SERROR].offset = ch_offset + 0x104; 894 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108; 895 896 /* setup SATA registers */ 897 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70; 898 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72; 899 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74; 900 901 ch->flags |= ATA_NO_SLAVE; 902 ch->flags |= ATA_SATA; 903 ata_pci_hw(dev); 904 ch->hw.status = ata_intel_31244_status; 905 ch->hw.tf_write = ata_intel_31244_tf_write; 906 907 /* enable PHY state change interrupt */ 908 ATA_OUTL(ctlr->r_res2, 0x4, 909 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3))); 910 return 0; 911 } 912 913 static int 914 ata_intel_31244_ch_detach(device_t dev) 915 { 916 917 ata_pci_dmafini(dev); 918 return (0); 919 } 920 921 static int 922 ata_intel_31244_status(device_t dev) 923 { 924 /* do we have any PHY events ? */ 925 ata_sata_phy_check_events(dev, -1); 926 927 /* any drive action to take care of ? */ 928 return ata_pci_status(dev); 929 } 930 931 static void 932 ata_intel_31244_tf_write(struct ata_request *request) 933 { 934 struct ata_channel *ch = device_get_softc(request->parent); 935 936 if (request->flags & ATA_R_48BIT) { 937 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature); 938 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count); 939 ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) | 940 (request->u.ata.lba & 0x00ff)); 941 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) | 942 ((request->u.ata.lba >> 8) & 0x00ff)); 943 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) | 944 ((request->u.ata.lba >> 16) & 0x00ff)); 945 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit)); 946 } 947 else { 948 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 949 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 950 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 951 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 952 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 953 ATA_IDX_OUTB(ch, ATA_DRIVE, 954 ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) | 955 ((request->u.ata.lba >> 24) & 0x0f)); 956 } 957 } 958 959 static void 960 ata_intel_31244_reset(device_t dev) 961 { 962 struct ata_channel *ch = device_get_softc(dev); 963 964 if (ata_sata_phy_reset(dev, -1, 1)) 965 ata_generic_reset(dev); 966 else 967 ch->devices = 0; 968 } 969 970 ATA_DECLARE_DRIVER(ata_intel); 971 MODULE_DEPEND(ata_intel, ata_ahci, 1, 1, 1); 972