1 /*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ata.h" 31 #include <sys/param.h> 32 #include <sys/module.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/ata.h> 36 #include <sys/bus.h> 37 #include <sys/endian.h> 38 #include <sys/malloc.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/sema.h> 42 #include <sys/taskqueue.h> 43 #include <vm/uma.h> 44 #include <machine/stdarg.h> 45 #include <machine/resource.h> 46 #include <machine/bus.h> 47 #include <sys/rman.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/ata/ata-all.h> 51 #include <dev/ata/ata-pci.h> 52 #include <ata_if.h> 53 54 /* local prototypes */ 55 static int ata_intel_chipinit(device_t dev); 56 static int ata_intel_ch_attach(device_t dev); 57 static void ata_intel_reset(device_t dev); 58 static int ata_intel_old_setmode(device_t dev, int target, int mode); 59 static int ata_intel_new_setmode(device_t dev, int target, int mode); 60 static int ata_intel_sata_getrev(device_t dev, int target); 61 static int ata_intel_31244_ch_attach(device_t dev); 62 static int ata_intel_31244_ch_detach(device_t dev); 63 static int ata_intel_31244_status(device_t dev); 64 static void ata_intel_31244_tf_write(struct ata_request *request); 65 static void ata_intel_31244_reset(device_t dev); 66 67 /* misc defines */ 68 #define INTEL_AHCI 1 69 70 71 /* 72 * Intel chipset support functions 73 */ 74 static int 75 ata_intel_probe(device_t dev) 76 { 77 struct ata_pci_controller *ctlr = device_get_softc(dev); 78 static struct ata_chip_id ids[] = 79 {{ ATA_I82371FB, 0, 0, 2, ATA_WDMA2, "PIIX" }, 80 { ATA_I82371SB, 0, 0, 2, ATA_WDMA2, "PIIX3" }, 81 { ATA_I82371AB, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 82 { ATA_I82443MX, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 83 { ATA_I82451NX, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 84 { ATA_I82801AB, 0, 0, 2, ATA_UDMA2, "ICH0" }, 85 { ATA_I82801AA, 0, 0, 2, ATA_UDMA4, "ICH" }, 86 { ATA_I82372FB, 0, 0, 2, ATA_UDMA4, "ICH" }, 87 { ATA_I82801BA, 0, 0, 2, ATA_UDMA5, "ICH2" }, 88 { ATA_I82801BA_1, 0, 0, 2, ATA_UDMA5, "ICH2" }, 89 { ATA_I82801CA, 0, 0, 2, ATA_UDMA5, "ICH3" }, 90 { ATA_I82801CA_1, 0, 0, 2, ATA_UDMA5, "ICH3" }, 91 { ATA_I82801DB, 0, 0, 2, ATA_UDMA5, "ICH4" }, 92 { ATA_I82801DB_1, 0, 0, 2, ATA_UDMA5, "ICH4" }, 93 { ATA_I82801EB, 0, 0, 2, ATA_UDMA5, "ICH5" }, 94 { ATA_I82801EB_S1, 0, 0, 2, ATA_SA150, "ICH5" }, 95 { ATA_I82801EB_R1, 0, 0, 2, ATA_SA150, "ICH5" }, 96 { ATA_I6300ESB, 0, 0, 2, ATA_UDMA5, "6300ESB" }, 97 { ATA_I6300ESB_S1, 0, 0, 2, ATA_SA150, "6300ESB" }, 98 { ATA_I6300ESB_R1, 0, 0, 2, ATA_SA150, "6300ESB" }, 99 { ATA_I82801FB, 0, 0, 2, ATA_UDMA5, "ICH6" }, 100 { ATA_I82801FB_S1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6" }, 101 { ATA_I82801FB_R1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6" }, 102 { ATA_I82801FBM, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6M" }, 103 { ATA_I82801GB, 0, 0, 1, ATA_UDMA5, "ICH7" }, 104 { ATA_I82801GB_S1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" }, 105 { ATA_I82801GB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" }, 106 { ATA_I82801GB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" }, 107 { ATA_I82801GBM_S1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" }, 108 { ATA_I82801GBM_R1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" }, 109 { ATA_I82801GBM_AH, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" }, 110 { ATA_I63XXESB2, 0, 0, 1, ATA_UDMA5, "63XXESB2" }, 111 { ATA_I63XXESB2_S1, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 112 { ATA_I63XXESB2_S2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 113 { ATA_I63XXESB2_R1, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 114 { ATA_I63XXESB2_R2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 115 { ATA_I82801HB_S1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 116 { ATA_I82801HB_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 117 { ATA_I82801HB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 118 { ATA_I82801HB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 119 { ATA_I82801HB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 120 { ATA_I82801HBM, 0, 0, 1, ATA_UDMA5, "ICH8M" }, 121 { ATA_I82801HBM_S1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" }, 122 { ATA_I82801HBM_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" }, 123 { ATA_I82801HBM_S3, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" }, 124 { ATA_I82801IB_S1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 125 { ATA_I82801IB_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 126 { ATA_I82801IB_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 127 { ATA_I82801IB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 128 { ATA_I82801IB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 129 { ATA_I82801IB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 130 { ATA_I82801JIB_S1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 131 { ATA_I82801JIB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 132 { ATA_I82801JIB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 133 { ATA_I82801JIB_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 134 { ATA_I82801JD_S1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 135 { ATA_I82801JD_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 136 { ATA_I82801JD_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 137 { ATA_I82801JD_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 138 { ATA_I82801JI_S1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 139 { ATA_I82801JI_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 140 { ATA_I82801JI_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 141 { ATA_I82801JI_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 142 { ATA_I31244, 0, 0, 2, ATA_SA150, "31244" }, 143 { 0, 0, 0, 0, 0, 0}}; 144 145 if (pci_get_vendor(dev) != ATA_INTEL_ID) 146 return ENXIO; 147 148 if (!(ctlr->chip = ata_match_chip(dev, ids))) 149 return ENXIO; 150 151 ata_set_desc(dev); 152 ctlr->chipinit = ata_intel_chipinit; 153 return (BUS_PROBE_DEFAULT); 154 } 155 156 static int 157 ata_intel_chipinit(device_t dev) 158 { 159 struct ata_pci_controller *ctlr = device_get_softc(dev); 160 161 if (ata_setup_interrupt(dev, ata_generic_intr)) 162 return ENXIO; 163 164 /* good old PIIX needs special treatment (not implemented) */ 165 if (ctlr->chip->chipid == ATA_I82371FB) { 166 ctlr->setmode = ata_intel_old_setmode; 167 } 168 169 /* the intel 31244 needs special care if in DPA mode */ 170 else if (ctlr->chip->chipid == ATA_I31244) { 171 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) { 172 ctlr->r_type2 = SYS_RES_MEMORY; 173 ctlr->r_rid2 = PCIR_BAR(0); 174 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 175 &ctlr->r_rid2, 176 RF_ACTIVE))) 177 return ENXIO; 178 ctlr->channels = 4; 179 ctlr->ch_attach = ata_intel_31244_ch_attach; 180 ctlr->ch_detach = ata_intel_31244_ch_detach; 181 ctlr->reset = ata_intel_31244_reset; 182 } 183 ctlr->setmode = ata_sata_setmode; 184 ctlr->getrev = ata_sata_getrev; 185 } 186 187 /* non SATA intel chips goes here */ 188 else if (ctlr->chip->max_dma < ATA_SA150) { 189 ctlr->channels = ctlr->chip->cfg2; 190 ctlr->ch_attach = ata_intel_ch_attach; 191 ctlr->ch_detach = ata_pci_ch_detach; 192 ctlr->setmode = ata_intel_new_setmode; 193 } 194 195 /* SATA parts can be either compat or AHCI */ 196 else { 197 /* force all ports active "the legacy way" */ 198 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f, 2); 199 200 ctlr->ch_attach = ata_intel_ch_attach; 201 ctlr->ch_detach = ata_pci_ch_detach; 202 ctlr->reset = ata_intel_reset; 203 204 /* 205 * if we have AHCI capability and AHCI or RAID mode enabled 206 * in BIOS we try for AHCI mode 207 */ 208 if ((ctlr->chip->cfg1 == INTEL_AHCI) && 209 (pci_read_config(dev, 0x90, 1) & 0xc0) && 210 (ata_ahci_chipinit(dev) != ENXIO)) 211 return 0; 212 213 /* if BAR(5) is IO it should point to SATA interface registers */ 214 ctlr->r_type2 = SYS_RES_IOPORT; 215 ctlr->r_rid2 = PCIR_BAR(5); 216 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 217 &ctlr->r_rid2, RF_ACTIVE))) 218 ctlr->getrev = ata_intel_sata_getrev; 219 ctlr->setmode = ata_sata_setmode; 220 } 221 return 0; 222 } 223 224 static int 225 ata_intel_ch_attach(device_t dev) 226 { 227 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 228 struct ata_channel *ch = device_get_softc(dev); 229 230 /* setup the usual register normal pci style */ 231 if (ata_pci_ch_attach(dev)) 232 return ENXIO; 233 234 /* if r_res2 is valid it points to SATA interface registers */ 235 if (ctlr->r_res2) { 236 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 237 ch->r_io[ATA_IDX_ADDR].offset = 0x00; 238 ch->r_io[ATA_IDX_DATA].res = ctlr->r_res2; 239 ch->r_io[ATA_IDX_DATA].offset = 0x04; 240 } 241 242 ch->flags |= ATA_ALWAYS_DMASTAT; 243 if (ctlr->chip->max_dma >= ATA_SA150) { 244 if (ctlr->chip->cfg1 == 0 && 245 (pci_read_config(device_get_parent(dev), 0x90, 1) & 0x04) == 0) 246 ch->flags |= ATA_NO_SLAVE; 247 ch->flags |= ATA_SATA; 248 } else 249 ch->flags |= ATA_CHECKS_CABLE; 250 return 0; 251 } 252 253 static void 254 ata_intel_reset(device_t dev) 255 { 256 device_t parent = device_get_parent(dev); 257 struct ata_pci_controller *ctlr = device_get_softc(parent); 258 struct ata_channel *ch = device_get_softc(dev); 259 int mask, timeout; 260 261 /* ICH6 & ICH7 in compat mode has 4 SATA ports as master/slave on 2 ch's */ 262 if (ctlr->chip->cfg1) { 263 mask = (0x0005 << ch->unit); 264 } 265 else { 266 /* ICH5 in compat mode has SATA ports as master/slave on 1 channel */ 267 if (pci_read_config(parent, 0x90, 1) & 0x04) 268 mask = 0x0003; 269 else 270 mask = (0x0001 << ch->unit); 271 } 272 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) & ~mask, 2); 273 DELAY(10); 274 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) | mask, 2); 275 276 /* wait up to 1 sec for "connect well" */ 277 for (timeout = 0; timeout < 100 ; timeout++) { 278 if (((pci_read_config(parent, 0x92, 2) & (mask << 4)) == (mask << 4)) && 279 (ATA_IDX_INB(ch, ATA_STATUS) != 0xff)) 280 break; 281 ata_udelay(10000); 282 } 283 ata_generic_reset(dev); 284 } 285 286 static int 287 ata_intel_old_setmode(device_t dev, int target, int mode) 288 { 289 device_t parent = device_get_parent(dev); 290 struct ata_pci_controller *ctlr = device_get_softc(parent); 291 292 mode = min(mode, ctlr->chip->max_dma); 293 return (mode); 294 } 295 296 static int 297 ata_intel_new_setmode(device_t dev, int target, int mode) 298 { 299 device_t parent = device_get_parent(dev); 300 struct ata_pci_controller *ctlr = device_get_softc(parent); 301 struct ata_channel *ch = device_get_softc(dev); 302 int devno = (ch->unit << 1) + target; 303 int piomode; 304 u_int32_t reg40 = pci_read_config(parent, 0x40, 4); 305 u_int8_t reg44 = pci_read_config(parent, 0x44, 1); 306 u_int8_t reg48 = pci_read_config(parent, 0x48, 1); 307 u_int16_t reg4a = pci_read_config(parent, 0x4a, 2); 308 u_int16_t reg54 = pci_read_config(parent, 0x54, 2); 309 u_int32_t mask40 = 0, new40 = 0; 310 u_int8_t mask44 = 0, new44 = 0; 311 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x00, 0x21, 0x23 }; 312 u_int8_t utimings[] = { 0x00, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02 }; 313 314 mode = min(mode, ctlr->chip->max_dma); 315 if (mode > ATA_UDMA2 && !(reg54 & (0x10 << devno))) { 316 ata_print_cable(dev, "controller"); 317 mode = ATA_UDMA2; 318 } 319 /* Enable/disable UDMA and set timings. */ 320 if (mode >= ATA_UDMA0) { 321 pci_write_config(parent, 0x48, reg48 | (0x0001 << devno), 2); 322 pci_write_config(parent, 0x4a, 323 (reg4a & ~(0x3 << (devno << 2))) | 324 (utimings[mode & ATA_MODE_MASK] << (devno<<2)), 2); 325 piomode = ATA_PIO4; 326 } else { 327 pci_write_config(parent, 0x48, reg48 & ~(0x0001 << devno), 2); 328 pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (devno << 2))),2); 329 piomode = mode; 330 } 331 reg54 |= 0x0400; 332 /* Set UDMA reference clock (33/66/133MHz). */ 333 reg54 &= ~(0x1001 << devno); 334 if (mode >= ATA_UDMA5) 335 reg54 |= (0x1000 << devno); 336 else if (mode >= ATA_UDMA3) 337 reg54 |= (0x1 << devno); 338 pci_write_config(parent, 0x54, reg54, 2); 339 /* Allow PIO/WDMA timing controls. */ 340 reg40 &= ~0x00ff00ff; 341 reg40 |= 0x40774077; 342 /* Set PIO/WDMA timings. */ 343 if (target == 0) { 344 mask40 = 0x3300; 345 new40 = timings[ata_mode2idx(piomode)] << 8; 346 } else { 347 mask44 = 0x0f; 348 new44 = ((timings[ata_mode2idx(piomode)] & 0x30) >> 2) | 349 (timings[ata_mode2idx(piomode)] & 0x03); 350 } 351 if (ch->unit) { 352 mask40 <<= 16; 353 new40 <<= 16; 354 mask44 <<= 4; 355 new44 <<= 4; 356 } 357 pci_write_config(parent, 0x40, (reg40 & ~mask40) | new40, 4); 358 pci_write_config(parent, 0x44, (reg44 & ~mask44) | new44, 1); 359 return (mode); 360 } 361 362 static int 363 ata_intel_sata_getrev(device_t dev, int target) 364 { 365 struct ata_channel *ch = device_get_softc(dev); 366 int devno = (ch->unit << 1) + target; 367 368 /* set ATA_SSTATUS register offset */ 369 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, devno * 0x100); 370 /* query SATA STATUS for the speed */ 371 return ((ATA_IDX_INL(ch, ATA_IDX_DATA) & 0x0f0) >> 4); 372 } 373 374 static int 375 ata_intel_31244_ch_attach(device_t dev) 376 { 377 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 378 struct ata_channel *ch = device_get_softc(dev); 379 int i; 380 int ch_offset; 381 382 ata_pci_dmainit(dev); 383 384 ch_offset = 0x200 + ch->unit * 0x200; 385 386 for (i = ATA_DATA; i < ATA_MAX_RES; i++) 387 ch->r_io[i].res = ctlr->r_res2; 388 389 /* setup ATA registers */ 390 ch->r_io[ATA_DATA].offset = ch_offset + 0x00; 391 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06; 392 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08; 393 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c; 394 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; 395 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14; 396 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18; 397 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d; 398 ch->r_io[ATA_ERROR].offset = ch_offset + 0x04; 399 ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c; 400 ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28; 401 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29; 402 403 /* setup DMA registers */ 404 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100; 405 ch->r_io[ATA_SERROR].offset = ch_offset + 0x104; 406 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108; 407 408 /* setup SATA registers */ 409 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70; 410 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72; 411 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74; 412 413 ch->flags |= ATA_NO_SLAVE; 414 ch->flags |= ATA_SATA; 415 ata_pci_hw(dev); 416 ch->hw.status = ata_intel_31244_status; 417 ch->hw.tf_write = ata_intel_31244_tf_write; 418 419 /* enable PHY state change interrupt */ 420 ATA_OUTL(ctlr->r_res2, 0x4, 421 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3))); 422 return 0; 423 } 424 425 static int 426 ata_intel_31244_ch_detach(device_t dev) 427 { 428 429 ata_pci_dmafini(dev); 430 return (0); 431 } 432 433 static int 434 ata_intel_31244_status(device_t dev) 435 { 436 /* do we have any PHY events ? */ 437 ata_sata_phy_check_events(dev); 438 439 /* any drive action to take care of ? */ 440 return ata_pci_status(dev); 441 } 442 443 static void 444 ata_intel_31244_tf_write(struct ata_request *request) 445 { 446 struct ata_channel *ch = device_get_softc(request->parent); 447 #ifndef ATA_CAM 448 struct ata_device *atadev = device_get_softc(request->dev); 449 #endif 450 451 if (request->flags & ATA_R_48BIT) { 452 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature); 453 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count); 454 ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) | 455 (request->u.ata.lba & 0x00ff)); 456 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) | 457 ((request->u.ata.lba >> 8) & 0x00ff)); 458 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) | 459 ((request->u.ata.lba >> 16) & 0x00ff)); 460 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit)); 461 } 462 else { 463 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 464 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 465 #ifndef ATA_CAM 466 if (atadev->flags & ATA_D_USE_CHS) { 467 int heads, sectors; 468 469 if (atadev->param.atavalid & ATA_FLAG_54_58) { 470 heads = atadev->param.current_heads; 471 sectors = atadev->param.current_sectors; 472 } 473 else { 474 heads = atadev->param.heads; 475 sectors = atadev->param.sectors; 476 } 477 ATA_IDX_OUTB(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1); 478 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 479 (request->u.ata.lba / (sectors * heads))); 480 ATA_IDX_OUTB(ch, ATA_CYL_MSB, 481 (request->u.ata.lba / (sectors * heads)) >> 8); 482 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit) | 483 (((request->u.ata.lba% (sectors * heads)) / 484 sectors) & 0xf)); 485 } 486 else { 487 #endif 488 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 489 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 490 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 491 ATA_IDX_OUTB(ch, ATA_DRIVE, 492 ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) | 493 ((request->u.ata.lba >> 24) & 0x0f)); 494 #ifndef ATA_CAM 495 } 496 #endif 497 } 498 } 499 500 static void 501 ata_intel_31244_reset(device_t dev) 502 { 503 if (ata_sata_phy_reset(dev, -1, 1)) 504 ata_generic_reset(dev); 505 } 506 507 ATA_DECLARE_DRIVER(ata_intel); 508 MODULE_DEPEND(ata_intel, ata_ahci, 1, 1, 1); 509