1 /*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ata.h" 31 #include <sys/param.h> 32 #include <sys/module.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/ata.h> 36 #include <sys/bus.h> 37 #include <sys/endian.h> 38 #include <sys/malloc.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/sema.h> 42 #include <sys/taskqueue.h> 43 #include <vm/uma.h> 44 #include <machine/stdarg.h> 45 #include <machine/resource.h> 46 #include <machine/bus.h> 47 #include <sys/rman.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/ata/ata-all.h> 51 #include <dev/ata/ata-pci.h> 52 #include <ata_if.h> 53 54 /* local prototypes */ 55 static int ata_intel_chipinit(device_t dev); 56 static int ata_intel_ch_attach(device_t dev); 57 static void ata_intel_reset(device_t dev); 58 static int ata_intel_old_setmode(device_t dev, int target, int mode); 59 static int ata_intel_new_setmode(device_t dev, int target, int mode); 60 static int ata_intel_sch_setmode(device_t dev, int target, int mode); 61 static int ata_intel_sata_getrev(device_t dev, int target); 62 static int ata_intel_sata_status(device_t dev); 63 static int ata_intel_sata_ahci_read(device_t dev, int port, 64 int reg, u_int32_t *result); 65 static int ata_intel_sata_cscr_read(device_t dev, int port, 66 int reg, u_int32_t *result); 67 static int ata_intel_sata_sidpr_read(device_t dev, int port, 68 int reg, u_int32_t *result); 69 static int ata_intel_sata_ahci_write(device_t dev, int port, 70 int reg, u_int32_t result); 71 static int ata_intel_sata_cscr_write(device_t dev, int port, 72 int reg, u_int32_t result); 73 static int ata_intel_sata_sidpr_write(device_t dev, int port, 74 int reg, u_int32_t result); 75 static int ata_intel_31244_ch_attach(device_t dev); 76 static int ata_intel_31244_ch_detach(device_t dev); 77 static int ata_intel_31244_status(device_t dev); 78 static void ata_intel_31244_tf_write(struct ata_request *request); 79 static void ata_intel_31244_reset(device_t dev); 80 81 /* misc defines */ 82 #define INTEL_AHCI 1 83 #define INTEL_ICH5 2 84 #define INTEL_6CH 4 85 #define INTEL_6CH2 8 86 #define INTEL_ICH7 16 87 88 /* 89 * Intel chipset support functions 90 */ 91 static int 92 ata_intel_probe(device_t dev) 93 { 94 struct ata_pci_controller *ctlr = device_get_softc(dev); 95 static struct ata_chip_id ids[] = 96 {{ ATA_I82371FB, 0, 0, 2, ATA_WDMA2, "PIIX" }, 97 { ATA_I82371SB, 0, 0, 2, ATA_WDMA2, "PIIX3" }, 98 { ATA_I82371AB, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 99 { ATA_I82443MX, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 100 { ATA_I82451NX, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 101 { ATA_I82801AB, 0, 0, 2, ATA_UDMA2, "ICH0" }, 102 { ATA_I82801AA, 0, 0, 2, ATA_UDMA4, "ICH" }, 103 { ATA_I82372FB, 0, 0, 2, ATA_UDMA4, "ICH" }, 104 { ATA_I82801BA, 0, 0, 2, ATA_UDMA5, "ICH2" }, 105 { ATA_I82801BA_1, 0, 0, 2, ATA_UDMA5, "ICH2" }, 106 { ATA_I82801CA, 0, 0, 2, ATA_UDMA5, "ICH3" }, 107 { ATA_I82801CA_1, 0, 0, 2, ATA_UDMA5, "ICH3" }, 108 { ATA_I82801DB, 0, 0, 2, ATA_UDMA5, "ICH4" }, 109 { ATA_I82801DB_1, 0, 0, 2, ATA_UDMA5, "ICH4" }, 110 { ATA_I82801EB, 0, 0, 2, ATA_UDMA5, "ICH5" }, 111 { ATA_I82801EB_S1, 0, INTEL_ICH5, 2, ATA_SA150, "ICH5" }, 112 { ATA_I82801EB_R1, 0, INTEL_ICH5, 2, ATA_SA150, "ICH5" }, 113 { ATA_I6300ESB, 0, 0, 2, ATA_UDMA5, "6300ESB" }, 114 { ATA_I6300ESB_S1, 0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" }, 115 { ATA_I6300ESB_R1, 0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" }, 116 { ATA_I82801FB, 0, 0, 2, ATA_UDMA5, "ICH6" }, 117 { ATA_I82801FB_S1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6" }, 118 { ATA_I82801FB_R1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6" }, 119 { ATA_I82801FBM, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6M" }, 120 { ATA_I82801GB, 0, 0, 1, ATA_UDMA5, "ICH7" }, 121 { ATA_I82801GB_S1, 0, INTEL_ICH7, 0, ATA_SA300, "ICH7" }, 122 { ATA_I82801GB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" }, 123 { ATA_I82801GB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" }, 124 { ATA_I82801GBM_S1, 0, INTEL_ICH7, 0, ATA_SA150, "ICH7M" }, 125 { ATA_I82801GBM_R1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" }, 126 { ATA_I82801GBM_AH, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" }, 127 { ATA_I63XXESB2, 0, 0, 1, ATA_UDMA5, "63XXESB2" }, 128 { ATA_I63XXESB2_S1, 0, 0, 0, ATA_SA300, "63XXESB2" }, 129 { ATA_I63XXESB2_S2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 130 { ATA_I63XXESB2_R1, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 131 { ATA_I63XXESB2_R2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 132 { ATA_I82801HB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH8" }, 133 { ATA_I82801HB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH8" }, 134 { ATA_I82801HB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 135 { ATA_I82801HB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 136 { ATA_I82801HB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 137 { ATA_I82801HBM, 0, 0, 1, ATA_UDMA5, "ICH8M" }, 138 { ATA_I82801HBM_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH8M" }, 139 { ATA_I82801HBM_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" }, 140 { ATA_I82801HBM_S3, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" }, 141 { ATA_I82801IB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH9" }, 142 { ATA_I82801IB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9" }, 143 { ATA_I82801IB_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 144 { ATA_I82801IB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 145 { ATA_I82801IB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 146 { ATA_I82801IB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 147 { ATA_I82801JIB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, 148 { ATA_I82801JIB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 149 { ATA_I82801JIB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 150 { ATA_I82801JIB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, 151 { ATA_I82801JD_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, 152 { ATA_I82801JD_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 153 { ATA_I82801JD_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 154 { ATA_I82801JD_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, 155 { ATA_I82801JI_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, 156 { ATA_I82801JI_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 157 { ATA_I82801JI_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 158 { ATA_I82801JI_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, 159 { ATA_5Series_S1, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 160 { ATA_5Series_S2, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 161 { ATA_5Series_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 162 { ATA_5Series_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 163 { ATA_5Series_R1, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 164 { ATA_5Series_S3, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 165 { ATA_5Series_S4, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 166 { ATA_5Series_AH3, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 167 { ATA_5Series_R2, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 168 { ATA_5Series_S5, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 169 { ATA_5Series_S6, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 170 { ATA_5Series_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 171 { ATA_CPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Cougar Point" }, 172 { ATA_CPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Cougar Point" }, 173 { ATA_CPT_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, 174 { ATA_CPT_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, 175 { ATA_CPT_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, 176 { ATA_CPT_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, 177 { ATA_CPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" }, 178 { ATA_CPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" }, 179 { ATA_PBG_S1, 0, INTEL_6CH, 0, ATA_SA300, "Patsburg" }, 180 { ATA_PBG_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" }, 181 { ATA_PBG_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" }, 182 { ATA_PBG_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" }, 183 { ATA_PBG_S2, 0, INTEL_6CH2, 0, ATA_SA300, "Patsburg" }, 184 { ATA_I31244, 0, 0, 2, ATA_SA150, "31244" }, 185 { ATA_ISCH, 0, 0, 1, ATA_UDMA5, "SCH" }, 186 { ATA_DH89XXCC, 0, INTEL_AHCI, 0, ATA_SA300, "DH89xxCC" }, 187 { 0, 0, 0, 0, 0, 0}}; 188 189 if (pci_get_vendor(dev) != ATA_INTEL_ID) 190 return ENXIO; 191 192 if (!(ctlr->chip = ata_match_chip(dev, ids))) 193 return ENXIO; 194 195 ata_set_desc(dev); 196 ctlr->chipinit = ata_intel_chipinit; 197 return (BUS_PROBE_DEFAULT); 198 } 199 200 static int 201 ata_intel_chipinit(device_t dev) 202 { 203 struct ata_pci_controller *ctlr = device_get_softc(dev); 204 205 if (ata_setup_interrupt(dev, ata_generic_intr)) 206 return ENXIO; 207 208 ctlr->chipset_data = NULL; 209 210 /* good old PIIX needs special treatment (not implemented) */ 211 if (ctlr->chip->chipid == ATA_I82371FB) { 212 ctlr->setmode = ata_intel_old_setmode; 213 } 214 215 /* the intel 31244 needs special care if in DPA mode */ 216 else if (ctlr->chip->chipid == ATA_I31244) { 217 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) { 218 ctlr->r_type2 = SYS_RES_MEMORY; 219 ctlr->r_rid2 = PCIR_BAR(0); 220 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 221 &ctlr->r_rid2, 222 RF_ACTIVE))) 223 return ENXIO; 224 ctlr->channels = 4; 225 ctlr->ch_attach = ata_intel_31244_ch_attach; 226 ctlr->ch_detach = ata_intel_31244_ch_detach; 227 ctlr->reset = ata_intel_31244_reset; 228 } 229 ctlr->setmode = ata_sata_setmode; 230 ctlr->getrev = ata_sata_getrev; 231 } 232 /* SCH */ 233 else if (ctlr->chip->chipid == ATA_ISCH) { 234 ctlr->channels = 1; 235 ctlr->ch_attach = ata_intel_ch_attach; 236 ctlr->ch_detach = ata_pci_ch_detach; 237 ctlr->setmode = ata_intel_sch_setmode; 238 } 239 /* non SATA intel chips goes here */ 240 else if (ctlr->chip->max_dma < ATA_SA150) { 241 ctlr->channels = ctlr->chip->cfg2; 242 ctlr->ch_attach = ata_intel_ch_attach; 243 ctlr->ch_detach = ata_pci_ch_detach; 244 ctlr->setmode = ata_intel_new_setmode; 245 } 246 247 /* SATA parts can be either compat or AHCI */ 248 else { 249 /* force all ports active "the legacy way" */ 250 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f, 2); 251 252 ctlr->ch_attach = ata_intel_ch_attach; 253 ctlr->ch_detach = ata_pci_ch_detach; 254 ctlr->reset = ata_intel_reset; 255 256 /* 257 * if we have AHCI capability and AHCI or RAID mode enabled 258 * in BIOS we try for AHCI mode 259 */ 260 if ((ctlr->chip->cfg1 & INTEL_AHCI) && 261 (pci_read_config(dev, 0x90, 1) & 0xc0) && 262 (ata_ahci_chipinit(dev) != ENXIO)) 263 return 0; 264 265 /* BAR(5) may point to SATA interface registers */ 266 if ((ctlr->chip->cfg1 & INTEL_ICH7)) { 267 ctlr->r_type2 = SYS_RES_MEMORY; 268 ctlr->r_rid2 = PCIR_BAR(5); 269 ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 270 &ctlr->r_rid2, RF_ACTIVE); 271 if (ctlr->r_res2 != NULL) { 272 /* Set SCRAE bit to enable registers access. */ 273 pci_write_config(dev, 0x94, 274 pci_read_config(dev, 0x94, 4) | (1 << 9), 4); 275 /* Set Ports Implemented register bits. */ 276 ATA_OUTL(ctlr->r_res2, 0x0C, 277 ATA_INL(ctlr->r_res2, 0x0C) | 0xf); 278 } 279 } else { 280 ctlr->r_type2 = SYS_RES_IOPORT; 281 ctlr->r_rid2 = PCIR_BAR(5); 282 ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 283 &ctlr->r_rid2, RF_ACTIVE); 284 } 285 if (ctlr->r_res2 != NULL || 286 (ctlr->chip->cfg1 & INTEL_ICH5)) 287 ctlr->getrev = ata_intel_sata_getrev; 288 ctlr->setmode = ata_sata_setmode; 289 } 290 return 0; 291 } 292 293 static int 294 ata_intel_ch_attach(device_t dev) 295 { 296 struct ata_pci_controller *ctlr; 297 struct ata_channel *ch; 298 u_char *smap; 299 u_int map; 300 301 /* setup the usual register normal pci style */ 302 if (ata_pci_ch_attach(dev)) 303 return (ENXIO); 304 305 ctlr = device_get_softc(device_get_parent(dev)); 306 ch = device_get_softc(dev); 307 308 /* if r_res2 is valid it points to SATA interface registers */ 309 if (ctlr->r_res2) { 310 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 311 ch->r_io[ATA_IDX_ADDR].offset = 0x00; 312 ch->r_io[ATA_IDX_DATA].res = ctlr->r_res2; 313 ch->r_io[ATA_IDX_DATA].offset = 0x04; 314 } 315 316 ch->flags |= ATA_ALWAYS_DMASTAT; 317 if (ctlr->chip->max_dma >= ATA_SA150) { 318 smap = (u_char *)&ctlr->chipset_data + ch->unit * 2; 319 map = pci_read_config(device_get_parent(dev), 0x90, 1); 320 if (ctlr->chip->cfg1 & INTEL_ICH5) { 321 map &= 0x07; 322 if ((map & 0x04) == 0) { 323 ch->flags |= ATA_SATA; 324 ch->flags |= ATA_NO_SLAVE; 325 smap[0] = (map & 0x01) ^ ch->unit; 326 smap[1] = 0; 327 } else if ((map & 0x02) == 0 && ch->unit == 0) { 328 ch->flags |= ATA_SATA; 329 smap[0] = (map & 0x01) ? 1 : 0; 330 smap[1] = (map & 0x01) ? 0 : 1; 331 } else if ((map & 0x02) != 0 && ch->unit == 1) { 332 ch->flags |= ATA_SATA; 333 smap[0] = (map & 0x01) ? 1 : 0; 334 smap[1] = (map & 0x01) ? 0 : 1; 335 } 336 } else if (ctlr->chip->cfg1 & INTEL_6CH2) { 337 ch->flags |= ATA_SATA; 338 ch->flags |= ATA_NO_SLAVE; 339 smap[0] = (ch->unit == 0) ? 4 : 5; 340 smap[1] = 0; 341 } else { 342 map &= 0x03; 343 if (map == 0x00) { 344 ch->flags |= ATA_SATA; 345 smap[0] = (ch->unit == 0) ? 0 : 1; 346 smap[1] = (ch->unit == 0) ? 2 : 3; 347 } else if (map == 0x02 && ch->unit == 0) { 348 ch->flags |= ATA_SATA; 349 smap[0] = 0; 350 smap[1] = 2; 351 } else if (map == 0x01 && ch->unit == 1) { 352 ch->flags |= ATA_SATA; 353 smap[0] = 1; 354 smap[1] = 3; 355 } 356 } 357 if (ch->flags & ATA_SATA) { 358 if ((ctlr->chip->cfg1 & INTEL_ICH5)) { 359 ch->flags |= ATA_PERIODIC_POLL; 360 ch->hw.status = ata_intel_sata_status; 361 ch->hw.pm_read = ata_intel_sata_cscr_read; 362 ch->hw.pm_write = ata_intel_sata_cscr_write; 363 } else if (ctlr->r_res2) { 364 ch->flags |= ATA_PERIODIC_POLL; 365 ch->hw.status = ata_intel_sata_status; 366 if ((ctlr->chip->cfg1 & INTEL_ICH7)) { 367 ch->hw.pm_read = ata_intel_sata_ahci_read; 368 ch->hw.pm_write = ata_intel_sata_ahci_write; 369 } else { 370 ch->hw.pm_read = ata_intel_sata_sidpr_read; 371 ch->hw.pm_write = ata_intel_sata_sidpr_write; 372 }; 373 } 374 if (ch->hw.pm_write != NULL) { 375 ata_sata_scr_write(ch, 0, 376 ATA_SERROR, 0xffffffff); 377 if ((ch->flags & ATA_NO_SLAVE) == 0) { 378 ata_sata_scr_write(ch, 1, 379 ATA_SERROR, 0xffffffff); 380 } 381 } 382 } else 383 ctlr->setmode = ata_intel_new_setmode; 384 } else if (ctlr->chip->chipid != ATA_ISCH) 385 ch->flags |= ATA_CHECKS_CABLE; 386 return (0); 387 } 388 389 static void 390 ata_intel_reset(device_t dev) 391 { 392 device_t parent = device_get_parent(dev); 393 struct ata_pci_controller *ctlr = device_get_softc(parent); 394 struct ata_channel *ch = device_get_softc(dev); 395 int mask, pmask, timeout, devs; 396 u_char *smap; 397 398 /* In combined mode, skip SATA stuff for PATA channel. */ 399 if ((ch->flags & ATA_SATA) == 0) 400 return (ata_generic_reset(dev)); 401 402 /* Do hard-reset on respective SATA ports. */ 403 smap = (u_char *)&ctlr->chipset_data + ch->unit * 2; 404 mask = 1 << smap[0]; 405 if ((ch->flags & ATA_NO_SLAVE) == 0) 406 mask |= (1 << smap[1]); 407 pci_write_config(parent, 0x92, 408 pci_read_config(parent, 0x92, 2) & ~mask, 2); 409 DELAY(10); 410 pci_write_config(parent, 0x92, 411 pci_read_config(parent, 0x92, 2) | mask, 2); 412 413 /* Wait up to 1 sec for "connect well". */ 414 if (ctlr->chip->cfg1 & (INTEL_6CH | INTEL_6CH2)) 415 pmask = mask << 8; 416 else 417 pmask = mask << 4; 418 for (timeout = 0; timeout < 100 ; timeout++) { 419 if (((pci_read_config(parent, 0x92, 2) & pmask) == pmask) && 420 (ATA_IDX_INB(ch, ATA_STATUS) != 0xff)) 421 break; 422 ata_udelay(10000); 423 } 424 425 /* If any device found, do soft-reset. */ 426 if (ch->hw.pm_read != NULL) { 427 devs = ata_sata_phy_reset(dev, 0, 2); 428 if ((ch->flags & ATA_NO_SLAVE) == 0) 429 devs += ata_sata_phy_reset(dev, 1, 2); 430 } else 431 devs = 1; 432 if (devs) 433 ata_generic_reset(dev); 434 else 435 ch->devices = 0; 436 } 437 438 static int 439 ata_intel_old_setmode(device_t dev, int target, int mode) 440 { 441 device_t parent = device_get_parent(dev); 442 struct ata_pci_controller *ctlr = device_get_softc(parent); 443 444 mode = min(mode, ctlr->chip->max_dma); 445 return (mode); 446 } 447 448 static int 449 ata_intel_new_setmode(device_t dev, int target, int mode) 450 { 451 device_t parent = device_get_parent(dev); 452 struct ata_pci_controller *ctlr = device_get_softc(parent); 453 struct ata_channel *ch = device_get_softc(dev); 454 int devno = (ch->unit << 1) + target; 455 int piomode; 456 u_int32_t reg40 = pci_read_config(parent, 0x40, 4); 457 u_int8_t reg44 = pci_read_config(parent, 0x44, 1); 458 u_int8_t reg48 = pci_read_config(parent, 0x48, 1); 459 u_int16_t reg4a = pci_read_config(parent, 0x4a, 2); 460 u_int16_t reg54 = pci_read_config(parent, 0x54, 2); 461 u_int32_t mask40 = 0, new40 = 0; 462 u_int8_t mask44 = 0, new44 = 0; 463 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x00, 0x21, 0x23 }; 464 u_int8_t utimings[] = { 0x00, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02 }; 465 466 /* In combined mode, skip PATA stuff for SATA channel. */ 467 if (ch->flags & ATA_SATA) 468 return (ata_sata_setmode(dev, target, mode)); 469 470 mode = min(mode, ctlr->chip->max_dma); 471 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 472 !(reg54 & (0x10 << devno))) { 473 ata_print_cable(dev, "controller"); 474 mode = ATA_UDMA2; 475 } 476 /* Enable/disable UDMA and set timings. */ 477 if (mode >= ATA_UDMA0) { 478 pci_write_config(parent, 0x48, reg48 | (0x0001 << devno), 2); 479 pci_write_config(parent, 0x4a, 480 (reg4a & ~(0x3 << (devno << 2))) | 481 (utimings[mode & ATA_MODE_MASK] << (devno<<2)), 2); 482 piomode = ATA_PIO4; 483 } else { 484 pci_write_config(parent, 0x48, reg48 & ~(0x0001 << devno), 2); 485 pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (devno << 2))),2); 486 piomode = mode; 487 } 488 reg54 |= 0x0400; 489 /* Set UDMA reference clock (33/66/133MHz). */ 490 reg54 &= ~(0x1001 << devno); 491 if (mode >= ATA_UDMA5) 492 reg54 |= (0x1000 << devno); 493 else if (mode >= ATA_UDMA3) 494 reg54 |= (0x1 << devno); 495 pci_write_config(parent, 0x54, reg54, 2); 496 /* Allow PIO/WDMA timing controls. */ 497 reg40 &= ~0x00ff00ff; 498 reg40 |= 0x40774077; 499 /* Set PIO/WDMA timings. */ 500 if (target == 0) { 501 mask40 = 0x3300; 502 new40 = timings[ata_mode2idx(piomode)] << 8; 503 } else { 504 mask44 = 0x0f; 505 new44 = ((timings[ata_mode2idx(piomode)] & 0x30) >> 2) | 506 (timings[ata_mode2idx(piomode)] & 0x03); 507 } 508 if (ch->unit) { 509 mask40 <<= 16; 510 new40 <<= 16; 511 mask44 <<= 4; 512 new44 <<= 4; 513 } 514 pci_write_config(parent, 0x40, (reg40 & ~mask40) | new40, 4); 515 pci_write_config(parent, 0x44, (reg44 & ~mask44) | new44, 1); 516 return (mode); 517 } 518 519 static int 520 ata_intel_sch_setmode(device_t dev, int target, int mode) 521 { 522 device_t parent = device_get_parent(dev); 523 struct ata_pci_controller *ctlr = device_get_softc(parent); 524 u_int8_t dtim = 0x80 + (target << 2); 525 u_int32_t tim = pci_read_config(parent, dtim, 4); 526 int piomode; 527 528 mode = min(mode, ctlr->chip->max_dma); 529 if (mode >= ATA_UDMA0) { 530 tim |= (0x1 << 31); 531 tim &= ~(0x7 << 16); 532 tim |= ((mode & ATA_MODE_MASK) << 16); 533 piomode = ATA_PIO4; 534 } else if (mode >= ATA_WDMA0) { 535 tim &= ~(0x1 << 31); 536 tim &= ~(0x3 << 8); 537 tim |= ((mode & ATA_MODE_MASK) << 8); 538 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 : 539 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4; 540 } else 541 piomode = mode; 542 tim &= ~(0x7); 543 tim |= (piomode & 0x7); 544 pci_write_config(parent, dtim, tim, 4); 545 return (mode); 546 } 547 548 static int 549 ata_intel_sata_getrev(device_t dev, int target) 550 { 551 struct ata_channel *ch = device_get_softc(dev); 552 uint32_t status; 553 554 if (ata_sata_scr_read(ch, target, ATA_SSTATUS, &status) == 0) 555 return ((status & 0x0f0) >> 4); 556 return (0xff); 557 } 558 559 static int 560 ata_intel_sata_status(device_t dev) 561 { 562 struct ata_channel *ch = device_get_softc(dev); 563 564 ata_sata_phy_check_events(dev, 0); 565 if ((ch->flags & ATA_NO_SLAVE) == 0) 566 ata_sata_phy_check_events(dev, 1); 567 568 return ata_pci_status(dev); 569 } 570 571 static int 572 ata_intel_sata_ahci_read(device_t dev, int port, int reg, u_int32_t *result) 573 { 574 struct ata_pci_controller *ctlr; 575 struct ata_channel *ch; 576 device_t parent; 577 u_char *smap; 578 int offset; 579 580 parent = device_get_parent(dev); 581 ctlr = device_get_softc(parent); 582 ch = device_get_softc(dev); 583 port = (port == 1) ? 1 : 0; 584 smap = (u_char *)&ctlr->chipset_data + ch->unit * 2; 585 offset = 0x100 + smap[port] * 0x80; 586 switch (reg) { 587 case ATA_SSTATUS: 588 reg = 0x28; 589 break; 590 case ATA_SCONTROL: 591 reg = 0x2c; 592 break; 593 case ATA_SERROR: 594 reg = 0x30; 595 break; 596 default: 597 return (EINVAL); 598 } 599 *result = ATA_INL(ctlr->r_res2, offset + reg); 600 return (0); 601 } 602 603 static int 604 ata_intel_sata_cscr_read(device_t dev, int port, int reg, u_int32_t *result) 605 { 606 struct ata_pci_controller *ctlr; 607 struct ata_channel *ch; 608 device_t parent; 609 u_char *smap; 610 611 parent = device_get_parent(dev); 612 ctlr = device_get_softc(parent); 613 ch = device_get_softc(dev); 614 smap = (u_char *)&ctlr->chipset_data + ch->unit * 2; 615 port = (port == 1) ? 1 : 0; 616 switch (reg) { 617 case ATA_SSTATUS: 618 reg = 0; 619 break; 620 case ATA_SERROR: 621 reg = 1; 622 break; 623 case ATA_SCONTROL: 624 reg = 2; 625 break; 626 default: 627 return (EINVAL); 628 } 629 pci_write_config(parent, 0xa0, 630 0x50 + smap[port] * 0x10 + reg * 4, 4); 631 *result = pci_read_config(parent, 0xa4, 4); 632 return (0); 633 } 634 635 static int 636 ata_intel_sata_sidpr_read(device_t dev, int port, int reg, u_int32_t *result) 637 { 638 struct ata_pci_controller *ctlr; 639 struct ata_channel *ch; 640 device_t parent; 641 642 parent = device_get_parent(dev); 643 ctlr = device_get_softc(parent); 644 ch = device_get_softc(dev); 645 port = (port == 1) ? 1 : 0; 646 switch (reg) { 647 case ATA_SSTATUS: 648 reg = 0; 649 break; 650 case ATA_SCONTROL: 651 reg = 1; 652 break; 653 case ATA_SERROR: 654 reg = 2; 655 break; 656 default: 657 return (EINVAL); 658 } 659 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, ((ch->unit * 2 + port) << 8) + reg); 660 *result = ATA_IDX_INL(ch, ATA_IDX_DATA); 661 return (0); 662 } 663 664 static int 665 ata_intel_sata_ahci_write(device_t dev, int port, int reg, u_int32_t value) 666 { 667 struct ata_pci_controller *ctlr; 668 struct ata_channel *ch; 669 device_t parent; 670 u_char *smap; 671 int offset; 672 673 parent = device_get_parent(dev); 674 ctlr = device_get_softc(parent); 675 ch = device_get_softc(dev); 676 port = (port == 1) ? 1 : 0; 677 smap = (u_char *)&ctlr->chipset_data + ch->unit * 2; 678 offset = 0x100 + smap[port] * 0x80; 679 switch (reg) { 680 case ATA_SSTATUS: 681 reg = 0x28; 682 break; 683 case ATA_SCONTROL: 684 reg = 0x2c; 685 break; 686 case ATA_SERROR: 687 reg = 0x30; 688 break; 689 default: 690 return (EINVAL); 691 } 692 ATA_OUTL(ctlr->r_res2, offset + reg, value); 693 return (0); 694 } 695 696 static int 697 ata_intel_sata_cscr_write(device_t dev, int port, int reg, u_int32_t value) 698 { 699 struct ata_pci_controller *ctlr; 700 struct ata_channel *ch; 701 device_t parent; 702 u_char *smap; 703 704 parent = device_get_parent(dev); 705 ctlr = device_get_softc(parent); 706 ch = device_get_softc(dev); 707 smap = (u_char *)&ctlr->chipset_data + ch->unit * 2; 708 port = (port == 1) ? 1 : 0; 709 switch (reg) { 710 case ATA_SSTATUS: 711 reg = 0; 712 break; 713 case ATA_SERROR: 714 reg = 1; 715 break; 716 case ATA_SCONTROL: 717 reg = 2; 718 break; 719 default: 720 return (EINVAL); 721 } 722 pci_write_config(parent, 0xa0, 723 0x50 + smap[port] * 0x10 + reg * 4, 4); 724 pci_write_config(parent, 0xa4, value, 4); 725 return (0); 726 } 727 728 static int 729 ata_intel_sata_sidpr_write(device_t dev, int port, int reg, u_int32_t value) 730 { 731 struct ata_pci_controller *ctlr; 732 struct ata_channel *ch; 733 device_t parent; 734 735 parent = device_get_parent(dev); 736 ctlr = device_get_softc(parent); 737 ch = device_get_softc(dev); 738 port = (port == 1) ? 1 : 0; 739 switch (reg) { 740 case ATA_SSTATUS: 741 reg = 0; 742 break; 743 case ATA_SCONTROL: 744 reg = 1; 745 break; 746 case ATA_SERROR: 747 reg = 2; 748 break; 749 default: 750 return (EINVAL); 751 } 752 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, ((ch->unit * 2 + port) << 8) + reg); 753 ATA_IDX_OUTL(ch, ATA_IDX_DATA, value); 754 return (0); 755 } 756 757 static int 758 ata_intel_31244_ch_attach(device_t dev) 759 { 760 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 761 struct ata_channel *ch = device_get_softc(dev); 762 int i; 763 int ch_offset; 764 765 ata_pci_dmainit(dev); 766 767 ch_offset = 0x200 + ch->unit * 0x200; 768 769 for (i = ATA_DATA; i < ATA_MAX_RES; i++) 770 ch->r_io[i].res = ctlr->r_res2; 771 772 /* setup ATA registers */ 773 ch->r_io[ATA_DATA].offset = ch_offset + 0x00; 774 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06; 775 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08; 776 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c; 777 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; 778 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14; 779 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18; 780 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d; 781 ch->r_io[ATA_ERROR].offset = ch_offset + 0x04; 782 ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c; 783 ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28; 784 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29; 785 786 /* setup DMA registers */ 787 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100; 788 ch->r_io[ATA_SERROR].offset = ch_offset + 0x104; 789 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108; 790 791 /* setup SATA registers */ 792 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70; 793 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72; 794 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74; 795 796 ch->flags |= ATA_NO_SLAVE; 797 ch->flags |= ATA_SATA; 798 ata_pci_hw(dev); 799 ch->hw.status = ata_intel_31244_status; 800 ch->hw.tf_write = ata_intel_31244_tf_write; 801 802 /* enable PHY state change interrupt */ 803 ATA_OUTL(ctlr->r_res2, 0x4, 804 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3))); 805 return 0; 806 } 807 808 static int 809 ata_intel_31244_ch_detach(device_t dev) 810 { 811 812 ata_pci_dmafini(dev); 813 return (0); 814 } 815 816 static int 817 ata_intel_31244_status(device_t dev) 818 { 819 /* do we have any PHY events ? */ 820 ata_sata_phy_check_events(dev, -1); 821 822 /* any drive action to take care of ? */ 823 return ata_pci_status(dev); 824 } 825 826 static void 827 ata_intel_31244_tf_write(struct ata_request *request) 828 { 829 struct ata_channel *ch = device_get_softc(request->parent); 830 #ifndef ATA_CAM 831 struct ata_device *atadev = device_get_softc(request->dev); 832 #endif 833 834 if (request->flags & ATA_R_48BIT) { 835 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature); 836 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count); 837 ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) | 838 (request->u.ata.lba & 0x00ff)); 839 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) | 840 ((request->u.ata.lba >> 8) & 0x00ff)); 841 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) | 842 ((request->u.ata.lba >> 16) & 0x00ff)); 843 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit)); 844 } 845 else { 846 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 847 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 848 #ifndef ATA_CAM 849 if (atadev->flags & ATA_D_USE_CHS) { 850 int heads, sectors; 851 852 if (atadev->param.atavalid & ATA_FLAG_54_58) { 853 heads = atadev->param.current_heads; 854 sectors = atadev->param.current_sectors; 855 } 856 else { 857 heads = atadev->param.heads; 858 sectors = atadev->param.sectors; 859 } 860 ATA_IDX_OUTB(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1); 861 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 862 (request->u.ata.lba / (sectors * heads))); 863 ATA_IDX_OUTB(ch, ATA_CYL_MSB, 864 (request->u.ata.lba / (sectors * heads)) >> 8); 865 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit) | 866 (((request->u.ata.lba% (sectors * heads)) / 867 sectors) & 0xf)); 868 } 869 else { 870 #endif 871 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 872 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 873 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 874 ATA_IDX_OUTB(ch, ATA_DRIVE, 875 ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) | 876 ((request->u.ata.lba >> 24) & 0x0f)); 877 #ifndef ATA_CAM 878 } 879 #endif 880 } 881 } 882 883 static void 884 ata_intel_31244_reset(device_t dev) 885 { 886 struct ata_channel *ch = device_get_softc(dev); 887 888 if (ata_sata_phy_reset(dev, -1, 1)) 889 ata_generic_reset(dev); 890 else 891 ch->devices = 0; 892 } 893 894 ATA_DECLARE_DRIVER(ata_intel); 895 MODULE_DEPEND(ata_intel, ata_ahci, 1, 1, 1); 896