1 /*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ata.h" 31 #include <sys/param.h> 32 #include <sys/module.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/ata.h> 36 #include <sys/bus.h> 37 #include <sys/endian.h> 38 #include <sys/malloc.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/sema.h> 42 #include <sys/taskqueue.h> 43 #include <vm/uma.h> 44 #include <machine/stdarg.h> 45 #include <machine/resource.h> 46 #include <machine/bus.h> 47 #include <sys/rman.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/ata/ata-all.h> 51 #include <dev/ata/ata-pci.h> 52 #include <ata_if.h> 53 54 /* local prototypes */ 55 static int ata_intel_chipinit(device_t dev); 56 static int ata_intel_ch_attach(device_t dev); 57 static void ata_intel_reset(device_t dev); 58 static int ata_intel_old_setmode(device_t dev, int target, int mode); 59 static int ata_intel_new_setmode(device_t dev, int target, int mode); 60 static int ata_intel_sch_setmode(device_t dev, int target, int mode); 61 static int ata_intel_sata_getrev(device_t dev, int target); 62 static int ata_intel_31244_ch_attach(device_t dev); 63 static int ata_intel_31244_ch_detach(device_t dev); 64 static int ata_intel_31244_status(device_t dev); 65 static void ata_intel_31244_tf_write(struct ata_request *request); 66 static void ata_intel_31244_reset(device_t dev); 67 68 /* misc defines */ 69 #define INTEL_AHCI 1 70 71 72 /* 73 * Intel chipset support functions 74 */ 75 static int 76 ata_intel_probe(device_t dev) 77 { 78 struct ata_pci_controller *ctlr = device_get_softc(dev); 79 static struct ata_chip_id ids[] = 80 {{ ATA_I82371FB, 0, 0, 2, ATA_WDMA2, "PIIX" }, 81 { ATA_I82371SB, 0, 0, 2, ATA_WDMA2, "PIIX3" }, 82 { ATA_I82371AB, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 83 { ATA_I82443MX, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 84 { ATA_I82451NX, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 85 { ATA_I82801AB, 0, 0, 2, ATA_UDMA2, "ICH0" }, 86 { ATA_I82801AA, 0, 0, 2, ATA_UDMA4, "ICH" }, 87 { ATA_I82372FB, 0, 0, 2, ATA_UDMA4, "ICH" }, 88 { ATA_I82801BA, 0, 0, 2, ATA_UDMA5, "ICH2" }, 89 { ATA_I82801BA_1, 0, 0, 2, ATA_UDMA5, "ICH2" }, 90 { ATA_I82801CA, 0, 0, 2, ATA_UDMA5, "ICH3" }, 91 { ATA_I82801CA_1, 0, 0, 2, ATA_UDMA5, "ICH3" }, 92 { ATA_I82801DB, 0, 0, 2, ATA_UDMA5, "ICH4" }, 93 { ATA_I82801DB_1, 0, 0, 2, ATA_UDMA5, "ICH4" }, 94 { ATA_I82801EB, 0, 0, 2, ATA_UDMA5, "ICH5" }, 95 { ATA_I82801EB_S1, 0, 0, 2, ATA_SA150, "ICH5" }, 96 { ATA_I82801EB_R1, 0, 0, 2, ATA_SA150, "ICH5" }, 97 { ATA_I6300ESB, 0, 0, 2, ATA_UDMA5, "6300ESB" }, 98 { ATA_I6300ESB_S1, 0, 0, 2, ATA_SA150, "6300ESB" }, 99 { ATA_I6300ESB_R1, 0, 0, 2, ATA_SA150, "6300ESB" }, 100 { ATA_I82801FB, 0, 0, 2, ATA_UDMA5, "ICH6" }, 101 { ATA_I82801FB_S1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6" }, 102 { ATA_I82801FB_R1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6" }, 103 { ATA_I82801FBM, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6M" }, 104 { ATA_I82801GB, 0, 0, 1, ATA_UDMA5, "ICH7" }, 105 { ATA_I82801GB_S1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" }, 106 { ATA_I82801GB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" }, 107 { ATA_I82801GB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" }, 108 { ATA_I82801GBM_S1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" }, 109 { ATA_I82801GBM_R1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" }, 110 { ATA_I82801GBM_AH, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" }, 111 { ATA_I63XXESB2, 0, 0, 1, ATA_UDMA5, "63XXESB2" }, 112 { ATA_I63XXESB2_S1, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 113 { ATA_I63XXESB2_S2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 114 { ATA_I63XXESB2_R1, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 115 { ATA_I63XXESB2_R2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 116 { ATA_I82801HB_S1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 117 { ATA_I82801HB_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 118 { ATA_I82801HB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 119 { ATA_I82801HB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 120 { ATA_I82801HB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 121 { ATA_I82801HBM, 0, 0, 1, ATA_UDMA5, "ICH8M" }, 122 { ATA_I82801HBM_S1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" }, 123 { ATA_I82801HBM_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" }, 124 { ATA_I82801HBM_S3, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" }, 125 { ATA_I82801IB_S1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 126 { ATA_I82801IB_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 127 { ATA_I82801IB_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 128 { ATA_I82801IB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 129 { ATA_I82801IB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 130 { ATA_I82801IB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 131 { ATA_I82801JIB_S1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 132 { ATA_I82801JIB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 133 { ATA_I82801JIB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 134 { ATA_I82801JIB_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 135 { ATA_I82801JD_S1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 136 { ATA_I82801JD_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 137 { ATA_I82801JD_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 138 { ATA_I82801JD_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 139 { ATA_I82801JI_S1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 140 { ATA_I82801JI_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 141 { ATA_I82801JI_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 142 { ATA_I82801JI_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 143 { 0x3b208086, 0, INTEL_AHCI, 0, ATA_SA300, "PCH" }, 144 { 0x3b218086, 0, INTEL_AHCI, 0, ATA_SA300, "PCH" }, 145 { 0x3b228086, 0, INTEL_AHCI, 0, ATA_SA300, "PCH" }, 146 { 0x3b238086, 0, INTEL_AHCI, 0, ATA_SA300, "PCH" }, 147 { 0x3b248086, 0, INTEL_AHCI, 0, ATA_SA300, "PCH" }, 148 { 0x3b258086, 0, INTEL_AHCI, 0, ATA_SA300, "PCH" }, 149 { 0x3b268086, 0, INTEL_AHCI, 0, ATA_SA300, "PCH" }, 150 { 0x3b278086, 0, INTEL_AHCI, 0, ATA_SA300, "PCH" }, 151 { 0x3b288086, 0, INTEL_AHCI, 0, ATA_SA300, "PCH" }, 152 { 0x3b298086, 0, INTEL_AHCI, 0, ATA_SA300, "PCH" }, 153 { 0x3b2a8086, 0, INTEL_AHCI, 0, ATA_SA300, "PCH" }, 154 { 0x3b2b8086, 0, INTEL_AHCI, 0, ATA_SA300, "PCH" }, 155 { 0x3b2c8086, 0, INTEL_AHCI, 0, ATA_SA300, "PCH" }, 156 { 0x3b2d8086, 0, INTEL_AHCI, 0, ATA_SA300, "PCH" }, 157 { 0x3b2e8086, 0, INTEL_AHCI, 0, ATA_SA300, "PCH" }, 158 { 0x3b2f8086, 0, INTEL_AHCI, 0, ATA_SA300, "PCH" }, 159 { ATA_I31244, 0, 0, 2, ATA_SA150, "31244" }, 160 { ATA_ISCH, 0, 0, 1, ATA_UDMA5, "SCH" }, 161 { 0, 0, 0, 0, 0, 0}}; 162 163 if (pci_get_vendor(dev) != ATA_INTEL_ID) 164 return ENXIO; 165 166 if (!(ctlr->chip = ata_match_chip(dev, ids))) 167 return ENXIO; 168 169 ata_set_desc(dev); 170 ctlr->chipinit = ata_intel_chipinit; 171 return (BUS_PROBE_DEFAULT); 172 } 173 174 static int 175 ata_intel_chipinit(device_t dev) 176 { 177 struct ata_pci_controller *ctlr = device_get_softc(dev); 178 179 if (ata_setup_interrupt(dev, ata_generic_intr)) 180 return ENXIO; 181 182 /* good old PIIX needs special treatment (not implemented) */ 183 if (ctlr->chip->chipid == ATA_I82371FB) { 184 ctlr->setmode = ata_intel_old_setmode; 185 } 186 187 /* the intel 31244 needs special care if in DPA mode */ 188 else if (ctlr->chip->chipid == ATA_I31244) { 189 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) { 190 ctlr->r_type2 = SYS_RES_MEMORY; 191 ctlr->r_rid2 = PCIR_BAR(0); 192 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 193 &ctlr->r_rid2, 194 RF_ACTIVE))) 195 return ENXIO; 196 ctlr->channels = 4; 197 ctlr->ch_attach = ata_intel_31244_ch_attach; 198 ctlr->ch_detach = ata_intel_31244_ch_detach; 199 ctlr->reset = ata_intel_31244_reset; 200 } 201 ctlr->setmode = ata_sata_setmode; 202 ctlr->getrev = ata_sata_getrev; 203 } 204 /* SCH */ 205 else if (ctlr->chip->chipid == ATA_ISCH) { 206 ctlr->channels = 1; 207 ctlr->ch_attach = ata_intel_ch_attach; 208 ctlr->ch_detach = ata_pci_ch_detach; 209 ctlr->setmode = ata_intel_sch_setmode; 210 } 211 /* non SATA intel chips goes here */ 212 else if (ctlr->chip->max_dma < ATA_SA150) { 213 ctlr->channels = ctlr->chip->cfg2; 214 ctlr->ch_attach = ata_intel_ch_attach; 215 ctlr->ch_detach = ata_pci_ch_detach; 216 ctlr->setmode = ata_intel_new_setmode; 217 } 218 219 /* SATA parts can be either compat or AHCI */ 220 else { 221 /* force all ports active "the legacy way" */ 222 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f, 2); 223 224 ctlr->ch_attach = ata_intel_ch_attach; 225 ctlr->ch_detach = ata_pci_ch_detach; 226 ctlr->reset = ata_intel_reset; 227 228 /* 229 * if we have AHCI capability and AHCI or RAID mode enabled 230 * in BIOS we try for AHCI mode 231 */ 232 if ((ctlr->chip->cfg1 == INTEL_AHCI) && 233 (pci_read_config(dev, 0x90, 1) & 0xc0) && 234 (ata_ahci_chipinit(dev) != ENXIO)) 235 return 0; 236 237 /* if BAR(5) is IO it should point to SATA interface registers */ 238 ctlr->r_type2 = SYS_RES_IOPORT; 239 ctlr->r_rid2 = PCIR_BAR(5); 240 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 241 &ctlr->r_rid2, RF_ACTIVE))) 242 ctlr->getrev = ata_intel_sata_getrev; 243 ctlr->setmode = ata_sata_setmode; 244 } 245 return 0; 246 } 247 248 static int 249 ata_intel_ch_attach(device_t dev) 250 { 251 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 252 struct ata_channel *ch = device_get_softc(dev); 253 254 /* setup the usual register normal pci style */ 255 if (ata_pci_ch_attach(dev)) 256 return ENXIO; 257 258 /* if r_res2 is valid it points to SATA interface registers */ 259 if (ctlr->r_res2) { 260 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 261 ch->r_io[ATA_IDX_ADDR].offset = 0x00; 262 ch->r_io[ATA_IDX_DATA].res = ctlr->r_res2; 263 ch->r_io[ATA_IDX_DATA].offset = 0x04; 264 } 265 266 ch->flags |= ATA_ALWAYS_DMASTAT; 267 if (ctlr->chip->max_dma >= ATA_SA150) { 268 if (ctlr->chip->cfg1 == 0 && 269 (pci_read_config(device_get_parent(dev), 0x90, 1) & 0x04) == 0) 270 ch->flags |= ATA_NO_SLAVE; 271 ch->flags |= ATA_SATA; 272 } else if (ctlr->chip->chipid != ATA_ISCH) 273 ch->flags |= ATA_CHECKS_CABLE; 274 return 0; 275 } 276 277 static void 278 ata_intel_reset(device_t dev) 279 { 280 device_t parent = device_get_parent(dev); 281 struct ata_pci_controller *ctlr = device_get_softc(parent); 282 struct ata_channel *ch = device_get_softc(dev); 283 int mask, timeout; 284 285 /* ICH6 & ICH7 in compat mode has 4 SATA ports as master/slave on 2 ch's */ 286 if (ctlr->chip->cfg1) { 287 mask = (0x0005 << ch->unit); 288 } 289 else { 290 /* ICH5 in compat mode has SATA ports as master/slave on 1 channel */ 291 if (pci_read_config(parent, 0x90, 1) & 0x04) 292 mask = 0x0003; 293 else 294 mask = (0x0001 << ch->unit); 295 } 296 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) & ~mask, 2); 297 DELAY(10); 298 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) | mask, 2); 299 300 /* wait up to 1 sec for "connect well" */ 301 for (timeout = 0; timeout < 100 ; timeout++) { 302 if (((pci_read_config(parent, 0x92, 2) & (mask << 4)) == (mask << 4)) && 303 (ATA_IDX_INB(ch, ATA_STATUS) != 0xff)) 304 break; 305 ata_udelay(10000); 306 } 307 ata_generic_reset(dev); 308 } 309 310 static int 311 ata_intel_old_setmode(device_t dev, int target, int mode) 312 { 313 device_t parent = device_get_parent(dev); 314 struct ata_pci_controller *ctlr = device_get_softc(parent); 315 316 mode = min(mode, ctlr->chip->max_dma); 317 return (mode); 318 } 319 320 static int 321 ata_intel_new_setmode(device_t dev, int target, int mode) 322 { 323 device_t parent = device_get_parent(dev); 324 struct ata_pci_controller *ctlr = device_get_softc(parent); 325 struct ata_channel *ch = device_get_softc(dev); 326 int devno = (ch->unit << 1) + target; 327 int piomode; 328 u_int32_t reg40 = pci_read_config(parent, 0x40, 4); 329 u_int8_t reg44 = pci_read_config(parent, 0x44, 1); 330 u_int8_t reg48 = pci_read_config(parent, 0x48, 1); 331 u_int16_t reg4a = pci_read_config(parent, 0x4a, 2); 332 u_int16_t reg54 = pci_read_config(parent, 0x54, 2); 333 u_int32_t mask40 = 0, new40 = 0; 334 u_int8_t mask44 = 0, new44 = 0; 335 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x00, 0x21, 0x23 }; 336 u_int8_t utimings[] = { 0x00, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02 }; 337 338 mode = min(mode, ctlr->chip->max_dma); 339 if (mode > ATA_UDMA2 && !(reg54 & (0x10 << devno))) { 340 ata_print_cable(dev, "controller"); 341 mode = ATA_UDMA2; 342 } 343 /* Enable/disable UDMA and set timings. */ 344 if (mode >= ATA_UDMA0) { 345 pci_write_config(parent, 0x48, reg48 | (0x0001 << devno), 2); 346 pci_write_config(parent, 0x4a, 347 (reg4a & ~(0x3 << (devno << 2))) | 348 (utimings[mode & ATA_MODE_MASK] << (devno<<2)), 2); 349 piomode = ATA_PIO4; 350 } else { 351 pci_write_config(parent, 0x48, reg48 & ~(0x0001 << devno), 2); 352 pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (devno << 2))),2); 353 piomode = mode; 354 } 355 reg54 |= 0x0400; 356 /* Set UDMA reference clock (33/66/133MHz). */ 357 reg54 &= ~(0x1001 << devno); 358 if (mode >= ATA_UDMA5) 359 reg54 |= (0x1000 << devno); 360 else if (mode >= ATA_UDMA3) 361 reg54 |= (0x1 << devno); 362 pci_write_config(parent, 0x54, reg54, 2); 363 /* Allow PIO/WDMA timing controls. */ 364 reg40 &= ~0x00ff00ff; 365 reg40 |= 0x40774077; 366 /* Set PIO/WDMA timings. */ 367 if (target == 0) { 368 mask40 = 0x3300; 369 new40 = timings[ata_mode2idx(piomode)] << 8; 370 } else { 371 mask44 = 0x0f; 372 new44 = ((timings[ata_mode2idx(piomode)] & 0x30) >> 2) | 373 (timings[ata_mode2idx(piomode)] & 0x03); 374 } 375 if (ch->unit) { 376 mask40 <<= 16; 377 new40 <<= 16; 378 mask44 <<= 4; 379 new44 <<= 4; 380 } 381 pci_write_config(parent, 0x40, (reg40 & ~mask40) | new40, 4); 382 pci_write_config(parent, 0x44, (reg44 & ~mask44) | new44, 1); 383 return (mode); 384 } 385 386 static int 387 ata_intel_sch_setmode(device_t dev, int target, int mode) 388 { 389 device_t parent = device_get_parent(dev); 390 struct ata_pci_controller *ctlr = device_get_softc(parent); 391 u_int8_t dtim = 0x80 + (target << 2); 392 u_int32_t tim = pci_read_config(parent, dtim, 4); 393 int piomode; 394 395 mode = min(mode, ctlr->chip->max_dma); 396 if (mode >= ATA_UDMA0) { 397 tim |= (0x1 << 31); 398 tim &= ~(0x7 << 16); 399 tim |= ((mode & ATA_MODE_MASK) << 16); 400 piomode = ATA_PIO4; 401 } else if (mode >= ATA_WDMA0) { 402 tim &= ~(0x1 << 31); 403 tim &= ~(0x3 << 8); 404 tim |= ((mode & ATA_MODE_MASK) << 8); 405 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 : 406 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4; 407 } else 408 piomode = mode; 409 tim &= ~(0x7); 410 tim |= (piomode & 0x7); 411 pci_write_config(parent, dtim, tim, 4); 412 return (mode); 413 } 414 415 static int 416 ata_intel_sata_getrev(device_t dev, int target) 417 { 418 struct ata_channel *ch = device_get_softc(dev); 419 int devno = (ch->unit << 1) + target; 420 421 /* set ATA_SSTATUS register offset */ 422 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, devno * 0x100); 423 /* query SATA STATUS for the speed */ 424 return ((ATA_IDX_INL(ch, ATA_IDX_DATA) & 0x0f0) >> 4); 425 } 426 427 static int 428 ata_intel_31244_ch_attach(device_t dev) 429 { 430 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 431 struct ata_channel *ch = device_get_softc(dev); 432 int i; 433 int ch_offset; 434 435 ata_pci_dmainit(dev); 436 437 ch_offset = 0x200 + ch->unit * 0x200; 438 439 for (i = ATA_DATA; i < ATA_MAX_RES; i++) 440 ch->r_io[i].res = ctlr->r_res2; 441 442 /* setup ATA registers */ 443 ch->r_io[ATA_DATA].offset = ch_offset + 0x00; 444 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06; 445 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08; 446 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c; 447 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; 448 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14; 449 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18; 450 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d; 451 ch->r_io[ATA_ERROR].offset = ch_offset + 0x04; 452 ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c; 453 ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28; 454 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29; 455 456 /* setup DMA registers */ 457 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100; 458 ch->r_io[ATA_SERROR].offset = ch_offset + 0x104; 459 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108; 460 461 /* setup SATA registers */ 462 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70; 463 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72; 464 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74; 465 466 ch->flags |= ATA_NO_SLAVE; 467 ch->flags |= ATA_SATA; 468 ata_pci_hw(dev); 469 ch->hw.status = ata_intel_31244_status; 470 ch->hw.tf_write = ata_intel_31244_tf_write; 471 472 /* enable PHY state change interrupt */ 473 ATA_OUTL(ctlr->r_res2, 0x4, 474 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3))); 475 return 0; 476 } 477 478 static int 479 ata_intel_31244_ch_detach(device_t dev) 480 { 481 482 ata_pci_dmafini(dev); 483 return (0); 484 } 485 486 static int 487 ata_intel_31244_status(device_t dev) 488 { 489 /* do we have any PHY events ? */ 490 ata_sata_phy_check_events(dev); 491 492 /* any drive action to take care of ? */ 493 return ata_pci_status(dev); 494 } 495 496 static void 497 ata_intel_31244_tf_write(struct ata_request *request) 498 { 499 struct ata_channel *ch = device_get_softc(request->parent); 500 #ifndef ATA_CAM 501 struct ata_device *atadev = device_get_softc(request->dev); 502 #endif 503 504 if (request->flags & ATA_R_48BIT) { 505 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature); 506 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count); 507 ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) | 508 (request->u.ata.lba & 0x00ff)); 509 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) | 510 ((request->u.ata.lba >> 8) & 0x00ff)); 511 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) | 512 ((request->u.ata.lba >> 16) & 0x00ff)); 513 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit)); 514 } 515 else { 516 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 517 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 518 #ifndef ATA_CAM 519 if (atadev->flags & ATA_D_USE_CHS) { 520 int heads, sectors; 521 522 if (atadev->param.atavalid & ATA_FLAG_54_58) { 523 heads = atadev->param.current_heads; 524 sectors = atadev->param.current_sectors; 525 } 526 else { 527 heads = atadev->param.heads; 528 sectors = atadev->param.sectors; 529 } 530 ATA_IDX_OUTB(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1); 531 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 532 (request->u.ata.lba / (sectors * heads))); 533 ATA_IDX_OUTB(ch, ATA_CYL_MSB, 534 (request->u.ata.lba / (sectors * heads)) >> 8); 535 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit) | 536 (((request->u.ata.lba% (sectors * heads)) / 537 sectors) & 0xf)); 538 } 539 else { 540 #endif 541 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 542 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 543 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 544 ATA_IDX_OUTB(ch, ATA_DRIVE, 545 ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) | 546 ((request->u.ata.lba >> 24) & 0x0f)); 547 #ifndef ATA_CAM 548 } 549 #endif 550 } 551 } 552 553 static void 554 ata_intel_31244_reset(device_t dev) 555 { 556 if (ata_sata_phy_reset(dev, -1, 1)) 557 ata_generic_reset(dev); 558 } 559 560 ATA_DECLARE_DRIVER(ata_intel); 561 MODULE_DEPEND(ata_intel, ata_ahci, 1, 1, 1); 562