1 /*- 2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/module.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/ata.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/malloc.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 #include <sys/sema.h> 41 #include <sys/taskqueue.h> 42 #include <vm/uma.h> 43 #include <machine/stdarg.h> 44 #include <machine/resource.h> 45 #include <machine/bus.h> 46 #include <sys/rman.h> 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcireg.h> 49 #include <dev/ata/ata-all.h> 50 #include <dev/ata/ata-pci.h> 51 #include <ata_if.h> 52 53 /* local prototypes */ 54 static int ata_intel_chipinit(device_t dev); 55 static int ata_intel_chipdeinit(device_t dev); 56 static int ata_intel_ch_attach(device_t dev); 57 static void ata_intel_reset(device_t dev); 58 static int ata_intel_old_setmode(device_t dev, int target, int mode); 59 static int ata_intel_new_setmode(device_t dev, int target, int mode); 60 static int ata_intel_sch_setmode(device_t dev, int target, int mode); 61 static int ata_intel_sata_getrev(device_t dev, int target); 62 static int ata_intel_sata_status(device_t dev); 63 static int ata_intel_sata_ahci_read(device_t dev, int port, 64 int reg, u_int32_t *result); 65 static int ata_intel_sata_cscr_read(device_t dev, int port, 66 int reg, u_int32_t *result); 67 static int ata_intel_sata_sidpr_read(device_t dev, int port, 68 int reg, u_int32_t *result); 69 static int ata_intel_sata_ahci_write(device_t dev, int port, 70 int reg, u_int32_t result); 71 static int ata_intel_sata_cscr_write(device_t dev, int port, 72 int reg, u_int32_t result); 73 static int ata_intel_sata_sidpr_write(device_t dev, int port, 74 int reg, u_int32_t result); 75 static int ata_intel_sata_sidpr_test(device_t dev); 76 static int ata_intel_31244_ch_attach(device_t dev); 77 static int ata_intel_31244_ch_detach(device_t dev); 78 static int ata_intel_31244_status(device_t dev); 79 static void ata_intel_31244_tf_write(struct ata_request *request); 80 static void ata_intel_31244_reset(device_t dev); 81 82 /* misc defines */ 83 #define INTEL_AHCI 1 84 #define INTEL_ICH5 2 85 #define INTEL_6CH 4 86 #define INTEL_6CH2 8 87 #define INTEL_ICH7 16 88 89 struct ata_intel_data { 90 struct mtx lock; 91 u_char smap[4]; 92 }; 93 94 #define ATA_INTEL_SMAP(ctlr, ch) \ 95 &((struct ata_intel_data *)((ctlr)->chipset_data))->smap[(ch)->unit * 2] 96 #define ATA_INTEL_LOCK(ctlr) \ 97 mtx_lock(&((struct ata_intel_data *)((ctlr)->chipset_data))->lock) 98 #define ATA_INTEL_UNLOCK(ctlr) \ 99 mtx_unlock(&((struct ata_intel_data *)((ctlr)->chipset_data))->lock) 100 101 /* 102 * Intel chipset support functions 103 */ 104 static int 105 ata_intel_probe(device_t dev) 106 { 107 struct ata_pci_controller *ctlr = device_get_softc(dev); 108 static const struct ata_chip_id ids[] = 109 {{ ATA_I82371FB, 0, 0, 2, ATA_WDMA2, "PIIX" }, 110 { ATA_I82371SB, 0, 0, 2, ATA_WDMA2, "PIIX3" }, 111 { ATA_I82371AB, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 112 { ATA_I82443MX, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 113 { ATA_I82451NX, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 114 { ATA_I82801AB, 0, 0, 2, ATA_UDMA2, "ICH0" }, 115 { ATA_I82801AA, 0, 0, 2, ATA_UDMA4, "ICH" }, 116 { ATA_I82372FB, 0, 0, 2, ATA_UDMA4, "ICH" }, 117 { ATA_I82801BA, 0, 0, 2, ATA_UDMA5, "ICH2" }, 118 { ATA_I82801BA_1, 0, 0, 2, ATA_UDMA5, "ICH2" }, 119 { ATA_I82801CA, 0, 0, 2, ATA_UDMA5, "ICH3" }, 120 { ATA_I82801CA_1, 0, 0, 2, ATA_UDMA5, "ICH3" }, 121 { ATA_I82801DB, 0, 0, 2, ATA_UDMA5, "ICH4" }, 122 { ATA_I82801DB_1, 0, 0, 2, ATA_UDMA5, "ICH4" }, 123 { ATA_I82801EB, 0, 0, 2, ATA_UDMA5, "ICH5" }, 124 { ATA_I82801EB_S1, 0, INTEL_ICH5, 2, ATA_SA150, "ICH5" }, 125 { ATA_I82801EB_R1, 0, INTEL_ICH5, 2, ATA_SA150, "ICH5" }, 126 { ATA_I6300ESB, 0, 0, 2, ATA_UDMA5, "6300ESB" }, 127 { ATA_I6300ESB_S1, 0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" }, 128 { ATA_I6300ESB_R1, 0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" }, 129 { ATA_I82801FB, 0, 0, 2, ATA_UDMA5, "ICH6" }, 130 { ATA_I82801FB_S1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6" }, 131 { ATA_I82801FB_R1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6" }, 132 { ATA_I82801FBM, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6M" }, 133 { ATA_I82801GB, 0, 0, 1, ATA_UDMA5, "ICH7" }, 134 { ATA_I82801GB_S1, 0, INTEL_ICH7, 0, ATA_SA300, "ICH7" }, 135 { ATA_I82801GB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" }, 136 { ATA_I82801GB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" }, 137 { ATA_I82801GBM_S1, 0, INTEL_ICH7, 0, ATA_SA150, "ICH7M" }, 138 { ATA_I82801GBM_R1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" }, 139 { ATA_I82801GBM_AH, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" }, 140 { ATA_I63XXESB2, 0, 0, 1, ATA_UDMA5, "63XXESB2" }, 141 { ATA_I63XXESB2_S1, 0, 0, 0, ATA_SA300, "63XXESB2" }, 142 { ATA_I63XXESB2_S2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 143 { ATA_I63XXESB2_R1, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 144 { ATA_I63XXESB2_R2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 145 { ATA_I82801HB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH8" }, 146 { ATA_I82801HB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH8" }, 147 { ATA_I82801HB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 148 { ATA_I82801HB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 149 { ATA_I82801HB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 150 { ATA_I82801HBM, 0, 0, 1, ATA_UDMA5, "ICH8M" }, 151 { ATA_I82801HBM_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH8M" }, 152 { ATA_I82801HBM_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" }, 153 { ATA_I82801HBM_S3, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" }, 154 { ATA_I82801IB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH9" }, 155 { ATA_I82801IB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9" }, 156 { ATA_I82801IB_S3, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9" }, 157 { ATA_I82801IB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 158 { ATA_I82801IB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 159 { ATA_I82801IB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 160 { ATA_I82801IBM_S1, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9M" }, 161 { ATA_I82801IBM_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9M" }, 162 { ATA_I82801IBM_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9M" }, 163 { ATA_I82801IBM_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9M" }, 164 { ATA_I82801JIB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, 165 { ATA_I82801JIB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 166 { ATA_I82801JIB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 167 { ATA_I82801JIB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, 168 { ATA_I82801JD_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, 169 { ATA_I82801JD_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 170 { ATA_I82801JD_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 171 { ATA_I82801JD_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, 172 { ATA_I82801JI_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, 173 { ATA_I82801JI_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 174 { ATA_I82801JI_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 175 { ATA_I82801JI_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, 176 { ATA_5Series_S1, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 177 { ATA_5Series_S2, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 178 { ATA_5Series_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 179 { ATA_5Series_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 180 { ATA_5Series_R1, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 181 { ATA_5Series_S3, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 182 { ATA_5Series_S4, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 183 { ATA_5Series_AH3, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 184 { ATA_5Series_R2, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 185 { ATA_5Series_S5, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 186 { ATA_5Series_S6, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 187 { ATA_5Series_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 188 { ATA_CPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Cougar Point" }, 189 { ATA_CPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Cougar Point" }, 190 { ATA_CPT_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, 191 { ATA_CPT_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, 192 { ATA_CPT_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, 193 { ATA_CPT_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, 194 { ATA_CPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" }, 195 { ATA_CPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" }, 196 { ATA_PBG_S1, 0, INTEL_6CH, 0, ATA_SA300, "Patsburg" }, 197 { ATA_PBG_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" }, 198 { ATA_PBG_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" }, 199 { ATA_PBG_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" }, 200 { ATA_PBG_R3, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" }, 201 { ATA_PBG_S2, 0, INTEL_6CH2, 0, ATA_SA300, "Patsburg" }, 202 { ATA_PPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Panther Point" }, 203 { ATA_PPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Panther Point" }, 204 { ATA_PPT_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 205 { ATA_PPT_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 206 { ATA_PPT_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 207 { ATA_PPT_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 208 { ATA_PPT_R3, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 209 { ATA_PPT_R4, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 210 { ATA_PPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Panther Point" }, 211 { ATA_PPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Panther Point" }, 212 { ATA_PPT_R5, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 213 { ATA_PPT_R6, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 214 { ATA_AVOTON_S1, 0, INTEL_6CH, 0, ATA_SA300, "Avoton" }, 215 { ATA_AVOTON_S2, 0, INTEL_6CH, 0, ATA_SA300, "Avoton" }, 216 { ATA_AVOTON_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Avoton" }, 217 { ATA_AVOTON_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Avoton" }, 218 { ATA_LPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Lynx Point" }, 219 { ATA_LPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Lynx Point" }, 220 { ATA_LPT_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, 221 { ATA_LPT_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, 222 { ATA_LPT_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, 223 { ATA_LPT_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, 224 { ATA_LPT_R3, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, 225 { ATA_LPT_R4, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, 226 { ATA_LPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point" }, 227 { ATA_LPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point" }, 228 { ATA_LPT_R5, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, 229 { ATA_LPT_R6, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, 230 { ATA_WCPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Wildcat Point" }, 231 { ATA_WCPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Wildcat Point" }, 232 { ATA_WCPT_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Wildcat Point" }, 233 { ATA_WCPT_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "Wildcat Point" }, 234 { ATA_WCPT_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Wildcat Point" }, 235 { ATA_WCPT_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Wildcat Point" }, 236 { ATA_WCPT_R3, 0, INTEL_AHCI, 0, ATA_SA300, "Wildcat Point" }, 237 { ATA_WCPT_R4, 0, INTEL_AHCI, 0, ATA_SA300, "Wildcat Point" }, 238 { ATA_WCPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Wildcat Point" }, 239 { ATA_WCPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Wildcat Point" }, 240 { ATA_WCPT_R5, 0, INTEL_AHCI, 0, ATA_SA300, "Wildcat Point" }, 241 { ATA_WCPT_R6, 0, INTEL_AHCI, 0, ATA_SA300, "Wildcat Point" }, 242 { ATA_WELLS_S1, 0, INTEL_6CH, 0, ATA_SA300, "Wellsburg" }, 243 { ATA_WELLS_S2, 0, INTEL_6CH2, 0, ATA_SA300, "Wellsburg" }, 244 { ATA_WELLS_S3, 0, INTEL_6CH, 0, ATA_SA300, "Wellsburg" }, 245 { ATA_WELLS_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Wellsburg" }, 246 { ATA_LPTLP_S1, 0, INTEL_6CH, 0, ATA_SA300, "Lynx Point-LP" }, 247 { ATA_LPTLP_S2, 0, INTEL_6CH, 0, ATA_SA300, "Lynx Point-LP" }, 248 { ATA_LPTLP_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point-LP" }, 249 { ATA_LPTLP_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point-LP" }, 250 { ATA_I31244, 0, 0, 2, ATA_SA150, "31244" }, 251 { ATA_ISCH, 0, 0, 1, ATA_UDMA5, "SCH" }, 252 { ATA_DH89XXCC, 0, INTEL_AHCI, 0, ATA_SA300, "DH89xxCC" }, 253 { ATA_COLETOCRK_S1, 0, INTEL_6CH2, 0, ATA_SA300, "COLETOCRK" }, 254 { ATA_COLETOCRK_S2, 0, INTEL_6CH2, 0, ATA_SA300, "COLETOCRK" }, 255 { ATA_COLETOCRK_AH1,0, INTEL_AHCI, 0, ATA_SA300, "COLETOCRK" }, 256 { 0, 0, 0, 0, 0, 0}}; 257 258 if (pci_get_vendor(dev) != ATA_INTEL_ID) 259 return ENXIO; 260 261 if (!(ctlr->chip = ata_match_chip(dev, ids))) 262 return ENXIO; 263 264 ata_set_desc(dev); 265 ctlr->chipinit = ata_intel_chipinit; 266 ctlr->chipdeinit = ata_intel_chipdeinit; 267 return (BUS_PROBE_DEFAULT); 268 } 269 270 static int 271 ata_intel_chipinit(device_t dev) 272 { 273 struct ata_pci_controller *ctlr = device_get_softc(dev); 274 struct ata_intel_data *data; 275 276 if (ata_setup_interrupt(dev, ata_generic_intr)) 277 return ENXIO; 278 279 data = malloc(sizeof(struct ata_intel_data), M_ATAPCI, M_WAITOK | M_ZERO); 280 mtx_init(&data->lock, "Intel SATA lock", NULL, MTX_DEF); 281 ctlr->chipset_data = (void *)data; 282 283 /* good old PIIX needs special treatment (not implemented) */ 284 if (ctlr->chip->chipid == ATA_I82371FB) { 285 ctlr->setmode = ata_intel_old_setmode; 286 } 287 288 /* the intel 31244 needs special care if in DPA mode */ 289 else if (ctlr->chip->chipid == ATA_I31244) { 290 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) { 291 ctlr->r_type2 = SYS_RES_MEMORY; 292 ctlr->r_rid2 = PCIR_BAR(0); 293 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 294 &ctlr->r_rid2, 295 RF_ACTIVE))) 296 return ENXIO; 297 ctlr->channels = 4; 298 ctlr->ch_attach = ata_intel_31244_ch_attach; 299 ctlr->ch_detach = ata_intel_31244_ch_detach; 300 ctlr->reset = ata_intel_31244_reset; 301 } 302 ctlr->setmode = ata_sata_setmode; 303 ctlr->getrev = ata_sata_getrev; 304 } 305 /* SCH */ 306 else if (ctlr->chip->chipid == ATA_ISCH) { 307 ctlr->channels = 1; 308 ctlr->ch_attach = ata_intel_ch_attach; 309 ctlr->ch_detach = ata_pci_ch_detach; 310 ctlr->setmode = ata_intel_sch_setmode; 311 } 312 /* non SATA intel chips goes here */ 313 else if (ctlr->chip->max_dma < ATA_SA150) { 314 ctlr->channels = ctlr->chip->cfg2; 315 ctlr->ch_attach = ata_intel_ch_attach; 316 ctlr->ch_detach = ata_pci_ch_detach; 317 ctlr->setmode = ata_intel_new_setmode; 318 } 319 320 /* SATA parts can be either compat or AHCI */ 321 else { 322 /* force all ports active "the legacy way" */ 323 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f, 2); 324 325 ctlr->ch_attach = ata_intel_ch_attach; 326 ctlr->ch_detach = ata_pci_ch_detach; 327 ctlr->reset = ata_intel_reset; 328 329 /* 330 * if we have AHCI capability and AHCI or RAID mode enabled 331 * in BIOS we try for AHCI mode 332 */ 333 if ((ctlr->chip->cfg1 & INTEL_AHCI) && 334 (pci_read_config(dev, 0x90, 1) & 0xc0) && 335 (ata_ahci_chipinit(dev) != ENXIO)) 336 return 0; 337 338 /* BAR(5) may point to SATA interface registers */ 339 if ((ctlr->chip->cfg1 & INTEL_ICH7)) { 340 ctlr->r_type2 = SYS_RES_MEMORY; 341 ctlr->r_rid2 = PCIR_BAR(5); 342 ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 343 &ctlr->r_rid2, RF_ACTIVE); 344 if (ctlr->r_res2 != NULL) { 345 /* Set SCRAE bit to enable registers access. */ 346 pci_write_config(dev, 0x94, 347 pci_read_config(dev, 0x94, 4) | (1 << 9), 4); 348 /* Set Ports Implemented register bits. */ 349 ATA_OUTL(ctlr->r_res2, 0x0C, 350 ATA_INL(ctlr->r_res2, 0x0C) | 0xf); 351 } 352 /* Skip BAR(5) on ICH8M Apples, system locks up on access. */ 353 } else if (ctlr->chip->chipid != ATA_I82801HBM_S1 || 354 pci_get_subvendor(dev) != 0x106b) { 355 ctlr->r_type2 = SYS_RES_IOPORT; 356 ctlr->r_rid2 = PCIR_BAR(5); 357 ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 358 &ctlr->r_rid2, RF_ACTIVE); 359 } 360 if (ctlr->r_res2 != NULL || 361 (ctlr->chip->cfg1 & INTEL_ICH5)) 362 ctlr->getrev = ata_intel_sata_getrev; 363 ctlr->setmode = ata_sata_setmode; 364 } 365 return 0; 366 } 367 368 static int 369 ata_intel_chipdeinit(device_t dev) 370 { 371 struct ata_pci_controller *ctlr = device_get_softc(dev); 372 struct ata_intel_data *data; 373 374 data = ctlr->chipset_data; 375 mtx_destroy(&data->lock); 376 free(data, M_ATAPCI); 377 ctlr->chipset_data = NULL; 378 return (0); 379 } 380 381 static int 382 ata_intel_ch_attach(device_t dev) 383 { 384 struct ata_pci_controller *ctlr; 385 struct ata_channel *ch; 386 u_char *smap; 387 u_int map; 388 389 /* setup the usual register normal pci style */ 390 if (ata_pci_ch_attach(dev)) 391 return (ENXIO); 392 393 ctlr = device_get_softc(device_get_parent(dev)); 394 ch = device_get_softc(dev); 395 396 /* if r_res2 is valid it points to SATA interface registers */ 397 if (ctlr->r_res2) { 398 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 399 ch->r_io[ATA_IDX_ADDR].offset = 0x00; 400 ch->r_io[ATA_IDX_DATA].res = ctlr->r_res2; 401 ch->r_io[ATA_IDX_DATA].offset = 0x04; 402 } 403 404 ch->flags |= ATA_ALWAYS_DMASTAT; 405 if (ctlr->chip->max_dma >= ATA_SA150) { 406 smap = ATA_INTEL_SMAP(ctlr, ch); 407 map = pci_read_config(device_get_parent(dev), 0x90, 1); 408 if (ctlr->chip->cfg1 & INTEL_ICH5) { 409 map &= 0x07; 410 if ((map & 0x04) == 0) { 411 ch->flags |= ATA_SATA; 412 ch->flags |= ATA_NO_SLAVE; 413 smap[0] = (map & 0x01) ^ ch->unit; 414 smap[1] = 0; 415 } else if ((map & 0x02) == 0 && ch->unit == 0) { 416 ch->flags |= ATA_SATA; 417 smap[0] = (map & 0x01) ? 1 : 0; 418 smap[1] = (map & 0x01) ? 0 : 1; 419 } else if ((map & 0x02) != 0 && ch->unit == 1) { 420 ch->flags |= ATA_SATA; 421 smap[0] = (map & 0x01) ? 1 : 0; 422 smap[1] = (map & 0x01) ? 0 : 1; 423 } 424 } else if (ctlr->chip->cfg1 & INTEL_6CH2) { 425 ch->flags |= ATA_SATA; 426 ch->flags |= ATA_NO_SLAVE; 427 smap[0] = (ch->unit == 0) ? 0 : 1; 428 smap[1] = 0; 429 } else { 430 map &= 0x03; 431 if (map == 0x00) { 432 ch->flags |= ATA_SATA; 433 smap[0] = (ch->unit == 0) ? 0 : 1; 434 smap[1] = (ch->unit == 0) ? 2 : 3; 435 } else if (map == 0x02 && ch->unit == 0) { 436 ch->flags |= ATA_SATA; 437 smap[0] = 0; 438 smap[1] = 2; 439 } else if (map == 0x01 && ch->unit == 1) { 440 ch->flags |= ATA_SATA; 441 smap[0] = 1; 442 smap[1] = 3; 443 } 444 } 445 if (ch->flags & ATA_SATA) { 446 if ((ctlr->chip->cfg1 & INTEL_ICH5)) { 447 ch->hw.pm_read = ata_intel_sata_cscr_read; 448 ch->hw.pm_write = ata_intel_sata_cscr_write; 449 } else if (ctlr->r_res2) { 450 if ((ctlr->chip->cfg1 & INTEL_ICH7)) { 451 ch->hw.pm_read = ata_intel_sata_ahci_read; 452 ch->hw.pm_write = ata_intel_sata_ahci_write; 453 } else if (ata_intel_sata_sidpr_test(dev)) { 454 ch->hw.pm_read = ata_intel_sata_sidpr_read; 455 ch->hw.pm_write = ata_intel_sata_sidpr_write; 456 }; 457 } 458 if (ch->hw.pm_write != NULL) { 459 ch->flags |= ATA_PERIODIC_POLL; 460 ch->hw.status = ata_intel_sata_status; 461 ata_sata_scr_write(ch, 0, 462 ATA_SERROR, 0xffffffff); 463 if ((ch->flags & ATA_NO_SLAVE) == 0) { 464 ata_sata_scr_write(ch, 1, 465 ATA_SERROR, 0xffffffff); 466 } 467 } 468 } else 469 ctlr->setmode = ata_intel_new_setmode; 470 } else if (ctlr->chip->chipid != ATA_ISCH) 471 ch->flags |= ATA_CHECKS_CABLE; 472 return (0); 473 } 474 475 static void 476 ata_intel_reset(device_t dev) 477 { 478 device_t parent = device_get_parent(dev); 479 struct ata_pci_controller *ctlr = device_get_softc(parent); 480 struct ata_channel *ch = device_get_softc(dev); 481 int mask, pshift, timeout, devs; 482 u_char *smap; 483 uint16_t pcs; 484 485 /* In combined mode, skip SATA stuff for PATA channel. */ 486 if ((ch->flags & ATA_SATA) == 0) 487 return (ata_generic_reset(dev)); 488 489 /* Do hard-reset on respective SATA ports. */ 490 smap = ATA_INTEL_SMAP(ctlr, ch); 491 mask = 1 << smap[0]; 492 if ((ch->flags & ATA_NO_SLAVE) == 0) 493 mask |= (1 << smap[1]); 494 pci_write_config(parent, 0x92, 495 pci_read_config(parent, 0x92, 2) & ~mask, 2); 496 DELAY(10); 497 pci_write_config(parent, 0x92, 498 pci_read_config(parent, 0x92, 2) | mask, 2); 499 500 /* Wait up to 1 sec for "connect well". */ 501 if (ctlr->chip->cfg1 & (INTEL_6CH | INTEL_6CH2)) 502 pshift = 8; 503 else 504 pshift = 4; 505 for (timeout = 0; timeout < 100 ; timeout++) { 506 pcs = (pci_read_config(parent, 0x92, 2) >> pshift) & mask; 507 if ((pcs == mask) && (ATA_IDX_INB(ch, ATA_STATUS) != 0xff)) 508 break; 509 ata_udelay(10000); 510 } 511 512 if (bootverbose) 513 device_printf(dev, "SATA reset: ports status=0x%02x\n", pcs); 514 /* If any device found, do soft-reset. */ 515 if (ch->hw.pm_read != NULL) { 516 devs = ata_sata_phy_reset(dev, 0, 2) ? ATA_ATA_MASTER : 0; 517 if ((ch->flags & ATA_NO_SLAVE) == 0) 518 devs |= ata_sata_phy_reset(dev, 1, 2) ? 519 ATA_ATA_SLAVE : 0; 520 } else { 521 devs = (pcs & (1 << smap[0])) ? ATA_ATA_MASTER : 0; 522 if ((ch->flags & ATA_NO_SLAVE) == 0) 523 devs |= (pcs & (1 << smap[1])) ? 524 ATA_ATA_SLAVE : 0; 525 } 526 if (devs) { 527 ata_generic_reset(dev); 528 /* Reset may give fake slave when only ATAPI master present. */ 529 ch->devices &= (devs | (devs * ATA_ATAPI_MASTER)); 530 } else 531 ch->devices = 0; 532 } 533 534 static int 535 ata_intel_old_setmode(device_t dev, int target, int mode) 536 { 537 device_t parent = device_get_parent(dev); 538 struct ata_pci_controller *ctlr = device_get_softc(parent); 539 540 mode = min(mode, ctlr->chip->max_dma); 541 return (mode); 542 } 543 544 static int 545 ata_intel_new_setmode(device_t dev, int target, int mode) 546 { 547 device_t parent = device_get_parent(dev); 548 struct ata_pci_controller *ctlr = device_get_softc(parent); 549 struct ata_channel *ch = device_get_softc(dev); 550 int devno = (ch->unit << 1) + target; 551 int piomode; 552 u_int32_t reg40 = pci_read_config(parent, 0x40, 4); 553 u_int8_t reg44 = pci_read_config(parent, 0x44, 1); 554 u_int8_t reg48 = pci_read_config(parent, 0x48, 1); 555 u_int16_t reg4a = pci_read_config(parent, 0x4a, 2); 556 u_int16_t reg54 = pci_read_config(parent, 0x54, 2); 557 u_int32_t mask40 = 0, new40 = 0; 558 u_int8_t mask44 = 0, new44 = 0; 559 static const uint8_t timings[] = 560 { 0x00, 0x00, 0x10, 0x21, 0x23, 0x00, 0x21, 0x23 }; 561 static const uint8_t utimings[] = 562 { 0x00, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02 }; 563 564 /* In combined mode, skip PATA stuff for SATA channel. */ 565 if (ch->flags & ATA_SATA) 566 return (ata_sata_setmode(dev, target, mode)); 567 568 mode = min(mode, ctlr->chip->max_dma); 569 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 570 !(reg54 & (0x10 << devno))) { 571 ata_print_cable(dev, "controller"); 572 mode = ATA_UDMA2; 573 } 574 /* Enable/disable UDMA and set timings. */ 575 if (mode >= ATA_UDMA0) { 576 pci_write_config(parent, 0x48, reg48 | (0x0001 << devno), 2); 577 pci_write_config(parent, 0x4a, 578 (reg4a & ~(0x3 << (devno << 2))) | 579 (utimings[mode & ATA_MODE_MASK] << (devno<<2)), 2); 580 piomode = ATA_PIO4; 581 } else { 582 pci_write_config(parent, 0x48, reg48 & ~(0x0001 << devno), 2); 583 pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (devno << 2))),2); 584 piomode = mode; 585 } 586 reg54 |= 0x0400; 587 /* Set UDMA reference clock (33/66/133MHz). */ 588 reg54 &= ~(0x1001 << devno); 589 if (mode >= ATA_UDMA5) 590 reg54 |= (0x1000 << devno); 591 else if (mode >= ATA_UDMA3) 592 reg54 |= (0x1 << devno); 593 pci_write_config(parent, 0x54, reg54, 2); 594 /* Allow PIO/WDMA timing controls. */ 595 reg40 &= ~0x00ff00ff; 596 reg40 |= 0x40774077; 597 /* Set PIO/WDMA timings. */ 598 if (target == 0) { 599 mask40 = 0x3300; 600 new40 = timings[ata_mode2idx(piomode)] << 8; 601 } else { 602 mask44 = 0x0f; 603 new44 = ((timings[ata_mode2idx(piomode)] & 0x30) >> 2) | 604 (timings[ata_mode2idx(piomode)] & 0x03); 605 } 606 if (ch->unit) { 607 mask40 <<= 16; 608 new40 <<= 16; 609 mask44 <<= 4; 610 new44 <<= 4; 611 } 612 pci_write_config(parent, 0x40, (reg40 & ~mask40) | new40, 4); 613 pci_write_config(parent, 0x44, (reg44 & ~mask44) | new44, 1); 614 return (mode); 615 } 616 617 static int 618 ata_intel_sch_setmode(device_t dev, int target, int mode) 619 { 620 device_t parent = device_get_parent(dev); 621 struct ata_pci_controller *ctlr = device_get_softc(parent); 622 u_int8_t dtim = 0x80 + (target << 2); 623 u_int32_t tim = pci_read_config(parent, dtim, 4); 624 int piomode; 625 626 mode = min(mode, ctlr->chip->max_dma); 627 if (mode >= ATA_UDMA0) { 628 tim |= (0x1 << 31); 629 tim &= ~(0x7 << 16); 630 tim |= ((mode & ATA_MODE_MASK) << 16); 631 piomode = ATA_PIO4; 632 } else if (mode >= ATA_WDMA0) { 633 tim &= ~(0x1 << 31); 634 tim &= ~(0x3 << 8); 635 tim |= ((mode & ATA_MODE_MASK) << 8); 636 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 : 637 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4; 638 } else 639 piomode = mode; 640 tim &= ~(0x7); 641 tim |= (piomode & 0x7); 642 pci_write_config(parent, dtim, tim, 4); 643 return (mode); 644 } 645 646 static int 647 ata_intel_sata_getrev(device_t dev, int target) 648 { 649 struct ata_channel *ch = device_get_softc(dev); 650 uint32_t status; 651 652 if (ata_sata_scr_read(ch, target, ATA_SSTATUS, &status) == 0) 653 return ((status & 0x0f0) >> 4); 654 return (0xff); 655 } 656 657 static int 658 ata_intel_sata_status(device_t dev) 659 { 660 struct ata_channel *ch = device_get_softc(dev); 661 662 ata_sata_phy_check_events(dev, 0); 663 if ((ch->flags & ATA_NO_SLAVE) == 0) 664 ata_sata_phy_check_events(dev, 1); 665 666 return ata_pci_status(dev); 667 } 668 669 static int 670 ata_intel_sata_ahci_read(device_t dev, int port, int reg, u_int32_t *result) 671 { 672 struct ata_pci_controller *ctlr; 673 struct ata_channel *ch; 674 device_t parent; 675 u_char *smap; 676 int offset; 677 678 parent = device_get_parent(dev); 679 ctlr = device_get_softc(parent); 680 ch = device_get_softc(dev); 681 port = (port == 1) ? 1 : 0; 682 smap = ATA_INTEL_SMAP(ctlr, ch); 683 offset = 0x100 + smap[port] * 0x80; 684 switch (reg) { 685 case ATA_SSTATUS: 686 reg = 0x28; 687 break; 688 case ATA_SCONTROL: 689 reg = 0x2c; 690 break; 691 case ATA_SERROR: 692 reg = 0x30; 693 break; 694 default: 695 return (EINVAL); 696 } 697 *result = ATA_INL(ctlr->r_res2, offset + reg); 698 return (0); 699 } 700 701 static int 702 ata_intel_sata_cscr_read(device_t dev, int port, int reg, u_int32_t *result) 703 { 704 struct ata_pci_controller *ctlr; 705 struct ata_channel *ch; 706 device_t parent; 707 u_char *smap; 708 709 parent = device_get_parent(dev); 710 ctlr = device_get_softc(parent); 711 ch = device_get_softc(dev); 712 smap = ATA_INTEL_SMAP(ctlr, ch); 713 port = (port == 1) ? 1 : 0; 714 switch (reg) { 715 case ATA_SSTATUS: 716 reg = 0; 717 break; 718 case ATA_SERROR: 719 reg = 1; 720 break; 721 case ATA_SCONTROL: 722 reg = 2; 723 break; 724 default: 725 return (EINVAL); 726 } 727 ATA_INTEL_LOCK(ctlr); 728 pci_write_config(parent, 0xa0, 729 0x50 + smap[port] * 0x10 + reg * 4, 4); 730 *result = pci_read_config(parent, 0xa4, 4); 731 ATA_INTEL_UNLOCK(ctlr); 732 return (0); 733 } 734 735 static int 736 ata_intel_sata_sidpr_read(device_t dev, int port, int reg, u_int32_t *result) 737 { 738 struct ata_pci_controller *ctlr; 739 struct ata_channel *ch; 740 device_t parent; 741 742 parent = device_get_parent(dev); 743 ctlr = device_get_softc(parent); 744 ch = device_get_softc(dev); 745 port = (port == 1) ? 1 : 0; 746 switch (reg) { 747 case ATA_SSTATUS: 748 reg = 0; 749 break; 750 case ATA_SCONTROL: 751 reg = 1; 752 break; 753 case ATA_SERROR: 754 reg = 2; 755 break; 756 default: 757 return (EINVAL); 758 } 759 ATA_INTEL_LOCK(ctlr); 760 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, ((ch->unit * 2 + port) << 8) + reg); 761 *result = ATA_IDX_INL(ch, ATA_IDX_DATA); 762 ATA_INTEL_UNLOCK(ctlr); 763 return (0); 764 } 765 766 static int 767 ata_intel_sata_ahci_write(device_t dev, int port, int reg, u_int32_t value) 768 { 769 struct ata_pci_controller *ctlr; 770 struct ata_channel *ch; 771 device_t parent; 772 u_char *smap; 773 int offset; 774 775 parent = device_get_parent(dev); 776 ctlr = device_get_softc(parent); 777 ch = device_get_softc(dev); 778 port = (port == 1) ? 1 : 0; 779 smap = ATA_INTEL_SMAP(ctlr, ch); 780 offset = 0x100 + smap[port] * 0x80; 781 switch (reg) { 782 case ATA_SSTATUS: 783 reg = 0x28; 784 break; 785 case ATA_SCONTROL: 786 reg = 0x2c; 787 break; 788 case ATA_SERROR: 789 reg = 0x30; 790 break; 791 default: 792 return (EINVAL); 793 } 794 ATA_OUTL(ctlr->r_res2, offset + reg, value); 795 return (0); 796 } 797 798 static int 799 ata_intel_sata_cscr_write(device_t dev, int port, int reg, u_int32_t value) 800 { 801 struct ata_pci_controller *ctlr; 802 struct ata_channel *ch; 803 device_t parent; 804 u_char *smap; 805 806 parent = device_get_parent(dev); 807 ctlr = device_get_softc(parent); 808 ch = device_get_softc(dev); 809 smap = ATA_INTEL_SMAP(ctlr, ch); 810 port = (port == 1) ? 1 : 0; 811 switch (reg) { 812 case ATA_SSTATUS: 813 reg = 0; 814 break; 815 case ATA_SERROR: 816 reg = 1; 817 break; 818 case ATA_SCONTROL: 819 reg = 2; 820 break; 821 default: 822 return (EINVAL); 823 } 824 ATA_INTEL_LOCK(ctlr); 825 pci_write_config(parent, 0xa0, 826 0x50 + smap[port] * 0x10 + reg * 4, 4); 827 pci_write_config(parent, 0xa4, value, 4); 828 ATA_INTEL_UNLOCK(ctlr); 829 return (0); 830 } 831 832 static int 833 ata_intel_sata_sidpr_write(device_t dev, int port, int reg, u_int32_t value) 834 { 835 struct ata_pci_controller *ctlr; 836 struct ata_channel *ch; 837 device_t parent; 838 839 parent = device_get_parent(dev); 840 ctlr = device_get_softc(parent); 841 ch = device_get_softc(dev); 842 port = (port == 1) ? 1 : 0; 843 switch (reg) { 844 case ATA_SSTATUS: 845 reg = 0; 846 break; 847 case ATA_SCONTROL: 848 reg = 1; 849 break; 850 case ATA_SERROR: 851 reg = 2; 852 break; 853 default: 854 return (EINVAL); 855 } 856 ATA_INTEL_LOCK(ctlr); 857 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, ((ch->unit * 2 + port) << 8) + reg); 858 ATA_IDX_OUTL(ch, ATA_IDX_DATA, value); 859 ATA_INTEL_UNLOCK(ctlr); 860 return (0); 861 } 862 863 static int 864 ata_intel_sata_sidpr_test(device_t dev) 865 { 866 struct ata_channel *ch = device_get_softc(dev); 867 int port; 868 uint32_t val; 869 870 port = (ch->flags & ATA_NO_SLAVE) ? 0 : 1; 871 for (; port >= 0; port--) { 872 ata_intel_sata_sidpr_read(dev, port, ATA_SCONTROL, &val); 873 if ((val & ATA_SC_IPM_MASK) == 874 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER)) 875 return (1); 876 val |= ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER; 877 ata_intel_sata_sidpr_write(dev, port, ATA_SCONTROL, val); 878 ata_intel_sata_sidpr_read(dev, port, ATA_SCONTROL, &val); 879 if ((val & ATA_SC_IPM_MASK) == 880 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER)) 881 return (1); 882 } 883 if (bootverbose) 884 device_printf(dev, 885 "SControl registers are not functional: %08x\n", val); 886 return (0); 887 } 888 889 static int 890 ata_intel_31244_ch_attach(device_t dev) 891 { 892 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 893 struct ata_channel *ch = device_get_softc(dev); 894 int i; 895 int ch_offset; 896 897 ata_pci_dmainit(dev); 898 899 ch_offset = 0x200 + ch->unit * 0x200; 900 901 for (i = ATA_DATA; i < ATA_MAX_RES; i++) 902 ch->r_io[i].res = ctlr->r_res2; 903 904 /* setup ATA registers */ 905 ch->r_io[ATA_DATA].offset = ch_offset + 0x00; 906 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06; 907 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08; 908 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c; 909 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; 910 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14; 911 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18; 912 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d; 913 ch->r_io[ATA_ERROR].offset = ch_offset + 0x04; 914 ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c; 915 ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28; 916 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29; 917 918 /* setup DMA registers */ 919 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100; 920 ch->r_io[ATA_SERROR].offset = ch_offset + 0x104; 921 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108; 922 923 /* setup SATA registers */ 924 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70; 925 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72; 926 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74; 927 928 ch->flags |= ATA_NO_SLAVE; 929 ch->flags |= ATA_SATA; 930 ata_pci_hw(dev); 931 ch->hw.status = ata_intel_31244_status; 932 ch->hw.tf_write = ata_intel_31244_tf_write; 933 934 /* enable PHY state change interrupt */ 935 ATA_OUTL(ctlr->r_res2, 0x4, 936 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3))); 937 return 0; 938 } 939 940 static int 941 ata_intel_31244_ch_detach(device_t dev) 942 { 943 944 ata_pci_dmafini(dev); 945 return (0); 946 } 947 948 static int 949 ata_intel_31244_status(device_t dev) 950 { 951 /* do we have any PHY events ? */ 952 ata_sata_phy_check_events(dev, -1); 953 954 /* any drive action to take care of ? */ 955 return ata_pci_status(dev); 956 } 957 958 static void 959 ata_intel_31244_tf_write(struct ata_request *request) 960 { 961 struct ata_channel *ch = device_get_softc(request->parent); 962 963 if (request->flags & ATA_R_48BIT) { 964 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature); 965 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count); 966 ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) | 967 (request->u.ata.lba & 0x00ff)); 968 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) | 969 ((request->u.ata.lba >> 8) & 0x00ff)); 970 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) | 971 ((request->u.ata.lba >> 16) & 0x00ff)); 972 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit)); 973 } 974 else { 975 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 976 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 977 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 978 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 979 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 980 ATA_IDX_OUTB(ch, ATA_DRIVE, 981 ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) | 982 ((request->u.ata.lba >> 24) & 0x0f)); 983 } 984 } 985 986 static void 987 ata_intel_31244_reset(device_t dev) 988 { 989 struct ata_channel *ch = device_get_softc(dev); 990 991 if (ata_sata_phy_reset(dev, -1, 1)) 992 ata_generic_reset(dev); 993 else 994 ch->devices = 0; 995 } 996 997 ATA_DECLARE_DRIVER(ata_intel); 998 MODULE_DEPEND(ata_intel, ata_ahci, 1, 1, 1); 999