1 /*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ata.h" 31 #include <sys/param.h> 32 #include <sys/module.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/ata.h> 36 #include <sys/bus.h> 37 #include <sys/endian.h> 38 #include <sys/malloc.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/sema.h> 42 #include <sys/taskqueue.h> 43 #include <vm/uma.h> 44 #include <machine/stdarg.h> 45 #include <machine/resource.h> 46 #include <machine/bus.h> 47 #include <sys/rman.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/ata/ata-all.h> 51 #include <dev/ata/ata-pci.h> 52 #include <ata_if.h> 53 54 /* local prototypes */ 55 static int ata_intel_chipinit(device_t dev); 56 static int ata_intel_ch_attach(device_t dev); 57 static void ata_intel_reset(device_t dev); 58 static int ata_intel_old_setmode(device_t dev, int target, int mode); 59 static int ata_intel_new_setmode(device_t dev, int target, int mode); 60 static int ata_intel_sch_setmode(device_t dev, int target, int mode); 61 static int ata_intel_sata_getrev(device_t dev, int target); 62 static int ata_intel_sata_status(device_t dev); 63 static int ata_intel_sata_cscr_read(device_t dev, int port, 64 int reg, u_int32_t *result); 65 static int ata_intel_sata_sidpr_read(device_t dev, int port, 66 int reg, u_int32_t *result); 67 static int ata_intel_sata_cscr_write(device_t dev, int port, 68 int reg, u_int32_t result); 69 static int ata_intel_sata_sidpr_write(device_t dev, int port, 70 int reg, u_int32_t result); 71 static int ata_intel_31244_ch_attach(device_t dev); 72 static int ata_intel_31244_ch_detach(device_t dev); 73 static int ata_intel_31244_status(device_t dev); 74 static void ata_intel_31244_tf_write(struct ata_request *request); 75 static void ata_intel_31244_reset(device_t dev); 76 77 /* misc defines */ 78 #define INTEL_AHCI 1 79 #define INTEL_ICH5 2 80 #define INTEL_6CH 4 81 #define INTEL_6CH2 8 82 83 /* 84 * Intel chipset support functions 85 */ 86 static int 87 ata_intel_probe(device_t dev) 88 { 89 struct ata_pci_controller *ctlr = device_get_softc(dev); 90 static struct ata_chip_id ids[] = 91 {{ ATA_I82371FB, 0, 0, 2, ATA_WDMA2, "PIIX" }, 92 { ATA_I82371SB, 0, 0, 2, ATA_WDMA2, "PIIX3" }, 93 { ATA_I82371AB, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 94 { ATA_I82443MX, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 95 { ATA_I82451NX, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 96 { ATA_I82801AB, 0, 0, 2, ATA_UDMA2, "ICH0" }, 97 { ATA_I82801AA, 0, 0, 2, ATA_UDMA4, "ICH" }, 98 { ATA_I82372FB, 0, 0, 2, ATA_UDMA4, "ICH" }, 99 { ATA_I82801BA, 0, 0, 2, ATA_UDMA5, "ICH2" }, 100 { ATA_I82801BA_1, 0, 0, 2, ATA_UDMA5, "ICH2" }, 101 { ATA_I82801CA, 0, 0, 2, ATA_UDMA5, "ICH3" }, 102 { ATA_I82801CA_1, 0, 0, 2, ATA_UDMA5, "ICH3" }, 103 { ATA_I82801DB, 0, 0, 2, ATA_UDMA5, "ICH4" }, 104 { ATA_I82801DB_1, 0, 0, 2, ATA_UDMA5, "ICH4" }, 105 { ATA_I82801EB, 0, 0, 2, ATA_UDMA5, "ICH5" }, 106 { ATA_I82801EB_S1, 0, INTEL_ICH5, 2, ATA_SA150, "ICH5" }, 107 { ATA_I82801EB_R1, 0, INTEL_ICH5, 2, ATA_SA150, "ICH5" }, 108 { ATA_I6300ESB, 0, 0, 2, ATA_UDMA5, "6300ESB" }, 109 { ATA_I6300ESB_S1, 0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" }, 110 { ATA_I6300ESB_R1, 0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" }, 111 { ATA_I82801FB, 0, 0, 2, ATA_UDMA5, "ICH6" }, 112 { ATA_I82801FB_S1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6" }, 113 { ATA_I82801FB_R1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6" }, 114 { ATA_I82801FBM, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6M" }, 115 { ATA_I82801GB, 0, 0, 1, ATA_UDMA5, "ICH7" }, 116 { ATA_I82801GB_S1, 0, 0, 0, ATA_SA300, "ICH7" }, 117 { ATA_I82801GB_R1, 0, 0, 0, ATA_SA300, "ICH7" }, 118 { ATA_I82801GB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" }, 119 { ATA_I82801GBM_S1, 0, 0, 0, ATA_SA150, "ICH7M" }, 120 { ATA_I82801GBM_R1, 0, 0, 0, ATA_SA150, "ICH7M" }, 121 { ATA_I82801GBM_AH, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" }, 122 { ATA_I63XXESB2, 0, 0, 1, ATA_UDMA5, "63XXESB2" }, 123 { ATA_I63XXESB2_S1, 0, 0, 0, ATA_SA300, "63XXESB2" }, 124 { ATA_I63XXESB2_S2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 125 { ATA_I63XXESB2_R1, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 126 { ATA_I63XXESB2_R2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 127 { ATA_I82801HB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH8" }, 128 { ATA_I82801HB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH8" }, 129 { ATA_I82801HB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 130 { ATA_I82801HB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 131 { ATA_I82801HB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 132 { ATA_I82801HBM, 0, 0, 1, ATA_UDMA5, "ICH8M" }, 133 { ATA_I82801HBM_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH8M" }, 134 { ATA_I82801HBM_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" }, 135 { ATA_I82801HBM_S3, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" }, 136 { ATA_I82801IB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH9" }, 137 { ATA_I82801IB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9" }, 138 { ATA_I82801IB_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 139 { ATA_I82801IB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 140 { ATA_I82801IB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 141 { ATA_I82801IB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 142 { ATA_I82801JIB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, 143 { ATA_I82801JIB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 144 { ATA_I82801JIB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 145 { ATA_I82801JIB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, 146 { ATA_I82801JD_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, 147 { ATA_I82801JD_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 148 { ATA_I82801JD_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 149 { ATA_I82801JD_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, 150 { ATA_I82801JI_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, 151 { ATA_I82801JI_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 152 { ATA_I82801JI_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 153 { ATA_I82801JI_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, 154 { ATA_5Series_S1, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 155 { ATA_5Series_S2, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 156 { ATA_5Series_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 157 { ATA_5Series_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 158 { ATA_5Series_R1, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 159 { ATA_5Series_S3, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 160 { ATA_5Series_S4, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 161 { ATA_5Series_AH3, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 162 { ATA_5Series_R2, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 163 { ATA_5Series_S5, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 164 { ATA_5Series_S6, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 165 { ATA_5Series_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 166 { ATA_CPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Cougar Point" }, 167 { ATA_CPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Cougar Point" }, 168 { ATA_CPT_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, 169 { ATA_CPT_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, 170 { ATA_CPT_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, 171 { ATA_CPT_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, 172 { ATA_CPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" }, 173 { ATA_CPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" }, 174 { ATA_I31244, 0, 0, 2, ATA_SA150, "31244" }, 175 { ATA_ISCH, 0, 0, 1, ATA_UDMA5, "SCH" }, 176 { 0, 0, 0, 0, 0, 0}}; 177 178 if (pci_get_vendor(dev) != ATA_INTEL_ID) 179 return ENXIO; 180 181 if (!(ctlr->chip = ata_match_chip(dev, ids))) 182 return ENXIO; 183 184 ata_set_desc(dev); 185 ctlr->chipinit = ata_intel_chipinit; 186 return (BUS_PROBE_DEFAULT); 187 } 188 189 static int 190 ata_intel_chipinit(device_t dev) 191 { 192 struct ata_pci_controller *ctlr = device_get_softc(dev); 193 194 if (ata_setup_interrupt(dev, ata_generic_intr)) 195 return ENXIO; 196 197 ctlr->chipset_data = NULL; 198 199 /* good old PIIX needs special treatment (not implemented) */ 200 if (ctlr->chip->chipid == ATA_I82371FB) { 201 ctlr->setmode = ata_intel_old_setmode; 202 } 203 204 /* the intel 31244 needs special care if in DPA mode */ 205 else if (ctlr->chip->chipid == ATA_I31244) { 206 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) { 207 ctlr->r_type2 = SYS_RES_MEMORY; 208 ctlr->r_rid2 = PCIR_BAR(0); 209 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 210 &ctlr->r_rid2, 211 RF_ACTIVE))) 212 return ENXIO; 213 ctlr->channels = 4; 214 ctlr->ch_attach = ata_intel_31244_ch_attach; 215 ctlr->ch_detach = ata_intel_31244_ch_detach; 216 ctlr->reset = ata_intel_31244_reset; 217 } 218 ctlr->setmode = ata_sata_setmode; 219 ctlr->getrev = ata_sata_getrev; 220 } 221 /* SCH */ 222 else if (ctlr->chip->chipid == ATA_ISCH) { 223 ctlr->channels = 1; 224 ctlr->ch_attach = ata_intel_ch_attach; 225 ctlr->ch_detach = ata_pci_ch_detach; 226 ctlr->setmode = ata_intel_sch_setmode; 227 } 228 /* non SATA intel chips goes here */ 229 else if (ctlr->chip->max_dma < ATA_SA150) { 230 ctlr->channels = ctlr->chip->cfg2; 231 ctlr->ch_attach = ata_intel_ch_attach; 232 ctlr->ch_detach = ata_pci_ch_detach; 233 ctlr->setmode = ata_intel_new_setmode; 234 } 235 236 /* SATA parts can be either compat or AHCI */ 237 else { 238 /* force all ports active "the legacy way" */ 239 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f, 2); 240 241 ctlr->ch_attach = ata_intel_ch_attach; 242 ctlr->ch_detach = ata_pci_ch_detach; 243 ctlr->reset = ata_intel_reset; 244 245 /* 246 * if we have AHCI capability and AHCI or RAID mode enabled 247 * in BIOS we try for AHCI mode 248 */ 249 if ((ctlr->chip->cfg1 & INTEL_AHCI) && 250 (pci_read_config(dev, 0x90, 1) & 0xc0) && 251 (ata_ahci_chipinit(dev) != ENXIO)) 252 return 0; 253 254 /* if BAR(5) is IO it should point to SATA interface registers */ 255 ctlr->r_type2 = SYS_RES_IOPORT; 256 ctlr->r_rid2 = PCIR_BAR(5); 257 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 258 &ctlr->r_rid2, RF_ACTIVE)) 259 || (ctlr->chip->cfg1 & INTEL_ICH5)) 260 ctlr->getrev = ata_intel_sata_getrev; 261 ctlr->setmode = ata_sata_setmode; 262 } 263 return 0; 264 } 265 266 static int 267 ata_intel_ch_attach(device_t dev) 268 { 269 struct ata_pci_controller *ctlr; 270 struct ata_channel *ch; 271 u_char *smap; 272 u_int map; 273 274 /* setup the usual register normal pci style */ 275 if (ata_pci_ch_attach(dev)) 276 return (ENXIO); 277 278 ctlr = device_get_softc(device_get_parent(dev)); 279 ch = device_get_softc(dev); 280 281 /* if r_res2 is valid it points to SATA interface registers */ 282 if (ctlr->r_res2) { 283 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 284 ch->r_io[ATA_IDX_ADDR].offset = 0x00; 285 ch->r_io[ATA_IDX_DATA].res = ctlr->r_res2; 286 ch->r_io[ATA_IDX_DATA].offset = 0x04; 287 } 288 289 ch->flags |= ATA_ALWAYS_DMASTAT; 290 if (ctlr->chip->max_dma >= ATA_SA150) { 291 smap = (u_char *)&ctlr->chipset_data + ch->unit * 2; 292 map = pci_read_config(device_get_parent(dev), 0x90, 1); 293 if (ctlr->chip->cfg1 & INTEL_ICH5) { 294 map &= 0x07; 295 if ((map & 0x04) == 0) { 296 ch->flags |= ATA_SATA; 297 ch->flags |= ATA_NO_SLAVE; 298 smap[0] = (map & 0x01) ^ ch->unit; 299 smap[1] = 0; 300 } else if ((map & 0x02) == 0 && ch->unit == 0) { 301 ch->flags |= ATA_SATA; 302 smap[0] = (map & 0x01) ? 1 : 0; 303 smap[1] = (map & 0x01) ? 0 : 1; 304 } else if ((map & 0x02) != 0 && ch->unit == 1) { 305 ch->flags |= ATA_SATA; 306 smap[0] = (map & 0x01) ? 1 : 0; 307 smap[1] = (map & 0x01) ? 0 : 1; 308 } 309 } else if (ctlr->chip->cfg1 & INTEL_6CH2) { 310 ch->flags |= ATA_SATA; 311 ch->flags |= ATA_NO_SLAVE; 312 smap[0] = (ch->unit == 0) ? 4 : 5; 313 smap[1] = 0; 314 } else { 315 map &= 0x03; 316 if (map == 0x00) { 317 ch->flags |= ATA_SATA; 318 smap[0] = (ch->unit == 0) ? 0 : 1; 319 smap[1] = (ch->unit == 0) ? 2 : 3; 320 } else if (map == 0x02 && ch->unit == 0) { 321 ch->flags |= ATA_SATA; 322 smap[0] = 0; 323 smap[1] = 2; 324 } else if (map == 0x01 && ch->unit == 1) { 325 ch->flags |= ATA_SATA; 326 smap[0] = 1; 327 smap[1] = 3; 328 } 329 } 330 if (ch->flags & ATA_SATA) { 331 if ((ctlr->chip->cfg1 & INTEL_ICH5)) { 332 ch->flags |= ATA_PERIODIC_POLL; 333 ch->hw.status = ata_intel_sata_status; 334 ch->hw.pm_read = ata_intel_sata_cscr_read; 335 ch->hw.pm_write = ata_intel_sata_cscr_write; 336 } else if (ctlr->r_res2) { 337 ch->flags |= ATA_PERIODIC_POLL; 338 ch->hw.status = ata_intel_sata_status; 339 ch->hw.pm_read = ata_intel_sata_sidpr_read; 340 ch->hw.pm_write = ata_intel_sata_sidpr_write; 341 } 342 if (ch->hw.pm_write != NULL) { 343 ata_sata_scr_write(ch, 0, 344 ATA_SERROR, 0xffffffff); 345 if ((ch->flags & ATA_NO_SLAVE) == 0) { 346 ata_sata_scr_write(ch, 1, 347 ATA_SERROR, 0xffffffff); 348 } 349 } 350 } else 351 ctlr->setmode = ata_intel_new_setmode; 352 } else if (ctlr->chip->chipid != ATA_ISCH) 353 ch->flags |= ATA_CHECKS_CABLE; 354 return (0); 355 } 356 357 static void 358 ata_intel_reset(device_t dev) 359 { 360 device_t parent = device_get_parent(dev); 361 struct ata_pci_controller *ctlr = device_get_softc(parent); 362 struct ata_channel *ch = device_get_softc(dev); 363 int mask, pmask, timeout, devs; 364 u_char *smap; 365 366 /* In combined mode, skip SATA stuff for PATA channel. */ 367 if ((ch->flags & ATA_SATA) == 0) 368 return (ata_generic_reset(dev)); 369 370 /* Do hard-reset on respective SATA ports. */ 371 smap = (u_char *)&ctlr->chipset_data + ch->unit * 2; 372 mask = 1 << smap[0]; 373 if ((ch->flags & ATA_NO_SLAVE) == 0) 374 mask |= (1 << smap[1]); 375 pci_write_config(parent, 0x92, 376 pci_read_config(parent, 0x92, 2) & ~mask, 2); 377 DELAY(10); 378 pci_write_config(parent, 0x92, 379 pci_read_config(parent, 0x92, 2) | mask, 2); 380 381 /* Wait up to 1 sec for "connect well". */ 382 if (ctlr->chip->cfg1 & (INTEL_6CH | INTEL_6CH2)) 383 pmask = mask << 8; 384 else 385 pmask = mask << 4; 386 for (timeout = 0; timeout < 100 ; timeout++) { 387 if (((pci_read_config(parent, 0x92, 2) & pmask) == pmask) && 388 (ATA_IDX_INB(ch, ATA_STATUS) != 0xff)) 389 break; 390 ata_udelay(10000); 391 } 392 393 /* If any device found, do soft-reset. */ 394 if (ch->hw.pm_read != NULL) { 395 devs = ata_sata_phy_reset(dev, 0, 2); 396 if ((ch->flags & ATA_NO_SLAVE) == 0) 397 devs += ata_sata_phy_reset(dev, 1, 2); 398 } else 399 devs = 1; 400 if (devs) 401 ata_generic_reset(dev); 402 else 403 ch->devices = 0; 404 } 405 406 static int 407 ata_intel_old_setmode(device_t dev, int target, int mode) 408 { 409 device_t parent = device_get_parent(dev); 410 struct ata_pci_controller *ctlr = device_get_softc(parent); 411 412 mode = min(mode, ctlr->chip->max_dma); 413 return (mode); 414 } 415 416 static int 417 ata_intel_new_setmode(device_t dev, int target, int mode) 418 { 419 device_t parent = device_get_parent(dev); 420 struct ata_pci_controller *ctlr = device_get_softc(parent); 421 struct ata_channel *ch = device_get_softc(dev); 422 int devno = (ch->unit << 1) + target; 423 int piomode; 424 u_int32_t reg40 = pci_read_config(parent, 0x40, 4); 425 u_int8_t reg44 = pci_read_config(parent, 0x44, 1); 426 u_int8_t reg48 = pci_read_config(parent, 0x48, 1); 427 u_int16_t reg4a = pci_read_config(parent, 0x4a, 2); 428 u_int16_t reg54 = pci_read_config(parent, 0x54, 2); 429 u_int32_t mask40 = 0, new40 = 0; 430 u_int8_t mask44 = 0, new44 = 0; 431 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x00, 0x21, 0x23 }; 432 u_int8_t utimings[] = { 0x00, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02 }; 433 434 /* In combined mode, skip PATA stuff for SATA channel. */ 435 if (ch->flags & ATA_SATA) 436 return (ata_sata_setmode(dev, target, mode)); 437 438 mode = min(mode, ctlr->chip->max_dma); 439 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 440 !(reg54 & (0x10 << devno))) { 441 ata_print_cable(dev, "controller"); 442 mode = ATA_UDMA2; 443 } 444 /* Enable/disable UDMA and set timings. */ 445 if (mode >= ATA_UDMA0) { 446 pci_write_config(parent, 0x48, reg48 | (0x0001 << devno), 2); 447 pci_write_config(parent, 0x4a, 448 (reg4a & ~(0x3 << (devno << 2))) | 449 (utimings[mode & ATA_MODE_MASK] << (devno<<2)), 2); 450 piomode = ATA_PIO4; 451 } else { 452 pci_write_config(parent, 0x48, reg48 & ~(0x0001 << devno), 2); 453 pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (devno << 2))),2); 454 piomode = mode; 455 } 456 reg54 |= 0x0400; 457 /* Set UDMA reference clock (33/66/133MHz). */ 458 reg54 &= ~(0x1001 << devno); 459 if (mode >= ATA_UDMA5) 460 reg54 |= (0x1000 << devno); 461 else if (mode >= ATA_UDMA3) 462 reg54 |= (0x1 << devno); 463 pci_write_config(parent, 0x54, reg54, 2); 464 /* Allow PIO/WDMA timing controls. */ 465 reg40 &= ~0x00ff00ff; 466 reg40 |= 0x40774077; 467 /* Set PIO/WDMA timings. */ 468 if (target == 0) { 469 mask40 = 0x3300; 470 new40 = timings[ata_mode2idx(piomode)] << 8; 471 } else { 472 mask44 = 0x0f; 473 new44 = ((timings[ata_mode2idx(piomode)] & 0x30) >> 2) | 474 (timings[ata_mode2idx(piomode)] & 0x03); 475 } 476 if (ch->unit) { 477 mask40 <<= 16; 478 new40 <<= 16; 479 mask44 <<= 4; 480 new44 <<= 4; 481 } 482 pci_write_config(parent, 0x40, (reg40 & ~mask40) | new40, 4); 483 pci_write_config(parent, 0x44, (reg44 & ~mask44) | new44, 1); 484 return (mode); 485 } 486 487 static int 488 ata_intel_sch_setmode(device_t dev, int target, int mode) 489 { 490 device_t parent = device_get_parent(dev); 491 struct ata_pci_controller *ctlr = device_get_softc(parent); 492 u_int8_t dtim = 0x80 + (target << 2); 493 u_int32_t tim = pci_read_config(parent, dtim, 4); 494 int piomode; 495 496 mode = min(mode, ctlr->chip->max_dma); 497 if (mode >= ATA_UDMA0) { 498 tim |= (0x1 << 31); 499 tim &= ~(0x7 << 16); 500 tim |= ((mode & ATA_MODE_MASK) << 16); 501 piomode = ATA_PIO4; 502 } else if (mode >= ATA_WDMA0) { 503 tim &= ~(0x1 << 31); 504 tim &= ~(0x3 << 8); 505 tim |= ((mode & ATA_MODE_MASK) << 8); 506 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 : 507 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4; 508 } else 509 piomode = mode; 510 tim &= ~(0x7); 511 tim |= (piomode & 0x7); 512 pci_write_config(parent, dtim, tim, 4); 513 return (mode); 514 } 515 516 static int 517 ata_intel_sata_getrev(device_t dev, int target) 518 { 519 struct ata_channel *ch = device_get_softc(dev); 520 uint32_t status; 521 522 if (ata_sata_scr_read(ch, target, ATA_SSTATUS, &status) == 0) 523 return ((status & 0x0f0) >> 4); 524 return (0xff); 525 } 526 527 static int 528 ata_intel_sata_status(device_t dev) 529 { 530 struct ata_channel *ch = device_get_softc(dev); 531 532 ata_sata_phy_check_events(dev, 0); 533 if ((ch->flags & ATA_NO_SLAVE) == 0) 534 ata_sata_phy_check_events(dev, 1); 535 536 return ata_pci_status(dev); 537 } 538 539 static int 540 ata_intel_sata_cscr_read(device_t dev, int port, int reg, u_int32_t *result) 541 { 542 struct ata_pci_controller *ctlr; 543 struct ata_channel *ch; 544 device_t parent; 545 u_char *smap; 546 547 parent = device_get_parent(dev); 548 ctlr = device_get_softc(parent); 549 ch = device_get_softc(dev); 550 smap = (u_char *)&ctlr->chipset_data + ch->unit * 2; 551 port = (port == 1) ? 1 : 0; 552 switch (reg) { 553 case ATA_SSTATUS: 554 reg = 0; 555 break; 556 case ATA_SERROR: 557 reg = 1; 558 break; 559 case ATA_SCONTROL: 560 reg = 2; 561 break; 562 default: 563 return (EINVAL); 564 } 565 pci_write_config(parent, 0xa0, 566 0x50 + smap[port] * 0x10 + reg * 4, 4); 567 *result = pci_read_config(parent, 0xa4, 4); 568 return (0); 569 } 570 571 static int 572 ata_intel_sata_sidpr_read(device_t dev, int port, int reg, u_int32_t *result) 573 { 574 struct ata_pci_controller *ctlr; 575 struct ata_channel *ch; 576 device_t parent; 577 578 parent = device_get_parent(dev); 579 ctlr = device_get_softc(parent); 580 ch = device_get_softc(dev); 581 port = (port == 1) ? 1 : 0; 582 switch (reg) { 583 case ATA_SSTATUS: 584 reg = 0; 585 break; 586 case ATA_SCONTROL: 587 reg = 1; 588 break; 589 case ATA_SERROR: 590 reg = 2; 591 break; 592 default: 593 return (EINVAL); 594 } 595 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, ((ch->unit * 2 + port) << 8) + reg); 596 *result = ATA_IDX_INL(ch, ATA_IDX_DATA); 597 return (0); 598 } 599 600 static int 601 ata_intel_sata_cscr_write(device_t dev, int port, int reg, u_int32_t value) 602 { 603 struct ata_pci_controller *ctlr; 604 struct ata_channel *ch; 605 device_t parent; 606 u_char *smap; 607 608 parent = device_get_parent(dev); 609 ctlr = device_get_softc(parent); 610 ch = device_get_softc(dev); 611 smap = (u_char *)&ctlr->chipset_data + ch->unit * 2; 612 port = (port == 1) ? 1 : 0; 613 switch (reg) { 614 case ATA_SSTATUS: 615 reg = 0; 616 break; 617 case ATA_SERROR: 618 reg = 1; 619 break; 620 case ATA_SCONTROL: 621 reg = 2; 622 break; 623 default: 624 return (EINVAL); 625 } 626 pci_write_config(parent, 0xa0, 627 0x50 + smap[port] * 0x10 + reg * 4, 4); 628 pci_write_config(parent, 0xa4, value, 4); 629 return (0); 630 } 631 632 static int 633 ata_intel_sata_sidpr_write(device_t dev, int port, int reg, u_int32_t value) 634 { 635 struct ata_pci_controller *ctlr; 636 struct ata_channel *ch; 637 device_t parent; 638 639 parent = device_get_parent(dev); 640 ctlr = device_get_softc(parent); 641 ch = device_get_softc(dev); 642 port = (port == 1) ? 1 : 0; 643 switch (reg) { 644 case ATA_SSTATUS: 645 reg = 0; 646 break; 647 case ATA_SCONTROL: 648 reg = 1; 649 break; 650 case ATA_SERROR: 651 reg = 2; 652 break; 653 default: 654 return (EINVAL); 655 } 656 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, ((ch->unit * 2 + port) << 8) + reg); 657 ATA_IDX_OUTL(ch, ATA_IDX_DATA, value); 658 return (0); 659 } 660 661 static int 662 ata_intel_31244_ch_attach(device_t dev) 663 { 664 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 665 struct ata_channel *ch = device_get_softc(dev); 666 int i; 667 int ch_offset; 668 669 ata_pci_dmainit(dev); 670 671 ch_offset = 0x200 + ch->unit * 0x200; 672 673 for (i = ATA_DATA; i < ATA_MAX_RES; i++) 674 ch->r_io[i].res = ctlr->r_res2; 675 676 /* setup ATA registers */ 677 ch->r_io[ATA_DATA].offset = ch_offset + 0x00; 678 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06; 679 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08; 680 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c; 681 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; 682 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14; 683 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18; 684 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d; 685 ch->r_io[ATA_ERROR].offset = ch_offset + 0x04; 686 ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c; 687 ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28; 688 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29; 689 690 /* setup DMA registers */ 691 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100; 692 ch->r_io[ATA_SERROR].offset = ch_offset + 0x104; 693 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108; 694 695 /* setup SATA registers */ 696 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70; 697 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72; 698 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74; 699 700 ch->flags |= ATA_NO_SLAVE; 701 ch->flags |= ATA_SATA; 702 ata_pci_hw(dev); 703 ch->hw.status = ata_intel_31244_status; 704 ch->hw.tf_write = ata_intel_31244_tf_write; 705 706 /* enable PHY state change interrupt */ 707 ATA_OUTL(ctlr->r_res2, 0x4, 708 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3))); 709 return 0; 710 } 711 712 static int 713 ata_intel_31244_ch_detach(device_t dev) 714 { 715 716 ata_pci_dmafini(dev); 717 return (0); 718 } 719 720 static int 721 ata_intel_31244_status(device_t dev) 722 { 723 /* do we have any PHY events ? */ 724 ata_sata_phy_check_events(dev, -1); 725 726 /* any drive action to take care of ? */ 727 return ata_pci_status(dev); 728 } 729 730 static void 731 ata_intel_31244_tf_write(struct ata_request *request) 732 { 733 struct ata_channel *ch = device_get_softc(request->parent); 734 #ifndef ATA_CAM 735 struct ata_device *atadev = device_get_softc(request->dev); 736 #endif 737 738 if (request->flags & ATA_R_48BIT) { 739 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature); 740 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count); 741 ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) | 742 (request->u.ata.lba & 0x00ff)); 743 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) | 744 ((request->u.ata.lba >> 8) & 0x00ff)); 745 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) | 746 ((request->u.ata.lba >> 16) & 0x00ff)); 747 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit)); 748 } 749 else { 750 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 751 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 752 #ifndef ATA_CAM 753 if (atadev->flags & ATA_D_USE_CHS) { 754 int heads, sectors; 755 756 if (atadev->param.atavalid & ATA_FLAG_54_58) { 757 heads = atadev->param.current_heads; 758 sectors = atadev->param.current_sectors; 759 } 760 else { 761 heads = atadev->param.heads; 762 sectors = atadev->param.sectors; 763 } 764 ATA_IDX_OUTB(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1); 765 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 766 (request->u.ata.lba / (sectors * heads))); 767 ATA_IDX_OUTB(ch, ATA_CYL_MSB, 768 (request->u.ata.lba / (sectors * heads)) >> 8); 769 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit) | 770 (((request->u.ata.lba% (sectors * heads)) / 771 sectors) & 0xf)); 772 } 773 else { 774 #endif 775 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 776 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 777 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 778 ATA_IDX_OUTB(ch, ATA_DRIVE, 779 ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) | 780 ((request->u.ata.lba >> 24) & 0x0f)); 781 #ifndef ATA_CAM 782 } 783 #endif 784 } 785 } 786 787 static void 788 ata_intel_31244_reset(device_t dev) 789 { 790 struct ata_channel *ch = device_get_softc(dev); 791 792 if (ata_sata_phy_reset(dev, -1, 1)) 793 ata_generic_reset(dev); 794 else 795 ch->devices = 0; 796 } 797 798 ATA_DECLARE_DRIVER(ata_intel); 799 MODULE_DEPEND(ata_intel, ata_ahci, 1, 1, 1); 800