1 /*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ata.h" 31 #include <sys/param.h> 32 #include <sys/module.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/ata.h> 36 #include <sys/bus.h> 37 #include <sys/endian.h> 38 #include <sys/malloc.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/sema.h> 42 #include <sys/taskqueue.h> 43 #include <vm/uma.h> 44 #include <machine/stdarg.h> 45 #include <machine/resource.h> 46 #include <machine/bus.h> 47 #include <sys/rman.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/ata/ata-all.h> 51 #include <dev/ata/ata-pci.h> 52 #include <ata_if.h> 53 54 /* local prototypes */ 55 static int ata_intel_chipinit(device_t dev); 56 static int ata_intel_ch_attach(device_t dev); 57 static void ata_intel_reset(device_t dev); 58 static int ata_intel_old_setmode(device_t dev, int target, int mode); 59 static int ata_intel_new_setmode(device_t dev, int target, int mode); 60 static int ata_intel_sch_setmode(device_t dev, int target, int mode); 61 static int ata_intel_sata_getrev(device_t dev, int target); 62 static int ata_intel_31244_ch_attach(device_t dev); 63 static int ata_intel_31244_ch_detach(device_t dev); 64 static int ata_intel_31244_status(device_t dev); 65 static void ata_intel_31244_tf_write(struct ata_request *request); 66 static void ata_intel_31244_reset(device_t dev); 67 68 /* misc defines */ 69 #define INTEL_AHCI 1 70 71 72 /* 73 * Intel chipset support functions 74 */ 75 static int 76 ata_intel_probe(device_t dev) 77 { 78 struct ata_pci_controller *ctlr = device_get_softc(dev); 79 static struct ata_chip_id ids[] = 80 {{ ATA_I82371FB, 0, 0, 2, ATA_WDMA2, "PIIX" }, 81 { ATA_I82371SB, 0, 0, 2, ATA_WDMA2, "PIIX3" }, 82 { ATA_I82371AB, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 83 { ATA_I82443MX, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 84 { ATA_I82451NX, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 85 { ATA_I82801AB, 0, 0, 2, ATA_UDMA2, "ICH0" }, 86 { ATA_I82801AA, 0, 0, 2, ATA_UDMA4, "ICH" }, 87 { ATA_I82372FB, 0, 0, 2, ATA_UDMA4, "ICH" }, 88 { ATA_I82801BA, 0, 0, 2, ATA_UDMA5, "ICH2" }, 89 { ATA_I82801BA_1, 0, 0, 2, ATA_UDMA5, "ICH2" }, 90 { ATA_I82801CA, 0, 0, 2, ATA_UDMA5, "ICH3" }, 91 { ATA_I82801CA_1, 0, 0, 2, ATA_UDMA5, "ICH3" }, 92 { ATA_I82801DB, 0, 0, 2, ATA_UDMA5, "ICH4" }, 93 { ATA_I82801DB_1, 0, 0, 2, ATA_UDMA5, "ICH4" }, 94 { ATA_I82801EB, 0, 0, 2, ATA_UDMA5, "ICH5" }, 95 { ATA_I82801EB_S1, 0, 0, 2, ATA_SA150, "ICH5" }, 96 { ATA_I82801EB_R1, 0, 0, 2, ATA_SA150, "ICH5" }, 97 { ATA_I6300ESB, 0, 0, 2, ATA_UDMA5, "6300ESB" }, 98 { ATA_I6300ESB_S1, 0, 0, 2, ATA_SA150, "6300ESB" }, 99 { ATA_I6300ESB_R1, 0, 0, 2, ATA_SA150, "6300ESB" }, 100 { ATA_I82801FB, 0, 0, 2, ATA_UDMA5, "ICH6" }, 101 { ATA_I82801FB_S1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6" }, 102 { ATA_I82801FB_R1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6" }, 103 { ATA_I82801FBM, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6M" }, 104 { ATA_I82801GB, 0, 0, 1, ATA_UDMA5, "ICH7" }, 105 { ATA_I82801GB_S1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" }, 106 { ATA_I82801GB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" }, 107 { ATA_I82801GB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" }, 108 { ATA_I82801GBM_S1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" }, 109 { ATA_I82801GBM_R1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" }, 110 { ATA_I82801GBM_AH, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" }, 111 { ATA_I63XXESB2, 0, 0, 1, ATA_UDMA5, "63XXESB2" }, 112 { ATA_I63XXESB2_S1, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 113 { ATA_I63XXESB2_S2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 114 { ATA_I63XXESB2_R1, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 115 { ATA_I63XXESB2_R2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 116 { ATA_I82801HB_S1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 117 { ATA_I82801HB_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 118 { ATA_I82801HB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 119 { ATA_I82801HB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 120 { ATA_I82801HB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 121 { ATA_I82801HBM, 0, 0, 1, ATA_UDMA5, "ICH8M" }, 122 { ATA_I82801HBM_S1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" }, 123 { ATA_I82801HBM_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" }, 124 { ATA_I82801HBM_S3, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" }, 125 { ATA_I82801IB_S1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 126 { ATA_I82801IB_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 127 { ATA_I82801IB_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 128 { ATA_I82801IB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 129 { ATA_I82801IB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 130 { ATA_I82801IB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 131 { ATA_I82801JIB_S1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 132 { ATA_I82801JIB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 133 { ATA_I82801JIB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 134 { ATA_I82801JIB_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 135 { ATA_I82801JD_S1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 136 { ATA_I82801JD_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 137 { ATA_I82801JD_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 138 { ATA_I82801JD_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 139 { ATA_I82801JI_S1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 140 { ATA_I82801JI_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 141 { ATA_I82801JI_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 142 { ATA_I82801JI_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 143 { ATA_I31244, 0, 0, 2, ATA_SA150, "31244" }, 144 { ATA_ISCH, 0, 0, 1, ATA_UDMA5, "SCH" }, 145 { 0, 0, 0, 0, 0, 0}}; 146 147 if (pci_get_vendor(dev) != ATA_INTEL_ID) 148 return ENXIO; 149 150 if (!(ctlr->chip = ata_match_chip(dev, ids))) 151 return ENXIO; 152 153 ata_set_desc(dev); 154 ctlr->chipinit = ata_intel_chipinit; 155 return (BUS_PROBE_DEFAULT); 156 } 157 158 static int 159 ata_intel_chipinit(device_t dev) 160 { 161 struct ata_pci_controller *ctlr = device_get_softc(dev); 162 163 if (ata_setup_interrupt(dev, ata_generic_intr)) 164 return ENXIO; 165 166 /* good old PIIX needs special treatment (not implemented) */ 167 if (ctlr->chip->chipid == ATA_I82371FB) { 168 ctlr->setmode = ata_intel_old_setmode; 169 } 170 171 /* the intel 31244 needs special care if in DPA mode */ 172 else if (ctlr->chip->chipid == ATA_I31244) { 173 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) { 174 ctlr->r_type2 = SYS_RES_MEMORY; 175 ctlr->r_rid2 = PCIR_BAR(0); 176 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 177 &ctlr->r_rid2, 178 RF_ACTIVE))) 179 return ENXIO; 180 ctlr->channels = 4; 181 ctlr->ch_attach = ata_intel_31244_ch_attach; 182 ctlr->ch_detach = ata_intel_31244_ch_detach; 183 ctlr->reset = ata_intel_31244_reset; 184 } 185 ctlr->setmode = ata_sata_setmode; 186 ctlr->getrev = ata_sata_getrev; 187 } 188 /* SCH */ 189 else if (ctlr->chip->chipid == ATA_ISCH) { 190 ctlr->channels = 1; 191 ctlr->ch_attach = ata_intel_ch_attach; 192 ctlr->ch_detach = ata_pci_ch_detach; 193 ctlr->setmode = ata_intel_sch_setmode; 194 } 195 /* non SATA intel chips goes here */ 196 else if (ctlr->chip->max_dma < ATA_SA150) { 197 ctlr->channels = ctlr->chip->cfg2; 198 ctlr->ch_attach = ata_intel_ch_attach; 199 ctlr->ch_detach = ata_pci_ch_detach; 200 ctlr->setmode = ata_intel_new_setmode; 201 } 202 203 /* SATA parts can be either compat or AHCI */ 204 else { 205 /* force all ports active "the legacy way" */ 206 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f, 2); 207 208 ctlr->ch_attach = ata_intel_ch_attach; 209 ctlr->ch_detach = ata_pci_ch_detach; 210 ctlr->reset = ata_intel_reset; 211 212 /* 213 * if we have AHCI capability and AHCI or RAID mode enabled 214 * in BIOS we try for AHCI mode 215 */ 216 if ((ctlr->chip->cfg1 == INTEL_AHCI) && 217 (pci_read_config(dev, 0x90, 1) & 0xc0) && 218 (ata_ahci_chipinit(dev) != ENXIO)) 219 return 0; 220 221 /* if BAR(5) is IO it should point to SATA interface registers */ 222 ctlr->r_type2 = SYS_RES_IOPORT; 223 ctlr->r_rid2 = PCIR_BAR(5); 224 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 225 &ctlr->r_rid2, RF_ACTIVE))) 226 ctlr->getrev = ata_intel_sata_getrev; 227 ctlr->setmode = ata_sata_setmode; 228 } 229 return 0; 230 } 231 232 static int 233 ata_intel_ch_attach(device_t dev) 234 { 235 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 236 struct ata_channel *ch = device_get_softc(dev); 237 238 /* setup the usual register normal pci style */ 239 if (ata_pci_ch_attach(dev)) 240 return ENXIO; 241 242 /* if r_res2 is valid it points to SATA interface registers */ 243 if (ctlr->r_res2) { 244 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 245 ch->r_io[ATA_IDX_ADDR].offset = 0x00; 246 ch->r_io[ATA_IDX_DATA].res = ctlr->r_res2; 247 ch->r_io[ATA_IDX_DATA].offset = 0x04; 248 } 249 250 ch->flags |= ATA_ALWAYS_DMASTAT; 251 if (ctlr->chip->max_dma >= ATA_SA150) { 252 if (ctlr->chip->cfg1 == 0 && 253 (pci_read_config(device_get_parent(dev), 0x90, 1) & 0x04) == 0) 254 ch->flags |= ATA_NO_SLAVE; 255 ch->flags |= ATA_SATA; 256 } else if (ctlr->chip->chipid != ATA_ISCH) 257 ch->flags |= ATA_CHECKS_CABLE; 258 return 0; 259 } 260 261 static void 262 ata_intel_reset(device_t dev) 263 { 264 device_t parent = device_get_parent(dev); 265 struct ata_pci_controller *ctlr = device_get_softc(parent); 266 struct ata_channel *ch = device_get_softc(dev); 267 int mask, timeout; 268 269 /* ICH6 & ICH7 in compat mode has 4 SATA ports as master/slave on 2 ch's */ 270 if (ctlr->chip->cfg1) { 271 mask = (0x0005 << ch->unit); 272 } 273 else { 274 /* ICH5 in compat mode has SATA ports as master/slave on 1 channel */ 275 if (pci_read_config(parent, 0x90, 1) & 0x04) 276 mask = 0x0003; 277 else 278 mask = (0x0001 << ch->unit); 279 } 280 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) & ~mask, 2); 281 DELAY(10); 282 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) | mask, 2); 283 284 /* wait up to 1 sec for "connect well" */ 285 for (timeout = 0; timeout < 100 ; timeout++) { 286 if (((pci_read_config(parent, 0x92, 2) & (mask << 4)) == (mask << 4)) && 287 (ATA_IDX_INB(ch, ATA_STATUS) != 0xff)) 288 break; 289 ata_udelay(10000); 290 } 291 ata_generic_reset(dev); 292 } 293 294 static int 295 ata_intel_old_setmode(device_t dev, int target, int mode) 296 { 297 device_t parent = device_get_parent(dev); 298 struct ata_pci_controller *ctlr = device_get_softc(parent); 299 300 mode = min(mode, ctlr->chip->max_dma); 301 return (mode); 302 } 303 304 static int 305 ata_intel_new_setmode(device_t dev, int target, int mode) 306 { 307 device_t parent = device_get_parent(dev); 308 struct ata_pci_controller *ctlr = device_get_softc(parent); 309 struct ata_channel *ch = device_get_softc(dev); 310 int devno = (ch->unit << 1) + target; 311 int piomode; 312 u_int32_t reg40 = pci_read_config(parent, 0x40, 4); 313 u_int8_t reg44 = pci_read_config(parent, 0x44, 1); 314 u_int8_t reg48 = pci_read_config(parent, 0x48, 1); 315 u_int16_t reg4a = pci_read_config(parent, 0x4a, 2); 316 u_int16_t reg54 = pci_read_config(parent, 0x54, 2); 317 u_int32_t mask40 = 0, new40 = 0; 318 u_int8_t mask44 = 0, new44 = 0; 319 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x00, 0x21, 0x23 }; 320 u_int8_t utimings[] = { 0x00, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02 }; 321 322 mode = min(mode, ctlr->chip->max_dma); 323 if (mode > ATA_UDMA2 && !(reg54 & (0x10 << devno))) { 324 ata_print_cable(dev, "controller"); 325 mode = ATA_UDMA2; 326 } 327 /* Enable/disable UDMA and set timings. */ 328 if (mode >= ATA_UDMA0) { 329 pci_write_config(parent, 0x48, reg48 | (0x0001 << devno), 2); 330 pci_write_config(parent, 0x4a, 331 (reg4a & ~(0x3 << (devno << 2))) | 332 (utimings[mode & ATA_MODE_MASK] << (devno<<2)), 2); 333 piomode = ATA_PIO4; 334 } else { 335 pci_write_config(parent, 0x48, reg48 & ~(0x0001 << devno), 2); 336 pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (devno << 2))),2); 337 piomode = mode; 338 } 339 reg54 |= 0x0400; 340 /* Set UDMA reference clock (33/66/133MHz). */ 341 reg54 &= ~(0x1001 << devno); 342 if (mode >= ATA_UDMA5) 343 reg54 |= (0x1000 << devno); 344 else if (mode >= ATA_UDMA3) 345 reg54 |= (0x1 << devno); 346 pci_write_config(parent, 0x54, reg54, 2); 347 /* Allow PIO/WDMA timing controls. */ 348 reg40 &= ~0x00ff00ff; 349 reg40 |= 0x40774077; 350 /* Set PIO/WDMA timings. */ 351 if (target == 0) { 352 mask40 = 0x3300; 353 new40 = timings[ata_mode2idx(piomode)] << 8; 354 } else { 355 mask44 = 0x0f; 356 new44 = ((timings[ata_mode2idx(piomode)] & 0x30) >> 2) | 357 (timings[ata_mode2idx(piomode)] & 0x03); 358 } 359 if (ch->unit) { 360 mask40 <<= 16; 361 new40 <<= 16; 362 mask44 <<= 4; 363 new44 <<= 4; 364 } 365 pci_write_config(parent, 0x40, (reg40 & ~mask40) | new40, 4); 366 pci_write_config(parent, 0x44, (reg44 & ~mask44) | new44, 1); 367 return (mode); 368 } 369 370 static int 371 ata_intel_sch_setmode(device_t dev, int target, int mode) 372 { 373 device_t parent = device_get_parent(dev); 374 struct ata_pci_controller *ctlr = device_get_softc(parent); 375 u_int8_t dtim = 0x80 + (target << 2); 376 u_int32_t tim = pci_read_config(parent, dtim, 4); 377 int piomode; 378 379 mode = min(mode, ctlr->chip->max_dma); 380 if (mode >= ATA_UDMA0) { 381 tim |= (0x1 << 31); 382 tim &= ~(0x7 << 16); 383 tim |= ((mode & ATA_MODE_MASK) << 16); 384 piomode = ATA_PIO4; 385 } else if (mode >= ATA_WDMA0) { 386 tim &= ~(0x1 << 31); 387 tim &= ~(0x3 << 8); 388 tim |= ((mode & ATA_MODE_MASK) << 8); 389 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 : 390 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4; 391 } else 392 piomode = mode; 393 tim &= ~(0x7); 394 tim |= (piomode & 0x7); 395 pci_write_config(parent, dtim, tim, 4); 396 return (mode); 397 } 398 399 static int 400 ata_intel_sata_getrev(device_t dev, int target) 401 { 402 struct ata_channel *ch = device_get_softc(dev); 403 int devno = (ch->unit << 1) + target; 404 405 /* set ATA_SSTATUS register offset */ 406 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, devno * 0x100); 407 /* query SATA STATUS for the speed */ 408 return ((ATA_IDX_INL(ch, ATA_IDX_DATA) & 0x0f0) >> 4); 409 } 410 411 static int 412 ata_intel_31244_ch_attach(device_t dev) 413 { 414 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 415 struct ata_channel *ch = device_get_softc(dev); 416 int i; 417 int ch_offset; 418 419 ata_pci_dmainit(dev); 420 421 ch_offset = 0x200 + ch->unit * 0x200; 422 423 for (i = ATA_DATA; i < ATA_MAX_RES; i++) 424 ch->r_io[i].res = ctlr->r_res2; 425 426 /* setup ATA registers */ 427 ch->r_io[ATA_DATA].offset = ch_offset + 0x00; 428 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06; 429 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08; 430 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c; 431 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; 432 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14; 433 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18; 434 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d; 435 ch->r_io[ATA_ERROR].offset = ch_offset + 0x04; 436 ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c; 437 ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28; 438 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29; 439 440 /* setup DMA registers */ 441 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100; 442 ch->r_io[ATA_SERROR].offset = ch_offset + 0x104; 443 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108; 444 445 /* setup SATA registers */ 446 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70; 447 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72; 448 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74; 449 450 ch->flags |= ATA_NO_SLAVE; 451 ch->flags |= ATA_SATA; 452 ata_pci_hw(dev); 453 ch->hw.status = ata_intel_31244_status; 454 ch->hw.tf_write = ata_intel_31244_tf_write; 455 456 /* enable PHY state change interrupt */ 457 ATA_OUTL(ctlr->r_res2, 0x4, 458 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3))); 459 return 0; 460 } 461 462 static int 463 ata_intel_31244_ch_detach(device_t dev) 464 { 465 466 ata_pci_dmafini(dev); 467 return (0); 468 } 469 470 static int 471 ata_intel_31244_status(device_t dev) 472 { 473 /* do we have any PHY events ? */ 474 ata_sata_phy_check_events(dev); 475 476 /* any drive action to take care of ? */ 477 return ata_pci_status(dev); 478 } 479 480 static void 481 ata_intel_31244_tf_write(struct ata_request *request) 482 { 483 struct ata_channel *ch = device_get_softc(request->parent); 484 #ifndef ATA_CAM 485 struct ata_device *atadev = device_get_softc(request->dev); 486 #endif 487 488 if (request->flags & ATA_R_48BIT) { 489 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature); 490 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count); 491 ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) | 492 (request->u.ata.lba & 0x00ff)); 493 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) | 494 ((request->u.ata.lba >> 8) & 0x00ff)); 495 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) | 496 ((request->u.ata.lba >> 16) & 0x00ff)); 497 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit)); 498 } 499 else { 500 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 501 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 502 #ifndef ATA_CAM 503 if (atadev->flags & ATA_D_USE_CHS) { 504 int heads, sectors; 505 506 if (atadev->param.atavalid & ATA_FLAG_54_58) { 507 heads = atadev->param.current_heads; 508 sectors = atadev->param.current_sectors; 509 } 510 else { 511 heads = atadev->param.heads; 512 sectors = atadev->param.sectors; 513 } 514 ATA_IDX_OUTB(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1); 515 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 516 (request->u.ata.lba / (sectors * heads))); 517 ATA_IDX_OUTB(ch, ATA_CYL_MSB, 518 (request->u.ata.lba / (sectors * heads)) >> 8); 519 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit) | 520 (((request->u.ata.lba% (sectors * heads)) / 521 sectors) & 0xf)); 522 } 523 else { 524 #endif 525 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 526 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 527 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 528 ATA_IDX_OUTB(ch, ATA_DRIVE, 529 ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) | 530 ((request->u.ata.lba >> 24) & 0x0f)); 531 #ifndef ATA_CAM 532 } 533 #endif 534 } 535 } 536 537 static void 538 ata_intel_31244_reset(device_t dev) 539 { 540 if (ata_sata_phy_reset(dev, -1, 1)) 541 ata_generic_reset(dev); 542 } 543 544 ATA_DECLARE_DRIVER(ata_intel); 545 MODULE_DEPEND(ata_intel, ata_ahci, 1, 1, 1); 546