1 /*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ata.h" 31 #include <sys/param.h> 32 #include <sys/module.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/ata.h> 36 #include <sys/bus.h> 37 #include <sys/endian.h> 38 #include <sys/malloc.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/sema.h> 42 #include <sys/taskqueue.h> 43 #include <vm/uma.h> 44 #include <machine/stdarg.h> 45 #include <machine/resource.h> 46 #include <machine/bus.h> 47 #include <sys/rman.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/ata/ata-all.h> 51 #include <dev/ata/ata-pci.h> 52 #include <ata_if.h> 53 54 /* local prototypes */ 55 static int ata_intel_chipinit(device_t dev); 56 static int ata_intel_ch_attach(device_t dev); 57 static void ata_intel_reset(device_t dev); 58 static int ata_intel_old_setmode(device_t dev, int target, int mode); 59 static int ata_intel_new_setmode(device_t dev, int target, int mode); 60 static int ata_intel_sch_setmode(device_t dev, int target, int mode); 61 static int ata_intel_sata_getrev(device_t dev, int target); 62 static int ata_intel_sata_status(device_t dev); 63 static int ata_intel_sata_ahci_read(device_t dev, int port, 64 int reg, u_int32_t *result); 65 static int ata_intel_sata_cscr_read(device_t dev, int port, 66 int reg, u_int32_t *result); 67 static int ata_intel_sata_sidpr_read(device_t dev, int port, 68 int reg, u_int32_t *result); 69 static int ata_intel_sata_ahci_write(device_t dev, int port, 70 int reg, u_int32_t result); 71 static int ata_intel_sata_cscr_write(device_t dev, int port, 72 int reg, u_int32_t result); 73 static int ata_intel_sata_sidpr_write(device_t dev, int port, 74 int reg, u_int32_t result); 75 static int ata_intel_31244_ch_attach(device_t dev); 76 static int ata_intel_31244_ch_detach(device_t dev); 77 static int ata_intel_31244_status(device_t dev); 78 static void ata_intel_31244_tf_write(struct ata_request *request); 79 static void ata_intel_31244_reset(device_t dev); 80 81 /* misc defines */ 82 #define INTEL_AHCI 1 83 #define INTEL_ICH5 2 84 #define INTEL_6CH 4 85 #define INTEL_6CH2 8 86 #define INTEL_ICH7 16 87 88 /* 89 * Intel chipset support functions 90 */ 91 static int 92 ata_intel_probe(device_t dev) 93 { 94 struct ata_pci_controller *ctlr = device_get_softc(dev); 95 static struct ata_chip_id ids[] = 96 {{ ATA_I82371FB, 0, 0, 2, ATA_WDMA2, "PIIX" }, 97 { ATA_I82371SB, 0, 0, 2, ATA_WDMA2, "PIIX3" }, 98 { ATA_I82371AB, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 99 { ATA_I82443MX, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 100 { ATA_I82451NX, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 101 { ATA_I82801AB, 0, 0, 2, ATA_UDMA2, "ICH0" }, 102 { ATA_I82801AA, 0, 0, 2, ATA_UDMA4, "ICH" }, 103 { ATA_I82372FB, 0, 0, 2, ATA_UDMA4, "ICH" }, 104 { ATA_I82801BA, 0, 0, 2, ATA_UDMA5, "ICH2" }, 105 { ATA_I82801BA_1, 0, 0, 2, ATA_UDMA5, "ICH2" }, 106 { ATA_I82801CA, 0, 0, 2, ATA_UDMA5, "ICH3" }, 107 { ATA_I82801CA_1, 0, 0, 2, ATA_UDMA5, "ICH3" }, 108 { ATA_I82801DB, 0, 0, 2, ATA_UDMA5, "ICH4" }, 109 { ATA_I82801DB_1, 0, 0, 2, ATA_UDMA5, "ICH4" }, 110 { ATA_I82801EB, 0, 0, 2, ATA_UDMA5, "ICH5" }, 111 { ATA_I82801EB_S1, 0, INTEL_ICH5, 2, ATA_SA150, "ICH5" }, 112 { ATA_I82801EB_R1, 0, INTEL_ICH5, 2, ATA_SA150, "ICH5" }, 113 { ATA_I6300ESB, 0, 0, 2, ATA_UDMA5, "6300ESB" }, 114 { ATA_I6300ESB_S1, 0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" }, 115 { ATA_I6300ESB_R1, 0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" }, 116 { ATA_I82801FB, 0, 0, 2, ATA_UDMA5, "ICH6" }, 117 { ATA_I82801FB_S1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6" }, 118 { ATA_I82801FB_R1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6" }, 119 { ATA_I82801FBM, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6M" }, 120 { ATA_I82801GB, 0, 0, 1, ATA_UDMA5, "ICH7" }, 121 { ATA_I82801GB_S1, 0, INTEL_ICH7, 0, ATA_SA300, "ICH7" }, 122 { ATA_I82801GB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" }, 123 { ATA_I82801GB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" }, 124 { ATA_I82801GBM_S1, 0, INTEL_ICH7, 0, ATA_SA150, "ICH7M" }, 125 { ATA_I82801GBM_R1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" }, 126 { ATA_I82801GBM_AH, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" }, 127 { ATA_I63XXESB2, 0, 0, 1, ATA_UDMA5, "63XXESB2" }, 128 { ATA_I63XXESB2_S1, 0, 0, 0, ATA_SA300, "63XXESB2" }, 129 { ATA_I63XXESB2_S2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 130 { ATA_I63XXESB2_R1, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 131 { ATA_I63XXESB2_R2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 132 { ATA_I82801HB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH8" }, 133 { ATA_I82801HB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH8" }, 134 { ATA_I82801HB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 135 { ATA_I82801HB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 136 { ATA_I82801HB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 137 { ATA_I82801HBM, 0, 0, 1, ATA_UDMA5, "ICH8M" }, 138 { ATA_I82801HBM_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH8M" }, 139 { ATA_I82801HBM_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" }, 140 { ATA_I82801HBM_S3, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" }, 141 { ATA_I82801IB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH9" }, 142 { ATA_I82801IB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9" }, 143 { ATA_I82801IB_S3, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9" }, 144 { ATA_I82801IB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 145 { ATA_I82801IB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 146 { ATA_I82801IB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 147 { ATA_I82801JIB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, 148 { ATA_I82801JIB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 149 { ATA_I82801JIB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 150 { ATA_I82801JIB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, 151 { ATA_I82801JD_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, 152 { ATA_I82801JD_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 153 { ATA_I82801JD_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 154 { ATA_I82801JD_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, 155 { ATA_I82801JI_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, 156 { ATA_I82801JI_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 157 { ATA_I82801JI_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 158 { ATA_I82801JI_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, 159 { ATA_5Series_S1, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 160 { ATA_5Series_S2, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 161 { ATA_5Series_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 162 { ATA_5Series_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 163 { ATA_5Series_R1, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 164 { ATA_5Series_S3, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 165 { ATA_5Series_S4, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 166 { ATA_5Series_AH3, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 167 { ATA_5Series_R2, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 168 { ATA_5Series_S5, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 169 { ATA_5Series_S6, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 170 { ATA_5Series_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 171 { ATA_CPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Cougar Point" }, 172 { ATA_CPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Cougar Point" }, 173 { ATA_CPT_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, 174 { ATA_CPT_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, 175 { ATA_CPT_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, 176 { ATA_CPT_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, 177 { ATA_CPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" }, 178 { ATA_CPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" }, 179 { ATA_PBG_S1, 0, INTEL_6CH, 0, ATA_SA300, "Patsburg" }, 180 { ATA_PBG_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" }, 181 { ATA_PBG_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" }, 182 { ATA_PBG_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" }, 183 { ATA_PBG_S2, 0, INTEL_6CH2, 0, ATA_SA300, "Patsburg" }, 184 { ATA_PPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Panther Point" }, 185 { ATA_PPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Panther Point" }, 186 { ATA_PPT_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 187 { ATA_PPT_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 188 { ATA_PPT_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 189 { ATA_PPT_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 190 { ATA_PPT_R3, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 191 { ATA_PPT_R4, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 192 { ATA_PPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Panther Point" }, 193 { ATA_PPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Panther Point" }, 194 { ATA_PPT_R5, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 195 { ATA_PPT_R6, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 196 { ATA_I31244, 0, 0, 2, ATA_SA150, "31244" }, 197 { ATA_ISCH, 0, 0, 1, ATA_UDMA5, "SCH" }, 198 { ATA_DH89XXCC, 0, INTEL_AHCI, 0, ATA_SA300, "DH89xxCC" }, 199 { 0, 0, 0, 0, 0, 0}}; 200 201 if (pci_get_vendor(dev) != ATA_INTEL_ID) 202 return ENXIO; 203 204 if (!(ctlr->chip = ata_match_chip(dev, ids))) 205 return ENXIO; 206 207 ata_set_desc(dev); 208 ctlr->chipinit = ata_intel_chipinit; 209 return (BUS_PROBE_DEFAULT); 210 } 211 212 static int 213 ata_intel_chipinit(device_t dev) 214 { 215 struct ata_pci_controller *ctlr = device_get_softc(dev); 216 217 if (ata_setup_interrupt(dev, ata_generic_intr)) 218 return ENXIO; 219 220 ctlr->chipset_data = NULL; 221 222 /* good old PIIX needs special treatment (not implemented) */ 223 if (ctlr->chip->chipid == ATA_I82371FB) { 224 ctlr->setmode = ata_intel_old_setmode; 225 } 226 227 /* the intel 31244 needs special care if in DPA mode */ 228 else if (ctlr->chip->chipid == ATA_I31244) { 229 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) { 230 ctlr->r_type2 = SYS_RES_MEMORY; 231 ctlr->r_rid2 = PCIR_BAR(0); 232 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 233 &ctlr->r_rid2, 234 RF_ACTIVE))) 235 return ENXIO; 236 ctlr->channels = 4; 237 ctlr->ch_attach = ata_intel_31244_ch_attach; 238 ctlr->ch_detach = ata_intel_31244_ch_detach; 239 ctlr->reset = ata_intel_31244_reset; 240 } 241 ctlr->setmode = ata_sata_setmode; 242 ctlr->getrev = ata_sata_getrev; 243 } 244 /* SCH */ 245 else if (ctlr->chip->chipid == ATA_ISCH) { 246 ctlr->channels = 1; 247 ctlr->ch_attach = ata_intel_ch_attach; 248 ctlr->ch_detach = ata_pci_ch_detach; 249 ctlr->setmode = ata_intel_sch_setmode; 250 } 251 /* non SATA intel chips goes here */ 252 else if (ctlr->chip->max_dma < ATA_SA150) { 253 ctlr->channels = ctlr->chip->cfg2; 254 ctlr->ch_attach = ata_intel_ch_attach; 255 ctlr->ch_detach = ata_pci_ch_detach; 256 ctlr->setmode = ata_intel_new_setmode; 257 } 258 259 /* SATA parts can be either compat or AHCI */ 260 else { 261 /* force all ports active "the legacy way" */ 262 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f, 2); 263 264 ctlr->ch_attach = ata_intel_ch_attach; 265 ctlr->ch_detach = ata_pci_ch_detach; 266 ctlr->reset = ata_intel_reset; 267 268 /* 269 * if we have AHCI capability and AHCI or RAID mode enabled 270 * in BIOS we try for AHCI mode 271 */ 272 if ((ctlr->chip->cfg1 & INTEL_AHCI) && 273 (pci_read_config(dev, 0x90, 1) & 0xc0) && 274 (ata_ahci_chipinit(dev) != ENXIO)) 275 return 0; 276 277 /* BAR(5) may point to SATA interface registers */ 278 if ((ctlr->chip->cfg1 & INTEL_ICH7)) { 279 ctlr->r_type2 = SYS_RES_MEMORY; 280 ctlr->r_rid2 = PCIR_BAR(5); 281 ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 282 &ctlr->r_rid2, RF_ACTIVE); 283 if (ctlr->r_res2 != NULL) { 284 /* Set SCRAE bit to enable registers access. */ 285 pci_write_config(dev, 0x94, 286 pci_read_config(dev, 0x94, 4) | (1 << 9), 4); 287 /* Set Ports Implemented register bits. */ 288 ATA_OUTL(ctlr->r_res2, 0x0C, 289 ATA_INL(ctlr->r_res2, 0x0C) | 0xf); 290 } 291 } else { 292 ctlr->r_type2 = SYS_RES_IOPORT; 293 ctlr->r_rid2 = PCIR_BAR(5); 294 ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 295 &ctlr->r_rid2, RF_ACTIVE); 296 } 297 if (ctlr->r_res2 != NULL || 298 (ctlr->chip->cfg1 & INTEL_ICH5)) 299 ctlr->getrev = ata_intel_sata_getrev; 300 ctlr->setmode = ata_sata_setmode; 301 } 302 return 0; 303 } 304 305 static int 306 ata_intel_ch_attach(device_t dev) 307 { 308 struct ata_pci_controller *ctlr; 309 struct ata_channel *ch; 310 u_char *smap; 311 u_int map; 312 313 /* setup the usual register normal pci style */ 314 if (ata_pci_ch_attach(dev)) 315 return (ENXIO); 316 317 ctlr = device_get_softc(device_get_parent(dev)); 318 ch = device_get_softc(dev); 319 320 /* if r_res2 is valid it points to SATA interface registers */ 321 if (ctlr->r_res2) { 322 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 323 ch->r_io[ATA_IDX_ADDR].offset = 0x00; 324 ch->r_io[ATA_IDX_DATA].res = ctlr->r_res2; 325 ch->r_io[ATA_IDX_DATA].offset = 0x04; 326 } 327 328 ch->flags |= ATA_ALWAYS_DMASTAT; 329 if (ctlr->chip->max_dma >= ATA_SA150) { 330 smap = (u_char *)&ctlr->chipset_data + ch->unit * 2; 331 map = pci_read_config(device_get_parent(dev), 0x90, 1); 332 if (ctlr->chip->cfg1 & INTEL_ICH5) { 333 map &= 0x07; 334 if ((map & 0x04) == 0) { 335 ch->flags |= ATA_SATA; 336 ch->flags |= ATA_NO_SLAVE; 337 smap[0] = (map & 0x01) ^ ch->unit; 338 smap[1] = 0; 339 } else if ((map & 0x02) == 0 && ch->unit == 0) { 340 ch->flags |= ATA_SATA; 341 smap[0] = (map & 0x01) ? 1 : 0; 342 smap[1] = (map & 0x01) ? 0 : 1; 343 } else if ((map & 0x02) != 0 && ch->unit == 1) { 344 ch->flags |= ATA_SATA; 345 smap[0] = (map & 0x01) ? 1 : 0; 346 smap[1] = (map & 0x01) ? 0 : 1; 347 } 348 } else if (ctlr->chip->cfg1 & INTEL_6CH2) { 349 ch->flags |= ATA_SATA; 350 ch->flags |= ATA_NO_SLAVE; 351 smap[0] = (ch->unit == 0) ? 0 : 1; 352 smap[1] = 0; 353 } else { 354 map &= 0x03; 355 if (map == 0x00) { 356 ch->flags |= ATA_SATA; 357 smap[0] = (ch->unit == 0) ? 0 : 1; 358 smap[1] = (ch->unit == 0) ? 2 : 3; 359 } else if (map == 0x02 && ch->unit == 0) { 360 ch->flags |= ATA_SATA; 361 smap[0] = 0; 362 smap[1] = 2; 363 } else if (map == 0x01 && ch->unit == 1) { 364 ch->flags |= ATA_SATA; 365 smap[0] = 1; 366 smap[1] = 3; 367 } 368 } 369 if (ch->flags & ATA_SATA) { 370 if ((ctlr->chip->cfg1 & INTEL_ICH5)) { 371 ch->flags |= ATA_PERIODIC_POLL; 372 ch->hw.status = ata_intel_sata_status; 373 ch->hw.pm_read = ata_intel_sata_cscr_read; 374 ch->hw.pm_write = ata_intel_sata_cscr_write; 375 } else if (ctlr->r_res2) { 376 ch->flags |= ATA_PERIODIC_POLL; 377 ch->hw.status = ata_intel_sata_status; 378 if ((ctlr->chip->cfg1 & INTEL_ICH7)) { 379 ch->hw.pm_read = ata_intel_sata_ahci_read; 380 ch->hw.pm_write = ata_intel_sata_ahci_write; 381 } else { 382 ch->hw.pm_read = ata_intel_sata_sidpr_read; 383 ch->hw.pm_write = ata_intel_sata_sidpr_write; 384 }; 385 } 386 if (ch->hw.pm_write != NULL) { 387 ata_sata_scr_write(ch, 0, 388 ATA_SERROR, 0xffffffff); 389 if ((ch->flags & ATA_NO_SLAVE) == 0) { 390 ata_sata_scr_write(ch, 1, 391 ATA_SERROR, 0xffffffff); 392 } 393 } 394 } else 395 ctlr->setmode = ata_intel_new_setmode; 396 } else if (ctlr->chip->chipid != ATA_ISCH) 397 ch->flags |= ATA_CHECKS_CABLE; 398 return (0); 399 } 400 401 static void 402 ata_intel_reset(device_t dev) 403 { 404 device_t parent = device_get_parent(dev); 405 struct ata_pci_controller *ctlr = device_get_softc(parent); 406 struct ata_channel *ch = device_get_softc(dev); 407 int mask, pshift, timeout, devs; 408 u_char *smap; 409 uint16_t pcs; 410 411 /* In combined mode, skip SATA stuff for PATA channel. */ 412 if ((ch->flags & ATA_SATA) == 0) 413 return (ata_generic_reset(dev)); 414 415 /* Do hard-reset on respective SATA ports. */ 416 smap = (u_char *)&ctlr->chipset_data + ch->unit * 2; 417 mask = 1 << smap[0]; 418 if ((ch->flags & ATA_NO_SLAVE) == 0) 419 mask |= (1 << smap[1]); 420 pci_write_config(parent, 0x92, 421 pci_read_config(parent, 0x92, 2) & ~mask, 2); 422 DELAY(10); 423 pci_write_config(parent, 0x92, 424 pci_read_config(parent, 0x92, 2) | mask, 2); 425 426 /* Wait up to 1 sec for "connect well". */ 427 if (ctlr->chip->cfg1 & (INTEL_6CH | INTEL_6CH2)) 428 pshift = 8; 429 else 430 pshift = 4; 431 for (timeout = 0; timeout < 100 ; timeout++) { 432 pcs = (pci_read_config(parent, 0x92, 2) >> pshift) & mask; 433 if ((pcs == mask) && (ATA_IDX_INB(ch, ATA_STATUS) != 0xff)) 434 break; 435 ata_udelay(10000); 436 } 437 438 if (bootverbose) 439 device_printf(dev, "SATA reset: ports status=0x%02x\n", pcs); 440 /* If any device found, do soft-reset. */ 441 if (ch->hw.pm_read != NULL) { 442 devs = ata_sata_phy_reset(dev, 0, 2) ? ATA_ATA_MASTER : 0; 443 if ((ch->flags & ATA_NO_SLAVE) == 0) 444 devs |= ata_sata_phy_reset(dev, 1, 2) ? 445 ATA_ATA_SLAVE : 0; 446 } else { 447 devs = (pcs & (1 << smap[0])) ? ATA_ATA_MASTER : 0; 448 if ((ch->flags & ATA_NO_SLAVE) == 0) 449 devs |= (pcs & (1 << smap[1])) ? 450 ATA_ATA_SLAVE : 0; 451 } 452 if (devs) { 453 ata_generic_reset(dev); 454 /* Reset may give fake slave when only ATAPI master present. */ 455 ch->devices &= (devs | (devs * ATA_ATAPI_MASTER)); 456 } else 457 ch->devices = 0; 458 } 459 460 static int 461 ata_intel_old_setmode(device_t dev, int target, int mode) 462 { 463 device_t parent = device_get_parent(dev); 464 struct ata_pci_controller *ctlr = device_get_softc(parent); 465 466 mode = min(mode, ctlr->chip->max_dma); 467 return (mode); 468 } 469 470 static int 471 ata_intel_new_setmode(device_t dev, int target, int mode) 472 { 473 device_t parent = device_get_parent(dev); 474 struct ata_pci_controller *ctlr = device_get_softc(parent); 475 struct ata_channel *ch = device_get_softc(dev); 476 int devno = (ch->unit << 1) + target; 477 int piomode; 478 u_int32_t reg40 = pci_read_config(parent, 0x40, 4); 479 u_int8_t reg44 = pci_read_config(parent, 0x44, 1); 480 u_int8_t reg48 = pci_read_config(parent, 0x48, 1); 481 u_int16_t reg4a = pci_read_config(parent, 0x4a, 2); 482 u_int16_t reg54 = pci_read_config(parent, 0x54, 2); 483 u_int32_t mask40 = 0, new40 = 0; 484 u_int8_t mask44 = 0, new44 = 0; 485 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x00, 0x21, 0x23 }; 486 u_int8_t utimings[] = { 0x00, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02 }; 487 488 /* In combined mode, skip PATA stuff for SATA channel. */ 489 if (ch->flags & ATA_SATA) 490 return (ata_sata_setmode(dev, target, mode)); 491 492 mode = min(mode, ctlr->chip->max_dma); 493 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 494 !(reg54 & (0x10 << devno))) { 495 ata_print_cable(dev, "controller"); 496 mode = ATA_UDMA2; 497 } 498 /* Enable/disable UDMA and set timings. */ 499 if (mode >= ATA_UDMA0) { 500 pci_write_config(parent, 0x48, reg48 | (0x0001 << devno), 2); 501 pci_write_config(parent, 0x4a, 502 (reg4a & ~(0x3 << (devno << 2))) | 503 (utimings[mode & ATA_MODE_MASK] << (devno<<2)), 2); 504 piomode = ATA_PIO4; 505 } else { 506 pci_write_config(parent, 0x48, reg48 & ~(0x0001 << devno), 2); 507 pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (devno << 2))),2); 508 piomode = mode; 509 } 510 reg54 |= 0x0400; 511 /* Set UDMA reference clock (33/66/133MHz). */ 512 reg54 &= ~(0x1001 << devno); 513 if (mode >= ATA_UDMA5) 514 reg54 |= (0x1000 << devno); 515 else if (mode >= ATA_UDMA3) 516 reg54 |= (0x1 << devno); 517 pci_write_config(parent, 0x54, reg54, 2); 518 /* Allow PIO/WDMA timing controls. */ 519 reg40 &= ~0x00ff00ff; 520 reg40 |= 0x40774077; 521 /* Set PIO/WDMA timings. */ 522 if (target == 0) { 523 mask40 = 0x3300; 524 new40 = timings[ata_mode2idx(piomode)] << 8; 525 } else { 526 mask44 = 0x0f; 527 new44 = ((timings[ata_mode2idx(piomode)] & 0x30) >> 2) | 528 (timings[ata_mode2idx(piomode)] & 0x03); 529 } 530 if (ch->unit) { 531 mask40 <<= 16; 532 new40 <<= 16; 533 mask44 <<= 4; 534 new44 <<= 4; 535 } 536 pci_write_config(parent, 0x40, (reg40 & ~mask40) | new40, 4); 537 pci_write_config(parent, 0x44, (reg44 & ~mask44) | new44, 1); 538 return (mode); 539 } 540 541 static int 542 ata_intel_sch_setmode(device_t dev, int target, int mode) 543 { 544 device_t parent = device_get_parent(dev); 545 struct ata_pci_controller *ctlr = device_get_softc(parent); 546 u_int8_t dtim = 0x80 + (target << 2); 547 u_int32_t tim = pci_read_config(parent, dtim, 4); 548 int piomode; 549 550 mode = min(mode, ctlr->chip->max_dma); 551 if (mode >= ATA_UDMA0) { 552 tim |= (0x1 << 31); 553 tim &= ~(0x7 << 16); 554 tim |= ((mode & ATA_MODE_MASK) << 16); 555 piomode = ATA_PIO4; 556 } else if (mode >= ATA_WDMA0) { 557 tim &= ~(0x1 << 31); 558 tim &= ~(0x3 << 8); 559 tim |= ((mode & ATA_MODE_MASK) << 8); 560 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 : 561 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4; 562 } else 563 piomode = mode; 564 tim &= ~(0x7); 565 tim |= (piomode & 0x7); 566 pci_write_config(parent, dtim, tim, 4); 567 return (mode); 568 } 569 570 static int 571 ata_intel_sata_getrev(device_t dev, int target) 572 { 573 struct ata_channel *ch = device_get_softc(dev); 574 uint32_t status; 575 576 if (ata_sata_scr_read(ch, target, ATA_SSTATUS, &status) == 0) 577 return ((status & 0x0f0) >> 4); 578 return (0xff); 579 } 580 581 static int 582 ata_intel_sata_status(device_t dev) 583 { 584 struct ata_channel *ch = device_get_softc(dev); 585 586 ata_sata_phy_check_events(dev, 0); 587 if ((ch->flags & ATA_NO_SLAVE) == 0) 588 ata_sata_phy_check_events(dev, 1); 589 590 return ata_pci_status(dev); 591 } 592 593 static int 594 ata_intel_sata_ahci_read(device_t dev, int port, int reg, u_int32_t *result) 595 { 596 struct ata_pci_controller *ctlr; 597 struct ata_channel *ch; 598 device_t parent; 599 u_char *smap; 600 int offset; 601 602 parent = device_get_parent(dev); 603 ctlr = device_get_softc(parent); 604 ch = device_get_softc(dev); 605 port = (port == 1) ? 1 : 0; 606 smap = (u_char *)&ctlr->chipset_data + ch->unit * 2; 607 offset = 0x100 + smap[port] * 0x80; 608 switch (reg) { 609 case ATA_SSTATUS: 610 reg = 0x28; 611 break; 612 case ATA_SCONTROL: 613 reg = 0x2c; 614 break; 615 case ATA_SERROR: 616 reg = 0x30; 617 break; 618 default: 619 return (EINVAL); 620 } 621 *result = ATA_INL(ctlr->r_res2, offset + reg); 622 return (0); 623 } 624 625 static int 626 ata_intel_sata_cscr_read(device_t dev, int port, int reg, u_int32_t *result) 627 { 628 struct ata_pci_controller *ctlr; 629 struct ata_channel *ch; 630 device_t parent; 631 u_char *smap; 632 633 parent = device_get_parent(dev); 634 ctlr = device_get_softc(parent); 635 ch = device_get_softc(dev); 636 smap = (u_char *)&ctlr->chipset_data + ch->unit * 2; 637 port = (port == 1) ? 1 : 0; 638 switch (reg) { 639 case ATA_SSTATUS: 640 reg = 0; 641 break; 642 case ATA_SERROR: 643 reg = 1; 644 break; 645 case ATA_SCONTROL: 646 reg = 2; 647 break; 648 default: 649 return (EINVAL); 650 } 651 pci_write_config(parent, 0xa0, 652 0x50 + smap[port] * 0x10 + reg * 4, 4); 653 *result = pci_read_config(parent, 0xa4, 4); 654 return (0); 655 } 656 657 static int 658 ata_intel_sata_sidpr_read(device_t dev, int port, int reg, u_int32_t *result) 659 { 660 struct ata_pci_controller *ctlr; 661 struct ata_channel *ch; 662 device_t parent; 663 664 parent = device_get_parent(dev); 665 ctlr = device_get_softc(parent); 666 ch = device_get_softc(dev); 667 port = (port == 1) ? 1 : 0; 668 switch (reg) { 669 case ATA_SSTATUS: 670 reg = 0; 671 break; 672 case ATA_SCONTROL: 673 reg = 1; 674 break; 675 case ATA_SERROR: 676 reg = 2; 677 break; 678 default: 679 return (EINVAL); 680 } 681 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, ((ch->unit * 2 + port) << 8) + reg); 682 *result = ATA_IDX_INL(ch, ATA_IDX_DATA); 683 return (0); 684 } 685 686 static int 687 ata_intel_sata_ahci_write(device_t dev, int port, int reg, u_int32_t value) 688 { 689 struct ata_pci_controller *ctlr; 690 struct ata_channel *ch; 691 device_t parent; 692 u_char *smap; 693 int offset; 694 695 parent = device_get_parent(dev); 696 ctlr = device_get_softc(parent); 697 ch = device_get_softc(dev); 698 port = (port == 1) ? 1 : 0; 699 smap = (u_char *)&ctlr->chipset_data + ch->unit * 2; 700 offset = 0x100 + smap[port] * 0x80; 701 switch (reg) { 702 case ATA_SSTATUS: 703 reg = 0x28; 704 break; 705 case ATA_SCONTROL: 706 reg = 0x2c; 707 break; 708 case ATA_SERROR: 709 reg = 0x30; 710 break; 711 default: 712 return (EINVAL); 713 } 714 ATA_OUTL(ctlr->r_res2, offset + reg, value); 715 return (0); 716 } 717 718 static int 719 ata_intel_sata_cscr_write(device_t dev, int port, int reg, u_int32_t value) 720 { 721 struct ata_pci_controller *ctlr; 722 struct ata_channel *ch; 723 device_t parent; 724 u_char *smap; 725 726 parent = device_get_parent(dev); 727 ctlr = device_get_softc(parent); 728 ch = device_get_softc(dev); 729 smap = (u_char *)&ctlr->chipset_data + ch->unit * 2; 730 port = (port == 1) ? 1 : 0; 731 switch (reg) { 732 case ATA_SSTATUS: 733 reg = 0; 734 break; 735 case ATA_SERROR: 736 reg = 1; 737 break; 738 case ATA_SCONTROL: 739 reg = 2; 740 break; 741 default: 742 return (EINVAL); 743 } 744 pci_write_config(parent, 0xa0, 745 0x50 + smap[port] * 0x10 + reg * 4, 4); 746 pci_write_config(parent, 0xa4, value, 4); 747 return (0); 748 } 749 750 static int 751 ata_intel_sata_sidpr_write(device_t dev, int port, int reg, u_int32_t value) 752 { 753 struct ata_pci_controller *ctlr; 754 struct ata_channel *ch; 755 device_t parent; 756 757 parent = device_get_parent(dev); 758 ctlr = device_get_softc(parent); 759 ch = device_get_softc(dev); 760 port = (port == 1) ? 1 : 0; 761 switch (reg) { 762 case ATA_SSTATUS: 763 reg = 0; 764 break; 765 case ATA_SCONTROL: 766 reg = 1; 767 break; 768 case ATA_SERROR: 769 reg = 2; 770 break; 771 default: 772 return (EINVAL); 773 } 774 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, ((ch->unit * 2 + port) << 8) + reg); 775 ATA_IDX_OUTL(ch, ATA_IDX_DATA, value); 776 return (0); 777 } 778 779 static int 780 ata_intel_31244_ch_attach(device_t dev) 781 { 782 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 783 struct ata_channel *ch = device_get_softc(dev); 784 int i; 785 int ch_offset; 786 787 ata_pci_dmainit(dev); 788 789 ch_offset = 0x200 + ch->unit * 0x200; 790 791 for (i = ATA_DATA; i < ATA_MAX_RES; i++) 792 ch->r_io[i].res = ctlr->r_res2; 793 794 /* setup ATA registers */ 795 ch->r_io[ATA_DATA].offset = ch_offset + 0x00; 796 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06; 797 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08; 798 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c; 799 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; 800 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14; 801 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18; 802 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d; 803 ch->r_io[ATA_ERROR].offset = ch_offset + 0x04; 804 ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c; 805 ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28; 806 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29; 807 808 /* setup DMA registers */ 809 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100; 810 ch->r_io[ATA_SERROR].offset = ch_offset + 0x104; 811 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108; 812 813 /* setup SATA registers */ 814 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70; 815 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72; 816 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74; 817 818 ch->flags |= ATA_NO_SLAVE; 819 ch->flags |= ATA_SATA; 820 ata_pci_hw(dev); 821 ch->hw.status = ata_intel_31244_status; 822 ch->hw.tf_write = ata_intel_31244_tf_write; 823 824 /* enable PHY state change interrupt */ 825 ATA_OUTL(ctlr->r_res2, 0x4, 826 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3))); 827 return 0; 828 } 829 830 static int 831 ata_intel_31244_ch_detach(device_t dev) 832 { 833 834 ata_pci_dmafini(dev); 835 return (0); 836 } 837 838 static int 839 ata_intel_31244_status(device_t dev) 840 { 841 /* do we have any PHY events ? */ 842 ata_sata_phy_check_events(dev, -1); 843 844 /* any drive action to take care of ? */ 845 return ata_pci_status(dev); 846 } 847 848 static void 849 ata_intel_31244_tf_write(struct ata_request *request) 850 { 851 struct ata_channel *ch = device_get_softc(request->parent); 852 #ifndef ATA_CAM 853 struct ata_device *atadev = device_get_softc(request->dev); 854 #endif 855 856 if (request->flags & ATA_R_48BIT) { 857 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature); 858 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count); 859 ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) | 860 (request->u.ata.lba & 0x00ff)); 861 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) | 862 ((request->u.ata.lba >> 8) & 0x00ff)); 863 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) | 864 ((request->u.ata.lba >> 16) & 0x00ff)); 865 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit)); 866 } 867 else { 868 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 869 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 870 #ifndef ATA_CAM 871 if (atadev->flags & ATA_D_USE_CHS) { 872 int heads, sectors; 873 874 if (atadev->param.atavalid & ATA_FLAG_54_58) { 875 heads = atadev->param.current_heads; 876 sectors = atadev->param.current_sectors; 877 } 878 else { 879 heads = atadev->param.heads; 880 sectors = atadev->param.sectors; 881 } 882 ATA_IDX_OUTB(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1); 883 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 884 (request->u.ata.lba / (sectors * heads))); 885 ATA_IDX_OUTB(ch, ATA_CYL_MSB, 886 (request->u.ata.lba / (sectors * heads)) >> 8); 887 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit) | 888 (((request->u.ata.lba% (sectors * heads)) / 889 sectors) & 0xf)); 890 } 891 else { 892 #endif 893 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 894 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 895 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 896 ATA_IDX_OUTB(ch, ATA_DRIVE, 897 ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) | 898 ((request->u.ata.lba >> 24) & 0x0f)); 899 #ifndef ATA_CAM 900 } 901 #endif 902 } 903 } 904 905 static void 906 ata_intel_31244_reset(device_t dev) 907 { 908 struct ata_channel *ch = device_get_softc(dev); 909 910 if (ata_sata_phy_reset(dev, -1, 1)) 911 ata_generic_reset(dev); 912 else 913 ch->devices = 0; 914 } 915 916 ATA_DECLARE_DRIVER(ata_intel); 917 MODULE_DEPEND(ata_intel, ata_ahci, 1, 1, 1); 918