1 /*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ata.h" 31 #include <sys/param.h> 32 #include <sys/module.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/ata.h> 36 #include <sys/bus.h> 37 #include <sys/endian.h> 38 #include <sys/malloc.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/sema.h> 42 #include <sys/taskqueue.h> 43 #include <vm/uma.h> 44 #include <machine/stdarg.h> 45 #include <machine/resource.h> 46 #include <machine/bus.h> 47 #include <sys/rman.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/ata/ata-all.h> 51 #include <dev/ata/ata-pci.h> 52 #include <ata_if.h> 53 54 /* local prototypes */ 55 static int ata_intel_chipinit(device_t dev); 56 static int ata_intel_chipdeinit(device_t dev); 57 static int ata_intel_ch_attach(device_t dev); 58 static void ata_intel_reset(device_t dev); 59 static int ata_intel_old_setmode(device_t dev, int target, int mode); 60 static int ata_intel_new_setmode(device_t dev, int target, int mode); 61 static int ata_intel_sch_setmode(device_t dev, int target, int mode); 62 static int ata_intel_sata_getrev(device_t dev, int target); 63 static int ata_intel_sata_status(device_t dev); 64 static int ata_intel_sata_ahci_read(device_t dev, int port, 65 int reg, u_int32_t *result); 66 static int ata_intel_sata_cscr_read(device_t dev, int port, 67 int reg, u_int32_t *result); 68 static int ata_intel_sata_sidpr_read(device_t dev, int port, 69 int reg, u_int32_t *result); 70 static int ata_intel_sata_ahci_write(device_t dev, int port, 71 int reg, u_int32_t result); 72 static int ata_intel_sata_cscr_write(device_t dev, int port, 73 int reg, u_int32_t result); 74 static int ata_intel_sata_sidpr_write(device_t dev, int port, 75 int reg, u_int32_t result); 76 static int ata_intel_31244_ch_attach(device_t dev); 77 static int ata_intel_31244_ch_detach(device_t dev); 78 static int ata_intel_31244_status(device_t dev); 79 static void ata_intel_31244_tf_write(struct ata_request *request); 80 static void ata_intel_31244_reset(device_t dev); 81 82 /* misc defines */ 83 #define INTEL_AHCI 1 84 #define INTEL_ICH5 2 85 #define INTEL_6CH 4 86 #define INTEL_6CH2 8 87 #define INTEL_ICH7 16 88 89 struct ata_intel_data { 90 struct mtx lock; 91 u_char smap[4]; 92 }; 93 94 #define ATA_INTEL_SMAP(ctlr, ch) \ 95 &((struct ata_intel_data *)((ctlr)->chipset_data))->smap[(ch)->unit * 2] 96 #define ATA_INTEL_LOCK(ctlr) \ 97 mtx_lock(&((struct ata_intel_data *)((ctlr)->chipset_data))->lock) 98 #define ATA_INTEL_UNLOCK(ctlr) \ 99 mtx_unlock(&((struct ata_intel_data *)((ctlr)->chipset_data))->lock) 100 101 /* 102 * Intel chipset support functions 103 */ 104 static int 105 ata_intel_probe(device_t dev) 106 { 107 struct ata_pci_controller *ctlr = device_get_softc(dev); 108 static struct ata_chip_id ids[] = 109 {{ ATA_I82371FB, 0, 0, 2, ATA_WDMA2, "PIIX" }, 110 { ATA_I82371SB, 0, 0, 2, ATA_WDMA2, "PIIX3" }, 111 { ATA_I82371AB, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 112 { ATA_I82443MX, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 113 { ATA_I82451NX, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 114 { ATA_I82801AB, 0, 0, 2, ATA_UDMA2, "ICH0" }, 115 { ATA_I82801AA, 0, 0, 2, ATA_UDMA4, "ICH" }, 116 { ATA_I82372FB, 0, 0, 2, ATA_UDMA4, "ICH" }, 117 { ATA_I82801BA, 0, 0, 2, ATA_UDMA5, "ICH2" }, 118 { ATA_I82801BA_1, 0, 0, 2, ATA_UDMA5, "ICH2" }, 119 { ATA_I82801CA, 0, 0, 2, ATA_UDMA5, "ICH3" }, 120 { ATA_I82801CA_1, 0, 0, 2, ATA_UDMA5, "ICH3" }, 121 { ATA_I82801DB, 0, 0, 2, ATA_UDMA5, "ICH4" }, 122 { ATA_I82801DB_1, 0, 0, 2, ATA_UDMA5, "ICH4" }, 123 { ATA_I82801EB, 0, 0, 2, ATA_UDMA5, "ICH5" }, 124 { ATA_I82801EB_S1, 0, INTEL_ICH5, 2, ATA_SA150, "ICH5" }, 125 { ATA_I82801EB_R1, 0, INTEL_ICH5, 2, ATA_SA150, "ICH5" }, 126 { ATA_I6300ESB, 0, 0, 2, ATA_UDMA5, "6300ESB" }, 127 { ATA_I6300ESB_S1, 0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" }, 128 { ATA_I6300ESB_R1, 0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" }, 129 { ATA_I82801FB, 0, 0, 2, ATA_UDMA5, "ICH6" }, 130 { ATA_I82801FB_S1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6" }, 131 { ATA_I82801FB_R1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6" }, 132 { ATA_I82801FBM, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6M" }, 133 { ATA_I82801GB, 0, 0, 1, ATA_UDMA5, "ICH7" }, 134 { ATA_I82801GB_S1, 0, INTEL_ICH7, 0, ATA_SA300, "ICH7" }, 135 { ATA_I82801GB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" }, 136 { ATA_I82801GB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" }, 137 { ATA_I82801GBM_S1, 0, INTEL_ICH7, 0, ATA_SA150, "ICH7M" }, 138 { ATA_I82801GBM_R1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" }, 139 { ATA_I82801GBM_AH, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" }, 140 { ATA_I63XXESB2, 0, 0, 1, ATA_UDMA5, "63XXESB2" }, 141 { ATA_I63XXESB2_S1, 0, 0, 0, ATA_SA300, "63XXESB2" }, 142 { ATA_I63XXESB2_S2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 143 { ATA_I63XXESB2_R1, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 144 { ATA_I63XXESB2_R2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 145 { ATA_I82801HB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH8" }, 146 { ATA_I82801HB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH8" }, 147 { ATA_I82801HB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 148 { ATA_I82801HB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 149 { ATA_I82801HB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 150 { ATA_I82801HBM, 0, 0, 1, ATA_UDMA5, "ICH8M" }, 151 { ATA_I82801HBM_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH8M" }, 152 { ATA_I82801HBM_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" }, 153 { ATA_I82801HBM_S3, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" }, 154 { ATA_I82801IB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH9" }, 155 { ATA_I82801IB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9" }, 156 { ATA_I82801IB_S3, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9" }, 157 { ATA_I82801IB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 158 { ATA_I82801IB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 159 { ATA_I82801IB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 160 { ATA_I82801IBM_S1, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9M" }, 161 { ATA_I82801IBM_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9M" }, 162 { ATA_I82801IBM_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9M" }, 163 { ATA_I82801IBM_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9M" }, 164 { ATA_I82801JIB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, 165 { ATA_I82801JIB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 166 { ATA_I82801JIB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 167 { ATA_I82801JIB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, 168 { ATA_I82801JD_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, 169 { ATA_I82801JD_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 170 { ATA_I82801JD_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 171 { ATA_I82801JD_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, 172 { ATA_I82801JI_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, 173 { ATA_I82801JI_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 174 { ATA_I82801JI_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 175 { ATA_I82801JI_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, 176 { ATA_5Series_S1, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 177 { ATA_5Series_S2, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 178 { ATA_5Series_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 179 { ATA_5Series_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 180 { ATA_5Series_R1, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 181 { ATA_5Series_S3, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 182 { ATA_5Series_S4, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 183 { ATA_5Series_AH3, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 184 { ATA_5Series_R2, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 185 { ATA_5Series_S5, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 186 { ATA_5Series_S6, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 187 { ATA_5Series_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 188 { ATA_CPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Cougar Point" }, 189 { ATA_CPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Cougar Point" }, 190 { ATA_CPT_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, 191 { ATA_CPT_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, 192 { ATA_CPT_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, 193 { ATA_CPT_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, 194 { ATA_CPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" }, 195 { ATA_CPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" }, 196 { ATA_PBG_S1, 0, INTEL_6CH, 0, ATA_SA300, "Patsburg" }, 197 { ATA_PBG_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" }, 198 { ATA_PBG_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" }, 199 { ATA_PBG_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" }, 200 { ATA_PBG_S2, 0, INTEL_6CH2, 0, ATA_SA300, "Patsburg" }, 201 { ATA_PPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Panther Point" }, 202 { ATA_PPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Panther Point" }, 203 { ATA_PPT_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 204 { ATA_PPT_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 205 { ATA_PPT_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 206 { ATA_PPT_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 207 { ATA_PPT_R3, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 208 { ATA_PPT_R4, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 209 { ATA_PPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Panther Point" }, 210 { ATA_PPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Panther Point" }, 211 { ATA_PPT_R5, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 212 { ATA_PPT_R6, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 213 { ATA_I31244, 0, 0, 2, ATA_SA150, "31244" }, 214 { ATA_ISCH, 0, 0, 1, ATA_UDMA5, "SCH" }, 215 { ATA_DH89XXCC, 0, INTEL_AHCI, 0, ATA_SA300, "DH89xxCC" }, 216 { 0, 0, 0, 0, 0, 0}}; 217 218 if (pci_get_vendor(dev) != ATA_INTEL_ID) 219 return ENXIO; 220 221 if (!(ctlr->chip = ata_match_chip(dev, ids))) 222 return ENXIO; 223 224 ata_set_desc(dev); 225 ctlr->chipinit = ata_intel_chipinit; 226 ctlr->chipdeinit = ata_intel_chipdeinit; 227 return (BUS_PROBE_DEFAULT); 228 } 229 230 static int 231 ata_intel_chipinit(device_t dev) 232 { 233 struct ata_pci_controller *ctlr = device_get_softc(dev); 234 struct ata_intel_data *data; 235 236 if (ata_setup_interrupt(dev, ata_generic_intr)) 237 return ENXIO; 238 239 data = malloc(sizeof(struct ata_intel_data), M_ATAPCI, M_WAITOK | M_ZERO); 240 mtx_init(&data->lock, "Intel SATA lock", NULL, MTX_DEF); 241 ctlr->chipset_data = (void *)data; 242 243 /* good old PIIX needs special treatment (not implemented) */ 244 if (ctlr->chip->chipid == ATA_I82371FB) { 245 ctlr->setmode = ata_intel_old_setmode; 246 } 247 248 /* the intel 31244 needs special care if in DPA mode */ 249 else if (ctlr->chip->chipid == ATA_I31244) { 250 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) { 251 ctlr->r_type2 = SYS_RES_MEMORY; 252 ctlr->r_rid2 = PCIR_BAR(0); 253 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 254 &ctlr->r_rid2, 255 RF_ACTIVE))) 256 return ENXIO; 257 ctlr->channels = 4; 258 ctlr->ch_attach = ata_intel_31244_ch_attach; 259 ctlr->ch_detach = ata_intel_31244_ch_detach; 260 ctlr->reset = ata_intel_31244_reset; 261 } 262 ctlr->setmode = ata_sata_setmode; 263 ctlr->getrev = ata_sata_getrev; 264 } 265 /* SCH */ 266 else if (ctlr->chip->chipid == ATA_ISCH) { 267 ctlr->channels = 1; 268 ctlr->ch_attach = ata_intel_ch_attach; 269 ctlr->ch_detach = ata_pci_ch_detach; 270 ctlr->setmode = ata_intel_sch_setmode; 271 } 272 /* non SATA intel chips goes here */ 273 else if (ctlr->chip->max_dma < ATA_SA150) { 274 ctlr->channels = ctlr->chip->cfg2; 275 ctlr->ch_attach = ata_intel_ch_attach; 276 ctlr->ch_detach = ata_pci_ch_detach; 277 ctlr->setmode = ata_intel_new_setmode; 278 } 279 280 /* SATA parts can be either compat or AHCI */ 281 else { 282 /* force all ports active "the legacy way" */ 283 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f, 2); 284 285 ctlr->ch_attach = ata_intel_ch_attach; 286 ctlr->ch_detach = ata_pci_ch_detach; 287 ctlr->reset = ata_intel_reset; 288 289 /* 290 * if we have AHCI capability and AHCI or RAID mode enabled 291 * in BIOS we try for AHCI mode 292 */ 293 if ((ctlr->chip->cfg1 & INTEL_AHCI) && 294 (pci_read_config(dev, 0x90, 1) & 0xc0) && 295 (ata_ahci_chipinit(dev) != ENXIO)) 296 return 0; 297 298 /* BAR(5) may point to SATA interface registers */ 299 if ((ctlr->chip->cfg1 & INTEL_ICH7)) { 300 ctlr->r_type2 = SYS_RES_MEMORY; 301 ctlr->r_rid2 = PCIR_BAR(5); 302 ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 303 &ctlr->r_rid2, RF_ACTIVE); 304 if (ctlr->r_res2 != NULL) { 305 /* Set SCRAE bit to enable registers access. */ 306 pci_write_config(dev, 0x94, 307 pci_read_config(dev, 0x94, 4) | (1 << 9), 4); 308 /* Set Ports Implemented register bits. */ 309 ATA_OUTL(ctlr->r_res2, 0x0C, 310 ATA_INL(ctlr->r_res2, 0x0C) | 0xf); 311 } 312 /* Skip BAR(5) on ICH8M Apples, system locks up on access. */ 313 } else if (ctlr->chip->chipid != ATA_I82801HBM_S1 || 314 pci_get_subvendor(dev) != 0x106b) { 315 ctlr->r_type2 = SYS_RES_IOPORT; 316 ctlr->r_rid2 = PCIR_BAR(5); 317 ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 318 &ctlr->r_rid2, RF_ACTIVE); 319 } 320 if (ctlr->r_res2 != NULL || 321 (ctlr->chip->cfg1 & INTEL_ICH5)) 322 ctlr->getrev = ata_intel_sata_getrev; 323 ctlr->setmode = ata_sata_setmode; 324 } 325 return 0; 326 } 327 328 static int 329 ata_intel_chipdeinit(device_t dev) 330 { 331 struct ata_pci_controller *ctlr = device_get_softc(dev); 332 struct ata_intel_data *data; 333 334 data = ctlr->chipset_data; 335 mtx_destroy(&data->lock); 336 free(data, M_ATAPCI); 337 ctlr->chipset_data = NULL; 338 return (0); 339 } 340 341 static int 342 ata_intel_ch_attach(device_t dev) 343 { 344 struct ata_pci_controller *ctlr; 345 struct ata_channel *ch; 346 u_char *smap; 347 u_int map; 348 349 /* setup the usual register normal pci style */ 350 if (ata_pci_ch_attach(dev)) 351 return (ENXIO); 352 353 ctlr = device_get_softc(device_get_parent(dev)); 354 ch = device_get_softc(dev); 355 356 /* if r_res2 is valid it points to SATA interface registers */ 357 if (ctlr->r_res2) { 358 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 359 ch->r_io[ATA_IDX_ADDR].offset = 0x00; 360 ch->r_io[ATA_IDX_DATA].res = ctlr->r_res2; 361 ch->r_io[ATA_IDX_DATA].offset = 0x04; 362 } 363 364 ch->flags |= ATA_ALWAYS_DMASTAT; 365 if (ctlr->chip->max_dma >= ATA_SA150) { 366 smap = ATA_INTEL_SMAP(ctlr, ch); 367 map = pci_read_config(device_get_parent(dev), 0x90, 1); 368 if (ctlr->chip->cfg1 & INTEL_ICH5) { 369 map &= 0x07; 370 if ((map & 0x04) == 0) { 371 ch->flags |= ATA_SATA; 372 ch->flags |= ATA_NO_SLAVE; 373 smap[0] = (map & 0x01) ^ ch->unit; 374 smap[1] = 0; 375 } else if ((map & 0x02) == 0 && ch->unit == 0) { 376 ch->flags |= ATA_SATA; 377 smap[0] = (map & 0x01) ? 1 : 0; 378 smap[1] = (map & 0x01) ? 0 : 1; 379 } else if ((map & 0x02) != 0 && ch->unit == 1) { 380 ch->flags |= ATA_SATA; 381 smap[0] = (map & 0x01) ? 1 : 0; 382 smap[1] = (map & 0x01) ? 0 : 1; 383 } 384 } else if (ctlr->chip->cfg1 & INTEL_6CH2) { 385 ch->flags |= ATA_SATA; 386 ch->flags |= ATA_NO_SLAVE; 387 smap[0] = (ch->unit == 0) ? 0 : 1; 388 smap[1] = 0; 389 } else { 390 map &= 0x03; 391 if (map == 0x00) { 392 ch->flags |= ATA_SATA; 393 smap[0] = (ch->unit == 0) ? 0 : 1; 394 smap[1] = (ch->unit == 0) ? 2 : 3; 395 } else if (map == 0x02 && ch->unit == 0) { 396 ch->flags |= ATA_SATA; 397 smap[0] = 0; 398 smap[1] = 2; 399 } else if (map == 0x01 && ch->unit == 1) { 400 ch->flags |= ATA_SATA; 401 smap[0] = 1; 402 smap[1] = 3; 403 } 404 } 405 if (ch->flags & ATA_SATA) { 406 if ((ctlr->chip->cfg1 & INTEL_ICH5)) { 407 ch->flags |= ATA_PERIODIC_POLL; 408 ch->hw.status = ata_intel_sata_status; 409 ch->hw.pm_read = ata_intel_sata_cscr_read; 410 ch->hw.pm_write = ata_intel_sata_cscr_write; 411 } else if (ctlr->r_res2) { 412 ch->flags |= ATA_PERIODIC_POLL; 413 ch->hw.status = ata_intel_sata_status; 414 if ((ctlr->chip->cfg1 & INTEL_ICH7)) { 415 ch->hw.pm_read = ata_intel_sata_ahci_read; 416 ch->hw.pm_write = ata_intel_sata_ahci_write; 417 } else { 418 ch->hw.pm_read = ata_intel_sata_sidpr_read; 419 ch->hw.pm_write = ata_intel_sata_sidpr_write; 420 }; 421 } 422 if (ch->hw.pm_write != NULL) { 423 ata_sata_scr_write(ch, 0, 424 ATA_SERROR, 0xffffffff); 425 if ((ch->flags & ATA_NO_SLAVE) == 0) { 426 ata_sata_scr_write(ch, 1, 427 ATA_SERROR, 0xffffffff); 428 } 429 } 430 } else 431 ctlr->setmode = ata_intel_new_setmode; 432 } else if (ctlr->chip->chipid != ATA_ISCH) 433 ch->flags |= ATA_CHECKS_CABLE; 434 return (0); 435 } 436 437 static void 438 ata_intel_reset(device_t dev) 439 { 440 device_t parent = device_get_parent(dev); 441 struct ata_pci_controller *ctlr = device_get_softc(parent); 442 struct ata_channel *ch = device_get_softc(dev); 443 int mask, pshift, timeout, devs; 444 u_char *smap; 445 uint16_t pcs; 446 447 /* In combined mode, skip SATA stuff for PATA channel. */ 448 if ((ch->flags & ATA_SATA) == 0) 449 return (ata_generic_reset(dev)); 450 451 /* Do hard-reset on respective SATA ports. */ 452 smap = ATA_INTEL_SMAP(ctlr, ch); 453 mask = 1 << smap[0]; 454 if ((ch->flags & ATA_NO_SLAVE) == 0) 455 mask |= (1 << smap[1]); 456 pci_write_config(parent, 0x92, 457 pci_read_config(parent, 0x92, 2) & ~mask, 2); 458 DELAY(10); 459 pci_write_config(parent, 0x92, 460 pci_read_config(parent, 0x92, 2) | mask, 2); 461 462 /* Wait up to 1 sec for "connect well". */ 463 if (ctlr->chip->cfg1 & (INTEL_6CH | INTEL_6CH2)) 464 pshift = 8; 465 else 466 pshift = 4; 467 for (timeout = 0; timeout < 100 ; timeout++) { 468 pcs = (pci_read_config(parent, 0x92, 2) >> pshift) & mask; 469 if ((pcs == mask) && (ATA_IDX_INB(ch, ATA_STATUS) != 0xff)) 470 break; 471 ata_udelay(10000); 472 } 473 474 if (bootverbose) 475 device_printf(dev, "SATA reset: ports status=0x%02x\n", pcs); 476 /* If any device found, do soft-reset. */ 477 if (ch->hw.pm_read != NULL) { 478 devs = ata_sata_phy_reset(dev, 0, 2) ? ATA_ATA_MASTER : 0; 479 if ((ch->flags & ATA_NO_SLAVE) == 0) 480 devs |= ata_sata_phy_reset(dev, 1, 2) ? 481 ATA_ATA_SLAVE : 0; 482 } else { 483 devs = (pcs & (1 << smap[0])) ? ATA_ATA_MASTER : 0; 484 if ((ch->flags & ATA_NO_SLAVE) == 0) 485 devs |= (pcs & (1 << smap[1])) ? 486 ATA_ATA_SLAVE : 0; 487 } 488 if (devs) { 489 ata_generic_reset(dev); 490 /* Reset may give fake slave when only ATAPI master present. */ 491 ch->devices &= (devs | (devs * ATA_ATAPI_MASTER)); 492 } else 493 ch->devices = 0; 494 } 495 496 static int 497 ata_intel_old_setmode(device_t dev, int target, int mode) 498 { 499 device_t parent = device_get_parent(dev); 500 struct ata_pci_controller *ctlr = device_get_softc(parent); 501 502 mode = min(mode, ctlr->chip->max_dma); 503 return (mode); 504 } 505 506 static int 507 ata_intel_new_setmode(device_t dev, int target, int mode) 508 { 509 device_t parent = device_get_parent(dev); 510 struct ata_pci_controller *ctlr = device_get_softc(parent); 511 struct ata_channel *ch = device_get_softc(dev); 512 int devno = (ch->unit << 1) + target; 513 int piomode; 514 u_int32_t reg40 = pci_read_config(parent, 0x40, 4); 515 u_int8_t reg44 = pci_read_config(parent, 0x44, 1); 516 u_int8_t reg48 = pci_read_config(parent, 0x48, 1); 517 u_int16_t reg4a = pci_read_config(parent, 0x4a, 2); 518 u_int16_t reg54 = pci_read_config(parent, 0x54, 2); 519 u_int32_t mask40 = 0, new40 = 0; 520 u_int8_t mask44 = 0, new44 = 0; 521 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x00, 0x21, 0x23 }; 522 u_int8_t utimings[] = { 0x00, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02 }; 523 524 /* In combined mode, skip PATA stuff for SATA channel. */ 525 if (ch->flags & ATA_SATA) 526 return (ata_sata_setmode(dev, target, mode)); 527 528 mode = min(mode, ctlr->chip->max_dma); 529 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 530 !(reg54 & (0x10 << devno))) { 531 ata_print_cable(dev, "controller"); 532 mode = ATA_UDMA2; 533 } 534 /* Enable/disable UDMA and set timings. */ 535 if (mode >= ATA_UDMA0) { 536 pci_write_config(parent, 0x48, reg48 | (0x0001 << devno), 2); 537 pci_write_config(parent, 0x4a, 538 (reg4a & ~(0x3 << (devno << 2))) | 539 (utimings[mode & ATA_MODE_MASK] << (devno<<2)), 2); 540 piomode = ATA_PIO4; 541 } else { 542 pci_write_config(parent, 0x48, reg48 & ~(0x0001 << devno), 2); 543 pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (devno << 2))),2); 544 piomode = mode; 545 } 546 reg54 |= 0x0400; 547 /* Set UDMA reference clock (33/66/133MHz). */ 548 reg54 &= ~(0x1001 << devno); 549 if (mode >= ATA_UDMA5) 550 reg54 |= (0x1000 << devno); 551 else if (mode >= ATA_UDMA3) 552 reg54 |= (0x1 << devno); 553 pci_write_config(parent, 0x54, reg54, 2); 554 /* Allow PIO/WDMA timing controls. */ 555 reg40 &= ~0x00ff00ff; 556 reg40 |= 0x40774077; 557 /* Set PIO/WDMA timings. */ 558 if (target == 0) { 559 mask40 = 0x3300; 560 new40 = timings[ata_mode2idx(piomode)] << 8; 561 } else { 562 mask44 = 0x0f; 563 new44 = ((timings[ata_mode2idx(piomode)] & 0x30) >> 2) | 564 (timings[ata_mode2idx(piomode)] & 0x03); 565 } 566 if (ch->unit) { 567 mask40 <<= 16; 568 new40 <<= 16; 569 mask44 <<= 4; 570 new44 <<= 4; 571 } 572 pci_write_config(parent, 0x40, (reg40 & ~mask40) | new40, 4); 573 pci_write_config(parent, 0x44, (reg44 & ~mask44) | new44, 1); 574 return (mode); 575 } 576 577 static int 578 ata_intel_sch_setmode(device_t dev, int target, int mode) 579 { 580 device_t parent = device_get_parent(dev); 581 struct ata_pci_controller *ctlr = device_get_softc(parent); 582 u_int8_t dtim = 0x80 + (target << 2); 583 u_int32_t tim = pci_read_config(parent, dtim, 4); 584 int piomode; 585 586 mode = min(mode, ctlr->chip->max_dma); 587 if (mode >= ATA_UDMA0) { 588 tim |= (0x1 << 31); 589 tim &= ~(0x7 << 16); 590 tim |= ((mode & ATA_MODE_MASK) << 16); 591 piomode = ATA_PIO4; 592 } else if (mode >= ATA_WDMA0) { 593 tim &= ~(0x1 << 31); 594 tim &= ~(0x3 << 8); 595 tim |= ((mode & ATA_MODE_MASK) << 8); 596 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 : 597 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4; 598 } else 599 piomode = mode; 600 tim &= ~(0x7); 601 tim |= (piomode & 0x7); 602 pci_write_config(parent, dtim, tim, 4); 603 return (mode); 604 } 605 606 static int 607 ata_intel_sata_getrev(device_t dev, int target) 608 { 609 struct ata_channel *ch = device_get_softc(dev); 610 uint32_t status; 611 612 if (ata_sata_scr_read(ch, target, ATA_SSTATUS, &status) == 0) 613 return ((status & 0x0f0) >> 4); 614 return (0xff); 615 } 616 617 static int 618 ata_intel_sata_status(device_t dev) 619 { 620 struct ata_channel *ch = device_get_softc(dev); 621 622 ata_sata_phy_check_events(dev, 0); 623 if ((ch->flags & ATA_NO_SLAVE) == 0) 624 ata_sata_phy_check_events(dev, 1); 625 626 return ata_pci_status(dev); 627 } 628 629 static int 630 ata_intel_sata_ahci_read(device_t dev, int port, int reg, u_int32_t *result) 631 { 632 struct ata_pci_controller *ctlr; 633 struct ata_channel *ch; 634 device_t parent; 635 u_char *smap; 636 int offset; 637 638 parent = device_get_parent(dev); 639 ctlr = device_get_softc(parent); 640 ch = device_get_softc(dev); 641 port = (port == 1) ? 1 : 0; 642 smap = ATA_INTEL_SMAP(ctlr, ch); 643 offset = 0x100 + smap[port] * 0x80; 644 switch (reg) { 645 case ATA_SSTATUS: 646 reg = 0x28; 647 break; 648 case ATA_SCONTROL: 649 reg = 0x2c; 650 break; 651 case ATA_SERROR: 652 reg = 0x30; 653 break; 654 default: 655 return (EINVAL); 656 } 657 *result = ATA_INL(ctlr->r_res2, offset + reg); 658 return (0); 659 } 660 661 static int 662 ata_intel_sata_cscr_read(device_t dev, int port, int reg, u_int32_t *result) 663 { 664 struct ata_pci_controller *ctlr; 665 struct ata_channel *ch; 666 device_t parent; 667 u_char *smap; 668 669 parent = device_get_parent(dev); 670 ctlr = device_get_softc(parent); 671 ch = device_get_softc(dev); 672 smap = ATA_INTEL_SMAP(ctlr, ch); 673 port = (port == 1) ? 1 : 0; 674 switch (reg) { 675 case ATA_SSTATUS: 676 reg = 0; 677 break; 678 case ATA_SERROR: 679 reg = 1; 680 break; 681 case ATA_SCONTROL: 682 reg = 2; 683 break; 684 default: 685 return (EINVAL); 686 } 687 ATA_INTEL_LOCK(ctlr); 688 pci_write_config(parent, 0xa0, 689 0x50 + smap[port] * 0x10 + reg * 4, 4); 690 *result = pci_read_config(parent, 0xa4, 4); 691 ATA_INTEL_UNLOCK(ctlr); 692 return (0); 693 } 694 695 static int 696 ata_intel_sata_sidpr_read(device_t dev, int port, int reg, u_int32_t *result) 697 { 698 struct ata_pci_controller *ctlr; 699 struct ata_channel *ch; 700 device_t parent; 701 702 parent = device_get_parent(dev); 703 ctlr = device_get_softc(parent); 704 ch = device_get_softc(dev); 705 port = (port == 1) ? 1 : 0; 706 switch (reg) { 707 case ATA_SSTATUS: 708 reg = 0; 709 break; 710 case ATA_SCONTROL: 711 reg = 1; 712 break; 713 case ATA_SERROR: 714 reg = 2; 715 break; 716 default: 717 return (EINVAL); 718 } 719 ATA_INTEL_LOCK(ctlr); 720 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, ((ch->unit * 2 + port) << 8) + reg); 721 *result = ATA_IDX_INL(ch, ATA_IDX_DATA); 722 ATA_INTEL_UNLOCK(ctlr); 723 return (0); 724 } 725 726 static int 727 ata_intel_sata_ahci_write(device_t dev, int port, int reg, u_int32_t value) 728 { 729 struct ata_pci_controller *ctlr; 730 struct ata_channel *ch; 731 device_t parent; 732 u_char *smap; 733 int offset; 734 735 parent = device_get_parent(dev); 736 ctlr = device_get_softc(parent); 737 ch = device_get_softc(dev); 738 port = (port == 1) ? 1 : 0; 739 smap = ATA_INTEL_SMAP(ctlr, ch); 740 offset = 0x100 + smap[port] * 0x80; 741 switch (reg) { 742 case ATA_SSTATUS: 743 reg = 0x28; 744 break; 745 case ATA_SCONTROL: 746 reg = 0x2c; 747 break; 748 case ATA_SERROR: 749 reg = 0x30; 750 break; 751 default: 752 return (EINVAL); 753 } 754 ATA_OUTL(ctlr->r_res2, offset + reg, value); 755 return (0); 756 } 757 758 static int 759 ata_intel_sata_cscr_write(device_t dev, int port, int reg, u_int32_t value) 760 { 761 struct ata_pci_controller *ctlr; 762 struct ata_channel *ch; 763 device_t parent; 764 u_char *smap; 765 766 parent = device_get_parent(dev); 767 ctlr = device_get_softc(parent); 768 ch = device_get_softc(dev); 769 smap = ATA_INTEL_SMAP(ctlr, ch); 770 port = (port == 1) ? 1 : 0; 771 switch (reg) { 772 case ATA_SSTATUS: 773 reg = 0; 774 break; 775 case ATA_SERROR: 776 reg = 1; 777 break; 778 case ATA_SCONTROL: 779 reg = 2; 780 break; 781 default: 782 return (EINVAL); 783 } 784 ATA_INTEL_LOCK(ctlr); 785 pci_write_config(parent, 0xa0, 786 0x50 + smap[port] * 0x10 + reg * 4, 4); 787 pci_write_config(parent, 0xa4, value, 4); 788 ATA_INTEL_UNLOCK(ctlr); 789 return (0); 790 } 791 792 static int 793 ata_intel_sata_sidpr_write(device_t dev, int port, int reg, u_int32_t value) 794 { 795 struct ata_pci_controller *ctlr; 796 struct ata_channel *ch; 797 device_t parent; 798 799 parent = device_get_parent(dev); 800 ctlr = device_get_softc(parent); 801 ch = device_get_softc(dev); 802 port = (port == 1) ? 1 : 0; 803 switch (reg) { 804 case ATA_SSTATUS: 805 reg = 0; 806 break; 807 case ATA_SCONTROL: 808 reg = 1; 809 break; 810 case ATA_SERROR: 811 reg = 2; 812 break; 813 default: 814 return (EINVAL); 815 } 816 ATA_INTEL_LOCK(ctlr); 817 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, ((ch->unit * 2 + port) << 8) + reg); 818 ATA_IDX_OUTL(ch, ATA_IDX_DATA, value); 819 ATA_INTEL_UNLOCK(ctlr); 820 return (0); 821 } 822 823 static int 824 ata_intel_31244_ch_attach(device_t dev) 825 { 826 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 827 struct ata_channel *ch = device_get_softc(dev); 828 int i; 829 int ch_offset; 830 831 ata_pci_dmainit(dev); 832 833 ch_offset = 0x200 + ch->unit * 0x200; 834 835 for (i = ATA_DATA; i < ATA_MAX_RES; i++) 836 ch->r_io[i].res = ctlr->r_res2; 837 838 /* setup ATA registers */ 839 ch->r_io[ATA_DATA].offset = ch_offset + 0x00; 840 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06; 841 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08; 842 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c; 843 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; 844 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14; 845 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18; 846 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d; 847 ch->r_io[ATA_ERROR].offset = ch_offset + 0x04; 848 ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c; 849 ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28; 850 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29; 851 852 /* setup DMA registers */ 853 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100; 854 ch->r_io[ATA_SERROR].offset = ch_offset + 0x104; 855 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108; 856 857 /* setup SATA registers */ 858 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70; 859 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72; 860 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74; 861 862 ch->flags |= ATA_NO_SLAVE; 863 ch->flags |= ATA_SATA; 864 ata_pci_hw(dev); 865 ch->hw.status = ata_intel_31244_status; 866 ch->hw.tf_write = ata_intel_31244_tf_write; 867 868 /* enable PHY state change interrupt */ 869 ATA_OUTL(ctlr->r_res2, 0x4, 870 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3))); 871 return 0; 872 } 873 874 static int 875 ata_intel_31244_ch_detach(device_t dev) 876 { 877 878 ata_pci_dmafini(dev); 879 return (0); 880 } 881 882 static int 883 ata_intel_31244_status(device_t dev) 884 { 885 /* do we have any PHY events ? */ 886 ata_sata_phy_check_events(dev, -1); 887 888 /* any drive action to take care of ? */ 889 return ata_pci_status(dev); 890 } 891 892 static void 893 ata_intel_31244_tf_write(struct ata_request *request) 894 { 895 struct ata_channel *ch = device_get_softc(request->parent); 896 #ifndef ATA_CAM 897 struct ata_device *atadev = device_get_softc(request->dev); 898 #endif 899 900 if (request->flags & ATA_R_48BIT) { 901 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature); 902 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count); 903 ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) | 904 (request->u.ata.lba & 0x00ff)); 905 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) | 906 ((request->u.ata.lba >> 8) & 0x00ff)); 907 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) | 908 ((request->u.ata.lba >> 16) & 0x00ff)); 909 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit)); 910 } 911 else { 912 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 913 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 914 #ifndef ATA_CAM 915 if (atadev->flags & ATA_D_USE_CHS) { 916 int heads, sectors; 917 918 if (atadev->param.atavalid & ATA_FLAG_54_58) { 919 heads = atadev->param.current_heads; 920 sectors = atadev->param.current_sectors; 921 } 922 else { 923 heads = atadev->param.heads; 924 sectors = atadev->param.sectors; 925 } 926 ATA_IDX_OUTB(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1); 927 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 928 (request->u.ata.lba / (sectors * heads))); 929 ATA_IDX_OUTB(ch, ATA_CYL_MSB, 930 (request->u.ata.lba / (sectors * heads)) >> 8); 931 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit) | 932 (((request->u.ata.lba% (sectors * heads)) / 933 sectors) & 0xf)); 934 } 935 else { 936 #endif 937 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 938 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 939 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 940 ATA_IDX_OUTB(ch, ATA_DRIVE, 941 ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) | 942 ((request->u.ata.lba >> 24) & 0x0f)); 943 #ifndef ATA_CAM 944 } 945 #endif 946 } 947 } 948 949 static void 950 ata_intel_31244_reset(device_t dev) 951 { 952 struct ata_channel *ch = device_get_softc(dev); 953 954 if (ata_sata_phy_reset(dev, -1, 1)) 955 ata_generic_reset(dev); 956 else 957 ch->devices = 0; 958 } 959 960 ATA_DECLARE_DRIVER(ata_intel); 961 MODULE_DEPEND(ata_intel, ata_ahci, 1, 1, 1); 962