1 /*- 2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/module.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/ata.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/malloc.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 #include <sys/sema.h> 41 #include <sys/taskqueue.h> 42 #include <vm/uma.h> 43 #include <machine/stdarg.h> 44 #include <machine/resource.h> 45 #include <machine/bus.h> 46 #include <sys/rman.h> 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcireg.h> 49 #include <dev/ata/ata-all.h> 50 #include <dev/ata/ata-pci.h> 51 #include <ata_if.h> 52 53 /* local prototypes */ 54 static int ata_intel_chipinit(device_t dev); 55 static int ata_intel_chipdeinit(device_t dev); 56 static int ata_intel_ch_attach(device_t dev); 57 static void ata_intel_reset(device_t dev); 58 static int ata_intel_old_setmode(device_t dev, int target, int mode); 59 static int ata_intel_new_setmode(device_t dev, int target, int mode); 60 static int ata_intel_sch_setmode(device_t dev, int target, int mode); 61 static int ata_intel_sata_getrev(device_t dev, int target); 62 static int ata_intel_sata_status(device_t dev); 63 static int ata_intel_sata_ahci_read(device_t dev, int port, 64 int reg, u_int32_t *result); 65 static int ata_intel_sata_cscr_read(device_t dev, int port, 66 int reg, u_int32_t *result); 67 static int ata_intel_sata_sidpr_read(device_t dev, int port, 68 int reg, u_int32_t *result); 69 static int ata_intel_sata_ahci_write(device_t dev, int port, 70 int reg, u_int32_t result); 71 static int ata_intel_sata_cscr_write(device_t dev, int port, 72 int reg, u_int32_t result); 73 static int ata_intel_sata_sidpr_write(device_t dev, int port, 74 int reg, u_int32_t result); 75 static int ata_intel_31244_ch_attach(device_t dev); 76 static int ata_intel_31244_ch_detach(device_t dev); 77 static int ata_intel_31244_status(device_t dev); 78 static void ata_intel_31244_tf_write(struct ata_request *request); 79 static void ata_intel_31244_reset(device_t dev); 80 81 /* misc defines */ 82 #define INTEL_AHCI 1 83 #define INTEL_ICH5 2 84 #define INTEL_6CH 4 85 #define INTEL_6CH2 8 86 #define INTEL_ICH7 16 87 88 struct ata_intel_data { 89 struct mtx lock; 90 u_char smap[4]; 91 }; 92 93 #define ATA_INTEL_SMAP(ctlr, ch) \ 94 &((struct ata_intel_data *)((ctlr)->chipset_data))->smap[(ch)->unit * 2] 95 #define ATA_INTEL_LOCK(ctlr) \ 96 mtx_lock(&((struct ata_intel_data *)((ctlr)->chipset_data))->lock) 97 #define ATA_INTEL_UNLOCK(ctlr) \ 98 mtx_unlock(&((struct ata_intel_data *)((ctlr)->chipset_data))->lock) 99 100 /* 101 * Intel chipset support functions 102 */ 103 static int 104 ata_intel_probe(device_t dev) 105 { 106 struct ata_pci_controller *ctlr = device_get_softc(dev); 107 static const struct ata_chip_id ids[] = 108 {{ ATA_I82371FB, 0, 0, 2, ATA_WDMA2, "PIIX" }, 109 { ATA_I82371SB, 0, 0, 2, ATA_WDMA2, "PIIX3" }, 110 { ATA_I82371AB, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 111 { ATA_I82443MX, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 112 { ATA_I82451NX, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 113 { ATA_I82801AB, 0, 0, 2, ATA_UDMA2, "ICH0" }, 114 { ATA_I82801AA, 0, 0, 2, ATA_UDMA4, "ICH" }, 115 { ATA_I82372FB, 0, 0, 2, ATA_UDMA4, "ICH" }, 116 { ATA_I82801BA, 0, 0, 2, ATA_UDMA5, "ICH2" }, 117 { ATA_I82801BA_1, 0, 0, 2, ATA_UDMA5, "ICH2" }, 118 { ATA_I82801CA, 0, 0, 2, ATA_UDMA5, "ICH3" }, 119 { ATA_I82801CA_1, 0, 0, 2, ATA_UDMA5, "ICH3" }, 120 { ATA_I82801DB, 0, 0, 2, ATA_UDMA5, "ICH4" }, 121 { ATA_I82801DB_1, 0, 0, 2, ATA_UDMA5, "ICH4" }, 122 { ATA_I82801EB, 0, 0, 2, ATA_UDMA5, "ICH5" }, 123 { ATA_I82801EB_S1, 0, INTEL_ICH5, 2, ATA_SA150, "ICH5" }, 124 { ATA_I82801EB_R1, 0, INTEL_ICH5, 2, ATA_SA150, "ICH5" }, 125 { ATA_I6300ESB, 0, 0, 2, ATA_UDMA5, "6300ESB" }, 126 { ATA_I6300ESB_S1, 0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" }, 127 { ATA_I6300ESB_R1, 0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" }, 128 { ATA_I82801FB, 0, 0, 2, ATA_UDMA5, "ICH6" }, 129 { ATA_I82801FB_S1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6" }, 130 { ATA_I82801FB_R1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6" }, 131 { ATA_I82801FBM, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6M" }, 132 { ATA_I82801GB, 0, 0, 1, ATA_UDMA5, "ICH7" }, 133 { ATA_I82801GB_S1, 0, INTEL_ICH7, 0, ATA_SA300, "ICH7" }, 134 { ATA_I82801GB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" }, 135 { ATA_I82801GB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" }, 136 { ATA_I82801GBM_S1, 0, INTEL_ICH7, 0, ATA_SA150, "ICH7M" }, 137 { ATA_I82801GBM_R1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" }, 138 { ATA_I82801GBM_AH, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" }, 139 { ATA_I63XXESB2, 0, 0, 1, ATA_UDMA5, "63XXESB2" }, 140 { ATA_I63XXESB2_S1, 0, 0, 0, ATA_SA300, "63XXESB2" }, 141 { ATA_I63XXESB2_S2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 142 { ATA_I63XXESB2_R1, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 143 { ATA_I63XXESB2_R2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 144 { ATA_I82801HB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH8" }, 145 { ATA_I82801HB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH8" }, 146 { ATA_I82801HB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 147 { ATA_I82801HB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 148 { ATA_I82801HB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 149 { ATA_I82801HBM, 0, 0, 1, ATA_UDMA5, "ICH8M" }, 150 { ATA_I82801HBM_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH8M" }, 151 { ATA_I82801HBM_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" }, 152 { ATA_I82801HBM_S3, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" }, 153 { ATA_I82801IB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH9" }, 154 { ATA_I82801IB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9" }, 155 { ATA_I82801IB_S3, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9" }, 156 { ATA_I82801IB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 157 { ATA_I82801IB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 158 { ATA_I82801IB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 159 { ATA_I82801IBM_S1, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9M" }, 160 { ATA_I82801IBM_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9M" }, 161 { ATA_I82801IBM_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9M" }, 162 { ATA_I82801IBM_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9M" }, 163 { ATA_I82801JIB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, 164 { ATA_I82801JIB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 165 { ATA_I82801JIB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 166 { ATA_I82801JIB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, 167 { ATA_I82801JD_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, 168 { ATA_I82801JD_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 169 { ATA_I82801JD_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 170 { ATA_I82801JD_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, 171 { ATA_I82801JI_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, 172 { ATA_I82801JI_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 173 { ATA_I82801JI_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 174 { ATA_I82801JI_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, 175 { ATA_5Series_S1, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 176 { ATA_5Series_S2, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 177 { ATA_5Series_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 178 { ATA_5Series_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 179 { ATA_5Series_R1, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 180 { ATA_5Series_S3, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 181 { ATA_5Series_S4, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 182 { ATA_5Series_AH3, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 183 { ATA_5Series_R2, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 184 { ATA_5Series_S5, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 185 { ATA_5Series_S6, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 186 { ATA_5Series_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 187 { ATA_CPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Cougar Point" }, 188 { ATA_CPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Cougar Point" }, 189 { ATA_CPT_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, 190 { ATA_CPT_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, 191 { ATA_CPT_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, 192 { ATA_CPT_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, 193 { ATA_CPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" }, 194 { ATA_CPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" }, 195 { ATA_PBG_S1, 0, INTEL_6CH, 0, ATA_SA300, "Patsburg" }, 196 { ATA_PBG_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" }, 197 { ATA_PBG_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" }, 198 { ATA_PBG_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" }, 199 { ATA_PBG_R3, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" }, 200 { ATA_PBG_S2, 0, INTEL_6CH2, 0, ATA_SA300, "Patsburg" }, 201 { ATA_PPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Panther Point" }, 202 { ATA_PPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Panther Point" }, 203 { ATA_PPT_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 204 { ATA_PPT_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 205 { ATA_PPT_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 206 { ATA_PPT_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 207 { ATA_PPT_R3, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 208 { ATA_PPT_R4, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 209 { ATA_PPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Panther Point" }, 210 { ATA_PPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Panther Point" }, 211 { ATA_PPT_R5, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 212 { ATA_PPT_R6, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 213 { ATA_LPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Lynx Point" }, 214 { ATA_LPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Lynx Point" }, 215 { ATA_LPT_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, 216 { ATA_LPT_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, 217 { ATA_LPT_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, 218 { ATA_LPT_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, 219 { ATA_LPT_R3, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, 220 { ATA_LPT_R4, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, 221 { ATA_LPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point" }, 222 { ATA_LPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point" }, 223 { ATA_LPT_R5, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, 224 { ATA_LPT_R6, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, 225 { ATA_I31244, 0, 0, 2, ATA_SA150, "31244" }, 226 { ATA_ISCH, 0, 0, 1, ATA_UDMA5, "SCH" }, 227 { ATA_DH89XXCC, 0, INTEL_AHCI, 0, ATA_SA300, "DH89xxCC" }, 228 { 0, 0, 0, 0, 0, 0}}; 229 230 if (pci_get_vendor(dev) != ATA_INTEL_ID) 231 return ENXIO; 232 233 if (!(ctlr->chip = ata_match_chip(dev, ids))) 234 return ENXIO; 235 236 ata_set_desc(dev); 237 ctlr->chipinit = ata_intel_chipinit; 238 ctlr->chipdeinit = ata_intel_chipdeinit; 239 return (BUS_PROBE_DEFAULT); 240 } 241 242 static int 243 ata_intel_chipinit(device_t dev) 244 { 245 struct ata_pci_controller *ctlr = device_get_softc(dev); 246 struct ata_intel_data *data; 247 248 if (ata_setup_interrupt(dev, ata_generic_intr)) 249 return ENXIO; 250 251 data = malloc(sizeof(struct ata_intel_data), M_ATAPCI, M_WAITOK | M_ZERO); 252 mtx_init(&data->lock, "Intel SATA lock", NULL, MTX_DEF); 253 ctlr->chipset_data = (void *)data; 254 255 /* good old PIIX needs special treatment (not implemented) */ 256 if (ctlr->chip->chipid == ATA_I82371FB) { 257 ctlr->setmode = ata_intel_old_setmode; 258 } 259 260 /* the intel 31244 needs special care if in DPA mode */ 261 else if (ctlr->chip->chipid == ATA_I31244) { 262 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) { 263 ctlr->r_type2 = SYS_RES_MEMORY; 264 ctlr->r_rid2 = PCIR_BAR(0); 265 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 266 &ctlr->r_rid2, 267 RF_ACTIVE))) 268 return ENXIO; 269 ctlr->channels = 4; 270 ctlr->ch_attach = ata_intel_31244_ch_attach; 271 ctlr->ch_detach = ata_intel_31244_ch_detach; 272 ctlr->reset = ata_intel_31244_reset; 273 } 274 ctlr->setmode = ata_sata_setmode; 275 ctlr->getrev = ata_sata_getrev; 276 } 277 /* SCH */ 278 else if (ctlr->chip->chipid == ATA_ISCH) { 279 ctlr->channels = 1; 280 ctlr->ch_attach = ata_intel_ch_attach; 281 ctlr->ch_detach = ata_pci_ch_detach; 282 ctlr->setmode = ata_intel_sch_setmode; 283 } 284 /* non SATA intel chips goes here */ 285 else if (ctlr->chip->max_dma < ATA_SA150) { 286 ctlr->channels = ctlr->chip->cfg2; 287 ctlr->ch_attach = ata_intel_ch_attach; 288 ctlr->ch_detach = ata_pci_ch_detach; 289 ctlr->setmode = ata_intel_new_setmode; 290 } 291 292 /* SATA parts can be either compat or AHCI */ 293 else { 294 /* force all ports active "the legacy way" */ 295 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f, 2); 296 297 ctlr->ch_attach = ata_intel_ch_attach; 298 ctlr->ch_detach = ata_pci_ch_detach; 299 ctlr->reset = ata_intel_reset; 300 301 /* 302 * if we have AHCI capability and AHCI or RAID mode enabled 303 * in BIOS we try for AHCI mode 304 */ 305 if ((ctlr->chip->cfg1 & INTEL_AHCI) && 306 (pci_read_config(dev, 0x90, 1) & 0xc0) && 307 (ata_ahci_chipinit(dev) != ENXIO)) 308 return 0; 309 310 /* BAR(5) may point to SATA interface registers */ 311 if ((ctlr->chip->cfg1 & INTEL_ICH7)) { 312 ctlr->r_type2 = SYS_RES_MEMORY; 313 ctlr->r_rid2 = PCIR_BAR(5); 314 ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 315 &ctlr->r_rid2, RF_ACTIVE); 316 if (ctlr->r_res2 != NULL) { 317 /* Set SCRAE bit to enable registers access. */ 318 pci_write_config(dev, 0x94, 319 pci_read_config(dev, 0x94, 4) | (1 << 9), 4); 320 /* Set Ports Implemented register bits. */ 321 ATA_OUTL(ctlr->r_res2, 0x0C, 322 ATA_INL(ctlr->r_res2, 0x0C) | 0xf); 323 } 324 /* Skip BAR(5) on ICH8M Apples, system locks up on access. */ 325 } else if (ctlr->chip->chipid != ATA_I82801HBM_S1 || 326 pci_get_subvendor(dev) != 0x106b) { 327 ctlr->r_type2 = SYS_RES_IOPORT; 328 ctlr->r_rid2 = PCIR_BAR(5); 329 ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 330 &ctlr->r_rid2, RF_ACTIVE); 331 } 332 if (ctlr->r_res2 != NULL || 333 (ctlr->chip->cfg1 & INTEL_ICH5)) 334 ctlr->getrev = ata_intel_sata_getrev; 335 ctlr->setmode = ata_sata_setmode; 336 } 337 return 0; 338 } 339 340 static int 341 ata_intel_chipdeinit(device_t dev) 342 { 343 struct ata_pci_controller *ctlr = device_get_softc(dev); 344 struct ata_intel_data *data; 345 346 data = ctlr->chipset_data; 347 mtx_destroy(&data->lock); 348 free(data, M_ATAPCI); 349 ctlr->chipset_data = NULL; 350 return (0); 351 } 352 353 static int 354 ata_intel_ch_attach(device_t dev) 355 { 356 struct ata_pci_controller *ctlr; 357 struct ata_channel *ch; 358 u_char *smap; 359 u_int map; 360 361 /* setup the usual register normal pci style */ 362 if (ata_pci_ch_attach(dev)) 363 return (ENXIO); 364 365 ctlr = device_get_softc(device_get_parent(dev)); 366 ch = device_get_softc(dev); 367 368 /* if r_res2 is valid it points to SATA interface registers */ 369 if (ctlr->r_res2) { 370 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 371 ch->r_io[ATA_IDX_ADDR].offset = 0x00; 372 ch->r_io[ATA_IDX_DATA].res = ctlr->r_res2; 373 ch->r_io[ATA_IDX_DATA].offset = 0x04; 374 } 375 376 ch->flags |= ATA_ALWAYS_DMASTAT; 377 if (ctlr->chip->max_dma >= ATA_SA150) { 378 smap = ATA_INTEL_SMAP(ctlr, ch); 379 map = pci_read_config(device_get_parent(dev), 0x90, 1); 380 if (ctlr->chip->cfg1 & INTEL_ICH5) { 381 map &= 0x07; 382 if ((map & 0x04) == 0) { 383 ch->flags |= ATA_SATA; 384 ch->flags |= ATA_NO_SLAVE; 385 smap[0] = (map & 0x01) ^ ch->unit; 386 smap[1] = 0; 387 } else if ((map & 0x02) == 0 && ch->unit == 0) { 388 ch->flags |= ATA_SATA; 389 smap[0] = (map & 0x01) ? 1 : 0; 390 smap[1] = (map & 0x01) ? 0 : 1; 391 } else if ((map & 0x02) != 0 && ch->unit == 1) { 392 ch->flags |= ATA_SATA; 393 smap[0] = (map & 0x01) ? 1 : 0; 394 smap[1] = (map & 0x01) ? 0 : 1; 395 } 396 } else if (ctlr->chip->cfg1 & INTEL_6CH2) { 397 ch->flags |= ATA_SATA; 398 ch->flags |= ATA_NO_SLAVE; 399 smap[0] = (ch->unit == 0) ? 0 : 1; 400 smap[1] = 0; 401 } else { 402 map &= 0x03; 403 if (map == 0x00) { 404 ch->flags |= ATA_SATA; 405 smap[0] = (ch->unit == 0) ? 0 : 1; 406 smap[1] = (ch->unit == 0) ? 2 : 3; 407 } else if (map == 0x02 && ch->unit == 0) { 408 ch->flags |= ATA_SATA; 409 smap[0] = 0; 410 smap[1] = 2; 411 } else if (map == 0x01 && ch->unit == 1) { 412 ch->flags |= ATA_SATA; 413 smap[0] = 1; 414 smap[1] = 3; 415 } 416 } 417 if (ch->flags & ATA_SATA) { 418 if ((ctlr->chip->cfg1 & INTEL_ICH5)) { 419 ch->flags |= ATA_PERIODIC_POLL; 420 ch->hw.status = ata_intel_sata_status; 421 ch->hw.pm_read = ata_intel_sata_cscr_read; 422 ch->hw.pm_write = ata_intel_sata_cscr_write; 423 } else if (ctlr->r_res2) { 424 ch->flags |= ATA_PERIODIC_POLL; 425 ch->hw.status = ata_intel_sata_status; 426 if ((ctlr->chip->cfg1 & INTEL_ICH7)) { 427 ch->hw.pm_read = ata_intel_sata_ahci_read; 428 ch->hw.pm_write = ata_intel_sata_ahci_write; 429 } else { 430 ch->hw.pm_read = ata_intel_sata_sidpr_read; 431 ch->hw.pm_write = ata_intel_sata_sidpr_write; 432 }; 433 } 434 if (ch->hw.pm_write != NULL) { 435 ata_sata_scr_write(ch, 0, 436 ATA_SERROR, 0xffffffff); 437 if ((ch->flags & ATA_NO_SLAVE) == 0) { 438 ata_sata_scr_write(ch, 1, 439 ATA_SERROR, 0xffffffff); 440 } 441 } 442 } else 443 ctlr->setmode = ata_intel_new_setmode; 444 } else if (ctlr->chip->chipid != ATA_ISCH) 445 ch->flags |= ATA_CHECKS_CABLE; 446 return (0); 447 } 448 449 static void 450 ata_intel_reset(device_t dev) 451 { 452 device_t parent = device_get_parent(dev); 453 struct ata_pci_controller *ctlr = device_get_softc(parent); 454 struct ata_channel *ch = device_get_softc(dev); 455 int mask, pshift, timeout, devs; 456 u_char *smap; 457 uint16_t pcs; 458 459 /* In combined mode, skip SATA stuff for PATA channel. */ 460 if ((ch->flags & ATA_SATA) == 0) 461 return (ata_generic_reset(dev)); 462 463 /* Do hard-reset on respective SATA ports. */ 464 smap = ATA_INTEL_SMAP(ctlr, ch); 465 mask = 1 << smap[0]; 466 if ((ch->flags & ATA_NO_SLAVE) == 0) 467 mask |= (1 << smap[1]); 468 pci_write_config(parent, 0x92, 469 pci_read_config(parent, 0x92, 2) & ~mask, 2); 470 DELAY(10); 471 pci_write_config(parent, 0x92, 472 pci_read_config(parent, 0x92, 2) | mask, 2); 473 474 /* Wait up to 1 sec for "connect well". */ 475 if (ctlr->chip->cfg1 & (INTEL_6CH | INTEL_6CH2)) 476 pshift = 8; 477 else 478 pshift = 4; 479 for (timeout = 0; timeout < 100 ; timeout++) { 480 pcs = (pci_read_config(parent, 0x92, 2) >> pshift) & mask; 481 if ((pcs == mask) && (ATA_IDX_INB(ch, ATA_STATUS) != 0xff)) 482 break; 483 ata_udelay(10000); 484 } 485 486 if (bootverbose) 487 device_printf(dev, "SATA reset: ports status=0x%02x\n", pcs); 488 /* If any device found, do soft-reset. */ 489 if (ch->hw.pm_read != NULL) { 490 devs = ata_sata_phy_reset(dev, 0, 2) ? ATA_ATA_MASTER : 0; 491 if ((ch->flags & ATA_NO_SLAVE) == 0) 492 devs |= ata_sata_phy_reset(dev, 1, 2) ? 493 ATA_ATA_SLAVE : 0; 494 } else { 495 devs = (pcs & (1 << smap[0])) ? ATA_ATA_MASTER : 0; 496 if ((ch->flags & ATA_NO_SLAVE) == 0) 497 devs |= (pcs & (1 << smap[1])) ? 498 ATA_ATA_SLAVE : 0; 499 } 500 if (devs) { 501 ata_generic_reset(dev); 502 /* Reset may give fake slave when only ATAPI master present. */ 503 ch->devices &= (devs | (devs * ATA_ATAPI_MASTER)); 504 } else 505 ch->devices = 0; 506 } 507 508 static int 509 ata_intel_old_setmode(device_t dev, int target, int mode) 510 { 511 device_t parent = device_get_parent(dev); 512 struct ata_pci_controller *ctlr = device_get_softc(parent); 513 514 mode = min(mode, ctlr->chip->max_dma); 515 return (mode); 516 } 517 518 static int 519 ata_intel_new_setmode(device_t dev, int target, int mode) 520 { 521 device_t parent = device_get_parent(dev); 522 struct ata_pci_controller *ctlr = device_get_softc(parent); 523 struct ata_channel *ch = device_get_softc(dev); 524 int devno = (ch->unit << 1) + target; 525 int piomode; 526 u_int32_t reg40 = pci_read_config(parent, 0x40, 4); 527 u_int8_t reg44 = pci_read_config(parent, 0x44, 1); 528 u_int8_t reg48 = pci_read_config(parent, 0x48, 1); 529 u_int16_t reg4a = pci_read_config(parent, 0x4a, 2); 530 u_int16_t reg54 = pci_read_config(parent, 0x54, 2); 531 u_int32_t mask40 = 0, new40 = 0; 532 u_int8_t mask44 = 0, new44 = 0; 533 static const uint8_t timings[] = 534 { 0x00, 0x00, 0x10, 0x21, 0x23, 0x00, 0x21, 0x23 }; 535 static const uint8_t utimings[] = 536 { 0x00, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02 }; 537 538 /* In combined mode, skip PATA stuff for SATA channel. */ 539 if (ch->flags & ATA_SATA) 540 return (ata_sata_setmode(dev, target, mode)); 541 542 mode = min(mode, ctlr->chip->max_dma); 543 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 544 !(reg54 & (0x10 << devno))) { 545 ata_print_cable(dev, "controller"); 546 mode = ATA_UDMA2; 547 } 548 /* Enable/disable UDMA and set timings. */ 549 if (mode >= ATA_UDMA0) { 550 pci_write_config(parent, 0x48, reg48 | (0x0001 << devno), 2); 551 pci_write_config(parent, 0x4a, 552 (reg4a & ~(0x3 << (devno << 2))) | 553 (utimings[mode & ATA_MODE_MASK] << (devno<<2)), 2); 554 piomode = ATA_PIO4; 555 } else { 556 pci_write_config(parent, 0x48, reg48 & ~(0x0001 << devno), 2); 557 pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (devno << 2))),2); 558 piomode = mode; 559 } 560 reg54 |= 0x0400; 561 /* Set UDMA reference clock (33/66/133MHz). */ 562 reg54 &= ~(0x1001 << devno); 563 if (mode >= ATA_UDMA5) 564 reg54 |= (0x1000 << devno); 565 else if (mode >= ATA_UDMA3) 566 reg54 |= (0x1 << devno); 567 pci_write_config(parent, 0x54, reg54, 2); 568 /* Allow PIO/WDMA timing controls. */ 569 reg40 &= ~0x00ff00ff; 570 reg40 |= 0x40774077; 571 /* Set PIO/WDMA timings. */ 572 if (target == 0) { 573 mask40 = 0x3300; 574 new40 = timings[ata_mode2idx(piomode)] << 8; 575 } else { 576 mask44 = 0x0f; 577 new44 = ((timings[ata_mode2idx(piomode)] & 0x30) >> 2) | 578 (timings[ata_mode2idx(piomode)] & 0x03); 579 } 580 if (ch->unit) { 581 mask40 <<= 16; 582 new40 <<= 16; 583 mask44 <<= 4; 584 new44 <<= 4; 585 } 586 pci_write_config(parent, 0x40, (reg40 & ~mask40) | new40, 4); 587 pci_write_config(parent, 0x44, (reg44 & ~mask44) | new44, 1); 588 return (mode); 589 } 590 591 static int 592 ata_intel_sch_setmode(device_t dev, int target, int mode) 593 { 594 device_t parent = device_get_parent(dev); 595 struct ata_pci_controller *ctlr = device_get_softc(parent); 596 u_int8_t dtim = 0x80 + (target << 2); 597 u_int32_t tim = pci_read_config(parent, dtim, 4); 598 int piomode; 599 600 mode = min(mode, ctlr->chip->max_dma); 601 if (mode >= ATA_UDMA0) { 602 tim |= (0x1 << 31); 603 tim &= ~(0x7 << 16); 604 tim |= ((mode & ATA_MODE_MASK) << 16); 605 piomode = ATA_PIO4; 606 } else if (mode >= ATA_WDMA0) { 607 tim &= ~(0x1 << 31); 608 tim &= ~(0x3 << 8); 609 tim |= ((mode & ATA_MODE_MASK) << 8); 610 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 : 611 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4; 612 } else 613 piomode = mode; 614 tim &= ~(0x7); 615 tim |= (piomode & 0x7); 616 pci_write_config(parent, dtim, tim, 4); 617 return (mode); 618 } 619 620 static int 621 ata_intel_sata_getrev(device_t dev, int target) 622 { 623 struct ata_channel *ch = device_get_softc(dev); 624 uint32_t status; 625 626 if (ata_sata_scr_read(ch, target, ATA_SSTATUS, &status) == 0) 627 return ((status & 0x0f0) >> 4); 628 return (0xff); 629 } 630 631 static int 632 ata_intel_sata_status(device_t dev) 633 { 634 struct ata_channel *ch = device_get_softc(dev); 635 636 ata_sata_phy_check_events(dev, 0); 637 if ((ch->flags & ATA_NO_SLAVE) == 0) 638 ata_sata_phy_check_events(dev, 1); 639 640 return ata_pci_status(dev); 641 } 642 643 static int 644 ata_intel_sata_ahci_read(device_t dev, int port, int reg, u_int32_t *result) 645 { 646 struct ata_pci_controller *ctlr; 647 struct ata_channel *ch; 648 device_t parent; 649 u_char *smap; 650 int offset; 651 652 parent = device_get_parent(dev); 653 ctlr = device_get_softc(parent); 654 ch = device_get_softc(dev); 655 port = (port == 1) ? 1 : 0; 656 smap = ATA_INTEL_SMAP(ctlr, ch); 657 offset = 0x100 + smap[port] * 0x80; 658 switch (reg) { 659 case ATA_SSTATUS: 660 reg = 0x28; 661 break; 662 case ATA_SCONTROL: 663 reg = 0x2c; 664 break; 665 case ATA_SERROR: 666 reg = 0x30; 667 break; 668 default: 669 return (EINVAL); 670 } 671 *result = ATA_INL(ctlr->r_res2, offset + reg); 672 return (0); 673 } 674 675 static int 676 ata_intel_sata_cscr_read(device_t dev, int port, int reg, u_int32_t *result) 677 { 678 struct ata_pci_controller *ctlr; 679 struct ata_channel *ch; 680 device_t parent; 681 u_char *smap; 682 683 parent = device_get_parent(dev); 684 ctlr = device_get_softc(parent); 685 ch = device_get_softc(dev); 686 smap = ATA_INTEL_SMAP(ctlr, ch); 687 port = (port == 1) ? 1 : 0; 688 switch (reg) { 689 case ATA_SSTATUS: 690 reg = 0; 691 break; 692 case ATA_SERROR: 693 reg = 1; 694 break; 695 case ATA_SCONTROL: 696 reg = 2; 697 break; 698 default: 699 return (EINVAL); 700 } 701 ATA_INTEL_LOCK(ctlr); 702 pci_write_config(parent, 0xa0, 703 0x50 + smap[port] * 0x10 + reg * 4, 4); 704 *result = pci_read_config(parent, 0xa4, 4); 705 ATA_INTEL_UNLOCK(ctlr); 706 return (0); 707 } 708 709 static int 710 ata_intel_sata_sidpr_read(device_t dev, int port, int reg, u_int32_t *result) 711 { 712 struct ata_pci_controller *ctlr; 713 struct ata_channel *ch; 714 device_t parent; 715 716 parent = device_get_parent(dev); 717 ctlr = device_get_softc(parent); 718 ch = device_get_softc(dev); 719 port = (port == 1) ? 1 : 0; 720 switch (reg) { 721 case ATA_SSTATUS: 722 reg = 0; 723 break; 724 case ATA_SCONTROL: 725 reg = 1; 726 break; 727 case ATA_SERROR: 728 reg = 2; 729 break; 730 default: 731 return (EINVAL); 732 } 733 ATA_INTEL_LOCK(ctlr); 734 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, ((ch->unit * 2 + port) << 8) + reg); 735 *result = ATA_IDX_INL(ch, ATA_IDX_DATA); 736 ATA_INTEL_UNLOCK(ctlr); 737 return (0); 738 } 739 740 static int 741 ata_intel_sata_ahci_write(device_t dev, int port, int reg, u_int32_t value) 742 { 743 struct ata_pci_controller *ctlr; 744 struct ata_channel *ch; 745 device_t parent; 746 u_char *smap; 747 int offset; 748 749 parent = device_get_parent(dev); 750 ctlr = device_get_softc(parent); 751 ch = device_get_softc(dev); 752 port = (port == 1) ? 1 : 0; 753 smap = ATA_INTEL_SMAP(ctlr, ch); 754 offset = 0x100 + smap[port] * 0x80; 755 switch (reg) { 756 case ATA_SSTATUS: 757 reg = 0x28; 758 break; 759 case ATA_SCONTROL: 760 reg = 0x2c; 761 break; 762 case ATA_SERROR: 763 reg = 0x30; 764 break; 765 default: 766 return (EINVAL); 767 } 768 ATA_OUTL(ctlr->r_res2, offset + reg, value); 769 return (0); 770 } 771 772 static int 773 ata_intel_sata_cscr_write(device_t dev, int port, int reg, u_int32_t value) 774 { 775 struct ata_pci_controller *ctlr; 776 struct ata_channel *ch; 777 device_t parent; 778 u_char *smap; 779 780 parent = device_get_parent(dev); 781 ctlr = device_get_softc(parent); 782 ch = device_get_softc(dev); 783 smap = ATA_INTEL_SMAP(ctlr, ch); 784 port = (port == 1) ? 1 : 0; 785 switch (reg) { 786 case ATA_SSTATUS: 787 reg = 0; 788 break; 789 case ATA_SERROR: 790 reg = 1; 791 break; 792 case ATA_SCONTROL: 793 reg = 2; 794 break; 795 default: 796 return (EINVAL); 797 } 798 ATA_INTEL_LOCK(ctlr); 799 pci_write_config(parent, 0xa0, 800 0x50 + smap[port] * 0x10 + reg * 4, 4); 801 pci_write_config(parent, 0xa4, value, 4); 802 ATA_INTEL_UNLOCK(ctlr); 803 return (0); 804 } 805 806 static int 807 ata_intel_sata_sidpr_write(device_t dev, int port, int reg, u_int32_t value) 808 { 809 struct ata_pci_controller *ctlr; 810 struct ata_channel *ch; 811 device_t parent; 812 813 parent = device_get_parent(dev); 814 ctlr = device_get_softc(parent); 815 ch = device_get_softc(dev); 816 port = (port == 1) ? 1 : 0; 817 switch (reg) { 818 case ATA_SSTATUS: 819 reg = 0; 820 break; 821 case ATA_SCONTROL: 822 reg = 1; 823 break; 824 case ATA_SERROR: 825 reg = 2; 826 break; 827 default: 828 return (EINVAL); 829 } 830 ATA_INTEL_LOCK(ctlr); 831 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, ((ch->unit * 2 + port) << 8) + reg); 832 ATA_IDX_OUTL(ch, ATA_IDX_DATA, value); 833 ATA_INTEL_UNLOCK(ctlr); 834 return (0); 835 } 836 837 static int 838 ata_intel_31244_ch_attach(device_t dev) 839 { 840 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 841 struct ata_channel *ch = device_get_softc(dev); 842 int i; 843 int ch_offset; 844 845 ata_pci_dmainit(dev); 846 847 ch_offset = 0x200 + ch->unit * 0x200; 848 849 for (i = ATA_DATA; i < ATA_MAX_RES; i++) 850 ch->r_io[i].res = ctlr->r_res2; 851 852 /* setup ATA registers */ 853 ch->r_io[ATA_DATA].offset = ch_offset + 0x00; 854 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06; 855 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08; 856 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c; 857 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; 858 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14; 859 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18; 860 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d; 861 ch->r_io[ATA_ERROR].offset = ch_offset + 0x04; 862 ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c; 863 ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28; 864 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29; 865 866 /* setup DMA registers */ 867 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100; 868 ch->r_io[ATA_SERROR].offset = ch_offset + 0x104; 869 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108; 870 871 /* setup SATA registers */ 872 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70; 873 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72; 874 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74; 875 876 ch->flags |= ATA_NO_SLAVE; 877 ch->flags |= ATA_SATA; 878 ata_pci_hw(dev); 879 ch->hw.status = ata_intel_31244_status; 880 ch->hw.tf_write = ata_intel_31244_tf_write; 881 882 /* enable PHY state change interrupt */ 883 ATA_OUTL(ctlr->r_res2, 0x4, 884 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3))); 885 return 0; 886 } 887 888 static int 889 ata_intel_31244_ch_detach(device_t dev) 890 { 891 892 ata_pci_dmafini(dev); 893 return (0); 894 } 895 896 static int 897 ata_intel_31244_status(device_t dev) 898 { 899 /* do we have any PHY events ? */ 900 ata_sata_phy_check_events(dev, -1); 901 902 /* any drive action to take care of ? */ 903 return ata_pci_status(dev); 904 } 905 906 static void 907 ata_intel_31244_tf_write(struct ata_request *request) 908 { 909 struct ata_channel *ch = device_get_softc(request->parent); 910 911 if (request->flags & ATA_R_48BIT) { 912 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature); 913 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count); 914 ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) | 915 (request->u.ata.lba & 0x00ff)); 916 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) | 917 ((request->u.ata.lba >> 8) & 0x00ff)); 918 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) | 919 ((request->u.ata.lba >> 16) & 0x00ff)); 920 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit)); 921 } 922 else { 923 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 924 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 925 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 926 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 927 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 928 ATA_IDX_OUTB(ch, ATA_DRIVE, 929 ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) | 930 ((request->u.ata.lba >> 24) & 0x0f)); 931 } 932 } 933 934 static void 935 ata_intel_31244_reset(device_t dev) 936 { 937 struct ata_channel *ch = device_get_softc(dev); 938 939 if (ata_sata_phy_reset(dev, -1, 1)) 940 ata_generic_reset(dev); 941 else 942 ch->devices = 0; 943 } 944 945 ATA_DECLARE_DRIVER(ata_intel); 946 MODULE_DEPEND(ata_intel, ata_ahci, 1, 1, 1); 947