1 /*- 2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ata.h" 31 #include <sys/param.h> 32 #include <sys/module.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/ata.h> 36 #include <sys/bus.h> 37 #include <sys/endian.h> 38 #include <sys/malloc.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/sema.h> 42 #include <sys/taskqueue.h> 43 #include <vm/uma.h> 44 #include <machine/stdarg.h> 45 #include <machine/resource.h> 46 #include <machine/bus.h> 47 #include <sys/rman.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/ata/ata-all.h> 51 #include <dev/ata/ata-pci.h> 52 #include <ata_if.h> 53 54 /* local prototypes */ 55 static int ata_intel_chipinit(device_t dev); 56 static int ata_intel_chipdeinit(device_t dev); 57 static int ata_intel_ch_attach(device_t dev); 58 static void ata_intel_reset(device_t dev); 59 static int ata_intel_old_setmode(device_t dev, int target, int mode); 60 static int ata_intel_new_setmode(device_t dev, int target, int mode); 61 static int ata_intel_sch_setmode(device_t dev, int target, int mode); 62 static int ata_intel_sata_getrev(device_t dev, int target); 63 static int ata_intel_sata_status(device_t dev); 64 static int ata_intel_sata_ahci_read(device_t dev, int port, 65 int reg, u_int32_t *result); 66 static int ata_intel_sata_cscr_read(device_t dev, int port, 67 int reg, u_int32_t *result); 68 static int ata_intel_sata_sidpr_read(device_t dev, int port, 69 int reg, u_int32_t *result); 70 static int ata_intel_sata_ahci_write(device_t dev, int port, 71 int reg, u_int32_t result); 72 static int ata_intel_sata_cscr_write(device_t dev, int port, 73 int reg, u_int32_t result); 74 static int ata_intel_sata_sidpr_write(device_t dev, int port, 75 int reg, u_int32_t result); 76 static int ata_intel_31244_ch_attach(device_t dev); 77 static int ata_intel_31244_ch_detach(device_t dev); 78 static int ata_intel_31244_status(device_t dev); 79 static void ata_intel_31244_tf_write(struct ata_request *request); 80 static void ata_intel_31244_reset(device_t dev); 81 82 /* misc defines */ 83 #define INTEL_AHCI 1 84 #define INTEL_ICH5 2 85 #define INTEL_6CH 4 86 #define INTEL_6CH2 8 87 #define INTEL_ICH7 16 88 89 struct ata_intel_data { 90 struct mtx lock; 91 u_char smap[4]; 92 }; 93 94 #define ATA_INTEL_SMAP(ctlr, ch) \ 95 &((struct ata_intel_data *)((ctlr)->chipset_data))->smap[(ch)->unit * 2] 96 #define ATA_INTEL_LOCK(ctlr) \ 97 mtx_lock(&((struct ata_intel_data *)((ctlr)->chipset_data))->lock) 98 #define ATA_INTEL_UNLOCK(ctlr) \ 99 mtx_unlock(&((struct ata_intel_data *)((ctlr)->chipset_data))->lock) 100 101 /* 102 * Intel chipset support functions 103 */ 104 static int 105 ata_intel_probe(device_t dev) 106 { 107 struct ata_pci_controller *ctlr = device_get_softc(dev); 108 static const struct ata_chip_id const ids[] = 109 {{ ATA_I82371FB, 0, 0, 2, ATA_WDMA2, "PIIX" }, 110 { ATA_I82371SB, 0, 0, 2, ATA_WDMA2, "PIIX3" }, 111 { ATA_I82371AB, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 112 { ATA_I82443MX, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 113 { ATA_I82451NX, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 114 { ATA_I82801AB, 0, 0, 2, ATA_UDMA2, "ICH0" }, 115 { ATA_I82801AA, 0, 0, 2, ATA_UDMA4, "ICH" }, 116 { ATA_I82372FB, 0, 0, 2, ATA_UDMA4, "ICH" }, 117 { ATA_I82801BA, 0, 0, 2, ATA_UDMA5, "ICH2" }, 118 { ATA_I82801BA_1, 0, 0, 2, ATA_UDMA5, "ICH2" }, 119 { ATA_I82801CA, 0, 0, 2, ATA_UDMA5, "ICH3" }, 120 { ATA_I82801CA_1, 0, 0, 2, ATA_UDMA5, "ICH3" }, 121 { ATA_I82801DB, 0, 0, 2, ATA_UDMA5, "ICH4" }, 122 { ATA_I82801DB_1, 0, 0, 2, ATA_UDMA5, "ICH4" }, 123 { ATA_I82801EB, 0, 0, 2, ATA_UDMA5, "ICH5" }, 124 { ATA_I82801EB_S1, 0, INTEL_ICH5, 2, ATA_SA150, "ICH5" }, 125 { ATA_I82801EB_R1, 0, INTEL_ICH5, 2, ATA_SA150, "ICH5" }, 126 { ATA_I6300ESB, 0, 0, 2, ATA_UDMA5, "6300ESB" }, 127 { ATA_I6300ESB_S1, 0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" }, 128 { ATA_I6300ESB_R1, 0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" }, 129 { ATA_I82801FB, 0, 0, 2, ATA_UDMA5, "ICH6" }, 130 { ATA_I82801FB_S1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6" }, 131 { ATA_I82801FB_R1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6" }, 132 { ATA_I82801FBM, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6M" }, 133 { ATA_I82801GB, 0, 0, 1, ATA_UDMA5, "ICH7" }, 134 { ATA_I82801GB_S1, 0, INTEL_ICH7, 0, ATA_SA300, "ICH7" }, 135 { ATA_I82801GB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" }, 136 { ATA_I82801GB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" }, 137 { ATA_I82801GBM_S1, 0, INTEL_ICH7, 0, ATA_SA150, "ICH7M" }, 138 { ATA_I82801GBM_R1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" }, 139 { ATA_I82801GBM_AH, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" }, 140 { ATA_I63XXESB2, 0, 0, 1, ATA_UDMA5, "63XXESB2" }, 141 { ATA_I63XXESB2_S1, 0, 0, 0, ATA_SA300, "63XXESB2" }, 142 { ATA_I63XXESB2_S2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 143 { ATA_I63XXESB2_R1, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 144 { ATA_I63XXESB2_R2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 145 { ATA_I82801HB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH8" }, 146 { ATA_I82801HB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH8" }, 147 { ATA_I82801HB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 148 { ATA_I82801HB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 149 { ATA_I82801HB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 150 { ATA_I82801HBM, 0, 0, 1, ATA_UDMA5, "ICH8M" }, 151 { ATA_I82801HBM_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH8M" }, 152 { ATA_I82801HBM_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" }, 153 { ATA_I82801HBM_S3, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" }, 154 { ATA_I82801IB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH9" }, 155 { ATA_I82801IB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9" }, 156 { ATA_I82801IB_S3, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9" }, 157 { ATA_I82801IB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 158 { ATA_I82801IB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 159 { ATA_I82801IB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 160 { ATA_I82801IBM_S1, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9M" }, 161 { ATA_I82801IBM_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9M" }, 162 { ATA_I82801IBM_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9M" }, 163 { ATA_I82801IBM_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9M" }, 164 { ATA_I82801JIB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, 165 { ATA_I82801JIB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 166 { ATA_I82801JIB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 167 { ATA_I82801JIB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, 168 { ATA_I82801JD_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, 169 { ATA_I82801JD_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 170 { ATA_I82801JD_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 171 { ATA_I82801JD_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, 172 { ATA_I82801JI_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, 173 { ATA_I82801JI_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 174 { ATA_I82801JI_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 175 { ATA_I82801JI_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, 176 { ATA_5Series_S1, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 177 { ATA_5Series_S2, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 178 { ATA_5Series_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 179 { ATA_5Series_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 180 { ATA_5Series_R1, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 181 { ATA_5Series_S3, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 182 { ATA_5Series_S4, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 183 { ATA_5Series_AH3, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 184 { ATA_5Series_R2, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 185 { ATA_5Series_S5, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 186 { ATA_5Series_S6, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 187 { ATA_5Series_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 188 { ATA_CPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Cougar Point" }, 189 { ATA_CPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Cougar Point" }, 190 { ATA_CPT_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, 191 { ATA_CPT_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, 192 { ATA_CPT_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, 193 { ATA_CPT_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, 194 { ATA_CPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" }, 195 { ATA_CPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" }, 196 { ATA_PBG_S1, 0, INTEL_6CH, 0, ATA_SA300, "Patsburg" }, 197 { ATA_PBG_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" }, 198 { ATA_PBG_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" }, 199 { ATA_PBG_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" }, 200 { ATA_PBG_R3, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" }, 201 { ATA_PBG_S2, 0, INTEL_6CH2, 0, ATA_SA300, "Patsburg" }, 202 { ATA_PPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Panther Point" }, 203 { ATA_PPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Panther Point" }, 204 { ATA_PPT_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 205 { ATA_PPT_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 206 { ATA_PPT_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 207 { ATA_PPT_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 208 { ATA_PPT_R3, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 209 { ATA_PPT_R4, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 210 { ATA_PPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Panther Point" }, 211 { ATA_PPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Panther Point" }, 212 { ATA_PPT_R5, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 213 { ATA_PPT_R6, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 214 { ATA_I31244, 0, 0, 2, ATA_SA150, "31244" }, 215 { ATA_ISCH, 0, 0, 1, ATA_UDMA5, "SCH" }, 216 { ATA_DH89XXCC, 0, INTEL_AHCI, 0, ATA_SA300, "DH89xxCC" }, 217 { 0, 0, 0, 0, 0, 0}}; 218 219 if (pci_get_vendor(dev) != ATA_INTEL_ID) 220 return ENXIO; 221 222 if (!(ctlr->chip = ata_match_chip(dev, ids))) 223 return ENXIO; 224 225 ata_set_desc(dev); 226 ctlr->chipinit = ata_intel_chipinit; 227 ctlr->chipdeinit = ata_intel_chipdeinit; 228 return (BUS_PROBE_DEFAULT); 229 } 230 231 static int 232 ata_intel_chipinit(device_t dev) 233 { 234 struct ata_pci_controller *ctlr = device_get_softc(dev); 235 struct ata_intel_data *data; 236 237 if (ata_setup_interrupt(dev, ata_generic_intr)) 238 return ENXIO; 239 240 data = malloc(sizeof(struct ata_intel_data), M_ATAPCI, M_WAITOK | M_ZERO); 241 mtx_init(&data->lock, "Intel SATA lock", NULL, MTX_DEF); 242 ctlr->chipset_data = (void *)data; 243 244 /* good old PIIX needs special treatment (not implemented) */ 245 if (ctlr->chip->chipid == ATA_I82371FB) { 246 ctlr->setmode = ata_intel_old_setmode; 247 } 248 249 /* the intel 31244 needs special care if in DPA mode */ 250 else if (ctlr->chip->chipid == ATA_I31244) { 251 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) { 252 ctlr->r_type2 = SYS_RES_MEMORY; 253 ctlr->r_rid2 = PCIR_BAR(0); 254 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 255 &ctlr->r_rid2, 256 RF_ACTIVE))) 257 return ENXIO; 258 ctlr->channels = 4; 259 ctlr->ch_attach = ata_intel_31244_ch_attach; 260 ctlr->ch_detach = ata_intel_31244_ch_detach; 261 ctlr->reset = ata_intel_31244_reset; 262 } 263 ctlr->setmode = ata_sata_setmode; 264 ctlr->getrev = ata_sata_getrev; 265 } 266 /* SCH */ 267 else if (ctlr->chip->chipid == ATA_ISCH) { 268 ctlr->channels = 1; 269 ctlr->ch_attach = ata_intel_ch_attach; 270 ctlr->ch_detach = ata_pci_ch_detach; 271 ctlr->setmode = ata_intel_sch_setmode; 272 } 273 /* non SATA intel chips goes here */ 274 else if (ctlr->chip->max_dma < ATA_SA150) { 275 ctlr->channels = ctlr->chip->cfg2; 276 ctlr->ch_attach = ata_intel_ch_attach; 277 ctlr->ch_detach = ata_pci_ch_detach; 278 ctlr->setmode = ata_intel_new_setmode; 279 } 280 281 /* SATA parts can be either compat or AHCI */ 282 else { 283 /* force all ports active "the legacy way" */ 284 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f, 2); 285 286 ctlr->ch_attach = ata_intel_ch_attach; 287 ctlr->ch_detach = ata_pci_ch_detach; 288 ctlr->reset = ata_intel_reset; 289 290 /* 291 * if we have AHCI capability and AHCI or RAID mode enabled 292 * in BIOS we try for AHCI mode 293 */ 294 if ((ctlr->chip->cfg1 & INTEL_AHCI) && 295 (pci_read_config(dev, 0x90, 1) & 0xc0) && 296 (ata_ahci_chipinit(dev) != ENXIO)) 297 return 0; 298 299 /* BAR(5) may point to SATA interface registers */ 300 if ((ctlr->chip->cfg1 & INTEL_ICH7)) { 301 ctlr->r_type2 = SYS_RES_MEMORY; 302 ctlr->r_rid2 = PCIR_BAR(5); 303 ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 304 &ctlr->r_rid2, RF_ACTIVE); 305 if (ctlr->r_res2 != NULL) { 306 /* Set SCRAE bit to enable registers access. */ 307 pci_write_config(dev, 0x94, 308 pci_read_config(dev, 0x94, 4) | (1 << 9), 4); 309 /* Set Ports Implemented register bits. */ 310 ATA_OUTL(ctlr->r_res2, 0x0C, 311 ATA_INL(ctlr->r_res2, 0x0C) | 0xf); 312 } 313 /* Skip BAR(5) on ICH8M Apples, system locks up on access. */ 314 } else if (ctlr->chip->chipid != ATA_I82801HBM_S1 || 315 pci_get_subvendor(dev) != 0x106b) { 316 ctlr->r_type2 = SYS_RES_IOPORT; 317 ctlr->r_rid2 = PCIR_BAR(5); 318 ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 319 &ctlr->r_rid2, RF_ACTIVE); 320 } 321 if (ctlr->r_res2 != NULL || 322 (ctlr->chip->cfg1 & INTEL_ICH5)) 323 ctlr->getrev = ata_intel_sata_getrev; 324 ctlr->setmode = ata_sata_setmode; 325 } 326 return 0; 327 } 328 329 static int 330 ata_intel_chipdeinit(device_t dev) 331 { 332 struct ata_pci_controller *ctlr = device_get_softc(dev); 333 struct ata_intel_data *data; 334 335 data = ctlr->chipset_data; 336 mtx_destroy(&data->lock); 337 free(data, M_ATAPCI); 338 ctlr->chipset_data = NULL; 339 return (0); 340 } 341 342 static int 343 ata_intel_ch_attach(device_t dev) 344 { 345 struct ata_pci_controller *ctlr; 346 struct ata_channel *ch; 347 u_char *smap; 348 u_int map; 349 350 /* setup the usual register normal pci style */ 351 if (ata_pci_ch_attach(dev)) 352 return (ENXIO); 353 354 ctlr = device_get_softc(device_get_parent(dev)); 355 ch = device_get_softc(dev); 356 357 /* if r_res2 is valid it points to SATA interface registers */ 358 if (ctlr->r_res2) { 359 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 360 ch->r_io[ATA_IDX_ADDR].offset = 0x00; 361 ch->r_io[ATA_IDX_DATA].res = ctlr->r_res2; 362 ch->r_io[ATA_IDX_DATA].offset = 0x04; 363 } 364 365 ch->flags |= ATA_ALWAYS_DMASTAT; 366 if (ctlr->chip->max_dma >= ATA_SA150) { 367 smap = ATA_INTEL_SMAP(ctlr, ch); 368 map = pci_read_config(device_get_parent(dev), 0x90, 1); 369 if (ctlr->chip->cfg1 & INTEL_ICH5) { 370 map &= 0x07; 371 if ((map & 0x04) == 0) { 372 ch->flags |= ATA_SATA; 373 ch->flags |= ATA_NO_SLAVE; 374 smap[0] = (map & 0x01) ^ ch->unit; 375 smap[1] = 0; 376 } else if ((map & 0x02) == 0 && ch->unit == 0) { 377 ch->flags |= ATA_SATA; 378 smap[0] = (map & 0x01) ? 1 : 0; 379 smap[1] = (map & 0x01) ? 0 : 1; 380 } else if ((map & 0x02) != 0 && ch->unit == 1) { 381 ch->flags |= ATA_SATA; 382 smap[0] = (map & 0x01) ? 1 : 0; 383 smap[1] = (map & 0x01) ? 0 : 1; 384 } 385 } else if (ctlr->chip->cfg1 & INTEL_6CH2) { 386 ch->flags |= ATA_SATA; 387 ch->flags |= ATA_NO_SLAVE; 388 smap[0] = (ch->unit == 0) ? 0 : 1; 389 smap[1] = 0; 390 } else { 391 map &= 0x03; 392 if (map == 0x00) { 393 ch->flags |= ATA_SATA; 394 smap[0] = (ch->unit == 0) ? 0 : 1; 395 smap[1] = (ch->unit == 0) ? 2 : 3; 396 } else if (map == 0x02 && ch->unit == 0) { 397 ch->flags |= ATA_SATA; 398 smap[0] = 0; 399 smap[1] = 2; 400 } else if (map == 0x01 && ch->unit == 1) { 401 ch->flags |= ATA_SATA; 402 smap[0] = 1; 403 smap[1] = 3; 404 } 405 } 406 if (ch->flags & ATA_SATA) { 407 if ((ctlr->chip->cfg1 & INTEL_ICH5)) { 408 ch->flags |= ATA_PERIODIC_POLL; 409 ch->hw.status = ata_intel_sata_status; 410 ch->hw.pm_read = ata_intel_sata_cscr_read; 411 ch->hw.pm_write = ata_intel_sata_cscr_write; 412 } else if (ctlr->r_res2) { 413 ch->flags |= ATA_PERIODIC_POLL; 414 ch->hw.status = ata_intel_sata_status; 415 if ((ctlr->chip->cfg1 & INTEL_ICH7)) { 416 ch->hw.pm_read = ata_intel_sata_ahci_read; 417 ch->hw.pm_write = ata_intel_sata_ahci_write; 418 } else { 419 ch->hw.pm_read = ata_intel_sata_sidpr_read; 420 ch->hw.pm_write = ata_intel_sata_sidpr_write; 421 }; 422 } 423 if (ch->hw.pm_write != NULL) { 424 ata_sata_scr_write(ch, 0, 425 ATA_SERROR, 0xffffffff); 426 if ((ch->flags & ATA_NO_SLAVE) == 0) { 427 ata_sata_scr_write(ch, 1, 428 ATA_SERROR, 0xffffffff); 429 } 430 } 431 } else 432 ctlr->setmode = ata_intel_new_setmode; 433 } else if (ctlr->chip->chipid != ATA_ISCH) 434 ch->flags |= ATA_CHECKS_CABLE; 435 return (0); 436 } 437 438 static void 439 ata_intel_reset(device_t dev) 440 { 441 device_t parent = device_get_parent(dev); 442 struct ata_pci_controller *ctlr = device_get_softc(parent); 443 struct ata_channel *ch = device_get_softc(dev); 444 int mask, pshift, timeout, devs; 445 u_char *smap; 446 uint16_t pcs; 447 448 /* In combined mode, skip SATA stuff for PATA channel. */ 449 if ((ch->flags & ATA_SATA) == 0) 450 return (ata_generic_reset(dev)); 451 452 /* Do hard-reset on respective SATA ports. */ 453 smap = ATA_INTEL_SMAP(ctlr, ch); 454 mask = 1 << smap[0]; 455 if ((ch->flags & ATA_NO_SLAVE) == 0) 456 mask |= (1 << smap[1]); 457 pci_write_config(parent, 0x92, 458 pci_read_config(parent, 0x92, 2) & ~mask, 2); 459 DELAY(10); 460 pci_write_config(parent, 0x92, 461 pci_read_config(parent, 0x92, 2) | mask, 2); 462 463 /* Wait up to 1 sec for "connect well". */ 464 if (ctlr->chip->cfg1 & (INTEL_6CH | INTEL_6CH2)) 465 pshift = 8; 466 else 467 pshift = 4; 468 for (timeout = 0; timeout < 100 ; timeout++) { 469 pcs = (pci_read_config(parent, 0x92, 2) >> pshift) & mask; 470 if ((pcs == mask) && (ATA_IDX_INB(ch, ATA_STATUS) != 0xff)) 471 break; 472 ata_udelay(10000); 473 } 474 475 if (bootverbose) 476 device_printf(dev, "SATA reset: ports status=0x%02x\n", pcs); 477 /* If any device found, do soft-reset. */ 478 if (ch->hw.pm_read != NULL) { 479 devs = ata_sata_phy_reset(dev, 0, 2) ? ATA_ATA_MASTER : 0; 480 if ((ch->flags & ATA_NO_SLAVE) == 0) 481 devs |= ata_sata_phy_reset(dev, 1, 2) ? 482 ATA_ATA_SLAVE : 0; 483 } else { 484 devs = (pcs & (1 << smap[0])) ? ATA_ATA_MASTER : 0; 485 if ((ch->flags & ATA_NO_SLAVE) == 0) 486 devs |= (pcs & (1 << smap[1])) ? 487 ATA_ATA_SLAVE : 0; 488 } 489 if (devs) { 490 ata_generic_reset(dev); 491 /* Reset may give fake slave when only ATAPI master present. */ 492 ch->devices &= (devs | (devs * ATA_ATAPI_MASTER)); 493 } else 494 ch->devices = 0; 495 } 496 497 static int 498 ata_intel_old_setmode(device_t dev, int target, int mode) 499 { 500 device_t parent = device_get_parent(dev); 501 struct ata_pci_controller *ctlr = device_get_softc(parent); 502 503 mode = min(mode, ctlr->chip->max_dma); 504 return (mode); 505 } 506 507 static int 508 ata_intel_new_setmode(device_t dev, int target, int mode) 509 { 510 device_t parent = device_get_parent(dev); 511 struct ata_pci_controller *ctlr = device_get_softc(parent); 512 struct ata_channel *ch = device_get_softc(dev); 513 int devno = (ch->unit << 1) + target; 514 int piomode; 515 u_int32_t reg40 = pci_read_config(parent, 0x40, 4); 516 u_int8_t reg44 = pci_read_config(parent, 0x44, 1); 517 u_int8_t reg48 = pci_read_config(parent, 0x48, 1); 518 u_int16_t reg4a = pci_read_config(parent, 0x4a, 2); 519 u_int16_t reg54 = pci_read_config(parent, 0x54, 2); 520 u_int32_t mask40 = 0, new40 = 0; 521 u_int8_t mask44 = 0, new44 = 0; 522 static const uint8_t timings[] = 523 { 0x00, 0x00, 0x10, 0x21, 0x23, 0x00, 0x21, 0x23 }; 524 static const uint8_t utimings[] = 525 { 0x00, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02 }; 526 527 /* In combined mode, skip PATA stuff for SATA channel. */ 528 if (ch->flags & ATA_SATA) 529 return (ata_sata_setmode(dev, target, mode)); 530 531 mode = min(mode, ctlr->chip->max_dma); 532 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 533 !(reg54 & (0x10 << devno))) { 534 ata_print_cable(dev, "controller"); 535 mode = ATA_UDMA2; 536 } 537 /* Enable/disable UDMA and set timings. */ 538 if (mode >= ATA_UDMA0) { 539 pci_write_config(parent, 0x48, reg48 | (0x0001 << devno), 2); 540 pci_write_config(parent, 0x4a, 541 (reg4a & ~(0x3 << (devno << 2))) | 542 (utimings[mode & ATA_MODE_MASK] << (devno<<2)), 2); 543 piomode = ATA_PIO4; 544 } else { 545 pci_write_config(parent, 0x48, reg48 & ~(0x0001 << devno), 2); 546 pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (devno << 2))),2); 547 piomode = mode; 548 } 549 reg54 |= 0x0400; 550 /* Set UDMA reference clock (33/66/133MHz). */ 551 reg54 &= ~(0x1001 << devno); 552 if (mode >= ATA_UDMA5) 553 reg54 |= (0x1000 << devno); 554 else if (mode >= ATA_UDMA3) 555 reg54 |= (0x1 << devno); 556 pci_write_config(parent, 0x54, reg54, 2); 557 /* Allow PIO/WDMA timing controls. */ 558 reg40 &= ~0x00ff00ff; 559 reg40 |= 0x40774077; 560 /* Set PIO/WDMA timings. */ 561 if (target == 0) { 562 mask40 = 0x3300; 563 new40 = timings[ata_mode2idx(piomode)] << 8; 564 } else { 565 mask44 = 0x0f; 566 new44 = ((timings[ata_mode2idx(piomode)] & 0x30) >> 2) | 567 (timings[ata_mode2idx(piomode)] & 0x03); 568 } 569 if (ch->unit) { 570 mask40 <<= 16; 571 new40 <<= 16; 572 mask44 <<= 4; 573 new44 <<= 4; 574 } 575 pci_write_config(parent, 0x40, (reg40 & ~mask40) | new40, 4); 576 pci_write_config(parent, 0x44, (reg44 & ~mask44) | new44, 1); 577 return (mode); 578 } 579 580 static int 581 ata_intel_sch_setmode(device_t dev, int target, int mode) 582 { 583 device_t parent = device_get_parent(dev); 584 struct ata_pci_controller *ctlr = device_get_softc(parent); 585 u_int8_t dtim = 0x80 + (target << 2); 586 u_int32_t tim = pci_read_config(parent, dtim, 4); 587 int piomode; 588 589 mode = min(mode, ctlr->chip->max_dma); 590 if (mode >= ATA_UDMA0) { 591 tim |= (0x1 << 31); 592 tim &= ~(0x7 << 16); 593 tim |= ((mode & ATA_MODE_MASK) << 16); 594 piomode = ATA_PIO4; 595 } else if (mode >= ATA_WDMA0) { 596 tim &= ~(0x1 << 31); 597 tim &= ~(0x3 << 8); 598 tim |= ((mode & ATA_MODE_MASK) << 8); 599 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 : 600 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4; 601 } else 602 piomode = mode; 603 tim &= ~(0x7); 604 tim |= (piomode & 0x7); 605 pci_write_config(parent, dtim, tim, 4); 606 return (mode); 607 } 608 609 static int 610 ata_intel_sata_getrev(device_t dev, int target) 611 { 612 struct ata_channel *ch = device_get_softc(dev); 613 uint32_t status; 614 615 if (ata_sata_scr_read(ch, target, ATA_SSTATUS, &status) == 0) 616 return ((status & 0x0f0) >> 4); 617 return (0xff); 618 } 619 620 static int 621 ata_intel_sata_status(device_t dev) 622 { 623 struct ata_channel *ch = device_get_softc(dev); 624 625 ata_sata_phy_check_events(dev, 0); 626 if ((ch->flags & ATA_NO_SLAVE) == 0) 627 ata_sata_phy_check_events(dev, 1); 628 629 return ata_pci_status(dev); 630 } 631 632 static int 633 ata_intel_sata_ahci_read(device_t dev, int port, int reg, u_int32_t *result) 634 { 635 struct ata_pci_controller *ctlr; 636 struct ata_channel *ch; 637 device_t parent; 638 u_char *smap; 639 int offset; 640 641 parent = device_get_parent(dev); 642 ctlr = device_get_softc(parent); 643 ch = device_get_softc(dev); 644 port = (port == 1) ? 1 : 0; 645 smap = ATA_INTEL_SMAP(ctlr, ch); 646 offset = 0x100 + smap[port] * 0x80; 647 switch (reg) { 648 case ATA_SSTATUS: 649 reg = 0x28; 650 break; 651 case ATA_SCONTROL: 652 reg = 0x2c; 653 break; 654 case ATA_SERROR: 655 reg = 0x30; 656 break; 657 default: 658 return (EINVAL); 659 } 660 *result = ATA_INL(ctlr->r_res2, offset + reg); 661 return (0); 662 } 663 664 static int 665 ata_intel_sata_cscr_read(device_t dev, int port, int reg, u_int32_t *result) 666 { 667 struct ata_pci_controller *ctlr; 668 struct ata_channel *ch; 669 device_t parent; 670 u_char *smap; 671 672 parent = device_get_parent(dev); 673 ctlr = device_get_softc(parent); 674 ch = device_get_softc(dev); 675 smap = ATA_INTEL_SMAP(ctlr, ch); 676 port = (port == 1) ? 1 : 0; 677 switch (reg) { 678 case ATA_SSTATUS: 679 reg = 0; 680 break; 681 case ATA_SERROR: 682 reg = 1; 683 break; 684 case ATA_SCONTROL: 685 reg = 2; 686 break; 687 default: 688 return (EINVAL); 689 } 690 ATA_INTEL_LOCK(ctlr); 691 pci_write_config(parent, 0xa0, 692 0x50 + smap[port] * 0x10 + reg * 4, 4); 693 *result = pci_read_config(parent, 0xa4, 4); 694 ATA_INTEL_UNLOCK(ctlr); 695 return (0); 696 } 697 698 static int 699 ata_intel_sata_sidpr_read(device_t dev, int port, int reg, u_int32_t *result) 700 { 701 struct ata_pci_controller *ctlr; 702 struct ata_channel *ch; 703 device_t parent; 704 705 parent = device_get_parent(dev); 706 ctlr = device_get_softc(parent); 707 ch = device_get_softc(dev); 708 port = (port == 1) ? 1 : 0; 709 switch (reg) { 710 case ATA_SSTATUS: 711 reg = 0; 712 break; 713 case ATA_SCONTROL: 714 reg = 1; 715 break; 716 case ATA_SERROR: 717 reg = 2; 718 break; 719 default: 720 return (EINVAL); 721 } 722 ATA_INTEL_LOCK(ctlr); 723 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, ((ch->unit * 2 + port) << 8) + reg); 724 *result = ATA_IDX_INL(ch, ATA_IDX_DATA); 725 ATA_INTEL_UNLOCK(ctlr); 726 return (0); 727 } 728 729 static int 730 ata_intel_sata_ahci_write(device_t dev, int port, int reg, u_int32_t value) 731 { 732 struct ata_pci_controller *ctlr; 733 struct ata_channel *ch; 734 device_t parent; 735 u_char *smap; 736 int offset; 737 738 parent = device_get_parent(dev); 739 ctlr = device_get_softc(parent); 740 ch = device_get_softc(dev); 741 port = (port == 1) ? 1 : 0; 742 smap = ATA_INTEL_SMAP(ctlr, ch); 743 offset = 0x100 + smap[port] * 0x80; 744 switch (reg) { 745 case ATA_SSTATUS: 746 reg = 0x28; 747 break; 748 case ATA_SCONTROL: 749 reg = 0x2c; 750 break; 751 case ATA_SERROR: 752 reg = 0x30; 753 break; 754 default: 755 return (EINVAL); 756 } 757 ATA_OUTL(ctlr->r_res2, offset + reg, value); 758 return (0); 759 } 760 761 static int 762 ata_intel_sata_cscr_write(device_t dev, int port, int reg, u_int32_t value) 763 { 764 struct ata_pci_controller *ctlr; 765 struct ata_channel *ch; 766 device_t parent; 767 u_char *smap; 768 769 parent = device_get_parent(dev); 770 ctlr = device_get_softc(parent); 771 ch = device_get_softc(dev); 772 smap = ATA_INTEL_SMAP(ctlr, ch); 773 port = (port == 1) ? 1 : 0; 774 switch (reg) { 775 case ATA_SSTATUS: 776 reg = 0; 777 break; 778 case ATA_SERROR: 779 reg = 1; 780 break; 781 case ATA_SCONTROL: 782 reg = 2; 783 break; 784 default: 785 return (EINVAL); 786 } 787 ATA_INTEL_LOCK(ctlr); 788 pci_write_config(parent, 0xa0, 789 0x50 + smap[port] * 0x10 + reg * 4, 4); 790 pci_write_config(parent, 0xa4, value, 4); 791 ATA_INTEL_UNLOCK(ctlr); 792 return (0); 793 } 794 795 static int 796 ata_intel_sata_sidpr_write(device_t dev, int port, int reg, u_int32_t value) 797 { 798 struct ata_pci_controller *ctlr; 799 struct ata_channel *ch; 800 device_t parent; 801 802 parent = device_get_parent(dev); 803 ctlr = device_get_softc(parent); 804 ch = device_get_softc(dev); 805 port = (port == 1) ? 1 : 0; 806 switch (reg) { 807 case ATA_SSTATUS: 808 reg = 0; 809 break; 810 case ATA_SCONTROL: 811 reg = 1; 812 break; 813 case ATA_SERROR: 814 reg = 2; 815 break; 816 default: 817 return (EINVAL); 818 } 819 ATA_INTEL_LOCK(ctlr); 820 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, ((ch->unit * 2 + port) << 8) + reg); 821 ATA_IDX_OUTL(ch, ATA_IDX_DATA, value); 822 ATA_INTEL_UNLOCK(ctlr); 823 return (0); 824 } 825 826 static int 827 ata_intel_31244_ch_attach(device_t dev) 828 { 829 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 830 struct ata_channel *ch = device_get_softc(dev); 831 int i; 832 int ch_offset; 833 834 ata_pci_dmainit(dev); 835 836 ch_offset = 0x200 + ch->unit * 0x200; 837 838 for (i = ATA_DATA; i < ATA_MAX_RES; i++) 839 ch->r_io[i].res = ctlr->r_res2; 840 841 /* setup ATA registers */ 842 ch->r_io[ATA_DATA].offset = ch_offset + 0x00; 843 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06; 844 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08; 845 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c; 846 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; 847 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14; 848 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18; 849 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d; 850 ch->r_io[ATA_ERROR].offset = ch_offset + 0x04; 851 ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c; 852 ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28; 853 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29; 854 855 /* setup DMA registers */ 856 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100; 857 ch->r_io[ATA_SERROR].offset = ch_offset + 0x104; 858 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108; 859 860 /* setup SATA registers */ 861 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70; 862 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72; 863 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74; 864 865 ch->flags |= ATA_NO_SLAVE; 866 ch->flags |= ATA_SATA; 867 ata_pci_hw(dev); 868 ch->hw.status = ata_intel_31244_status; 869 ch->hw.tf_write = ata_intel_31244_tf_write; 870 871 /* enable PHY state change interrupt */ 872 ATA_OUTL(ctlr->r_res2, 0x4, 873 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3))); 874 return 0; 875 } 876 877 static int 878 ata_intel_31244_ch_detach(device_t dev) 879 { 880 881 ata_pci_dmafini(dev); 882 return (0); 883 } 884 885 static int 886 ata_intel_31244_status(device_t dev) 887 { 888 /* do we have any PHY events ? */ 889 ata_sata_phy_check_events(dev, -1); 890 891 /* any drive action to take care of ? */ 892 return ata_pci_status(dev); 893 } 894 895 static void 896 ata_intel_31244_tf_write(struct ata_request *request) 897 { 898 struct ata_channel *ch = device_get_softc(request->parent); 899 #ifndef ATA_CAM 900 struct ata_device *atadev = device_get_softc(request->dev); 901 #endif 902 903 if (request->flags & ATA_R_48BIT) { 904 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature); 905 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count); 906 ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) | 907 (request->u.ata.lba & 0x00ff)); 908 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) | 909 ((request->u.ata.lba >> 8) & 0x00ff)); 910 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) | 911 ((request->u.ata.lba >> 16) & 0x00ff)); 912 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit)); 913 } 914 else { 915 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 916 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 917 #ifndef ATA_CAM 918 if (atadev->flags & ATA_D_USE_CHS) { 919 int heads, sectors; 920 921 if (atadev->param.atavalid & ATA_FLAG_54_58) { 922 heads = atadev->param.current_heads; 923 sectors = atadev->param.current_sectors; 924 } 925 else { 926 heads = atadev->param.heads; 927 sectors = atadev->param.sectors; 928 } 929 ATA_IDX_OUTB(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1); 930 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 931 (request->u.ata.lba / (sectors * heads))); 932 ATA_IDX_OUTB(ch, ATA_CYL_MSB, 933 (request->u.ata.lba / (sectors * heads)) >> 8); 934 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit) | 935 (((request->u.ata.lba% (sectors * heads)) / 936 sectors) & 0xf)); 937 } 938 else { 939 #endif 940 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 941 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 942 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 943 ATA_IDX_OUTB(ch, ATA_DRIVE, 944 ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) | 945 ((request->u.ata.lba >> 24) & 0x0f)); 946 #ifndef ATA_CAM 947 } 948 #endif 949 } 950 } 951 952 static void 953 ata_intel_31244_reset(device_t dev) 954 { 955 struct ata_channel *ch = device_get_softc(dev); 956 957 if (ata_sata_phy_reset(dev, -1, 1)) 958 ata_generic_reset(dev); 959 else 960 ch->devices = 0; 961 } 962 963 ATA_DECLARE_DRIVER(ata_intel); 964 MODULE_DEPEND(ata_intel, ata_ahci, 1, 1, 1); 965