1 /*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ata.h" 31 #include <sys/param.h> 32 #include <sys/module.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/ata.h> 36 #include <sys/bus.h> 37 #include <sys/endian.h> 38 #include <sys/malloc.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/sema.h> 42 #include <sys/taskqueue.h> 43 #include <vm/uma.h> 44 #include <machine/stdarg.h> 45 #include <machine/resource.h> 46 #include <machine/bus.h> 47 #include <sys/rman.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/ata/ata-all.h> 51 #include <dev/ata/ata-pci.h> 52 #include <ata_if.h> 53 54 /* local prototypes */ 55 static int ata_intel_chipinit(device_t dev); 56 static int ata_intel_ch_attach(device_t dev); 57 static void ata_intel_reset(device_t dev); 58 static int ata_intel_old_setmode(device_t dev, int target, int mode); 59 static int ata_intel_new_setmode(device_t dev, int target, int mode); 60 static int ata_intel_sch_setmode(device_t dev, int target, int mode); 61 static int ata_intel_sata_getrev(device_t dev, int target); 62 static int ata_intel_sata_status(device_t dev); 63 static int ata_intel_sata_ahci_read(device_t dev, int port, 64 int reg, u_int32_t *result); 65 static int ata_intel_sata_cscr_read(device_t dev, int port, 66 int reg, u_int32_t *result); 67 static int ata_intel_sata_sidpr_read(device_t dev, int port, 68 int reg, u_int32_t *result); 69 static int ata_intel_sata_ahci_write(device_t dev, int port, 70 int reg, u_int32_t result); 71 static int ata_intel_sata_cscr_write(device_t dev, int port, 72 int reg, u_int32_t result); 73 static int ata_intel_sata_sidpr_write(device_t dev, int port, 74 int reg, u_int32_t result); 75 static int ata_intel_31244_ch_attach(device_t dev); 76 static int ata_intel_31244_ch_detach(device_t dev); 77 static int ata_intel_31244_status(device_t dev); 78 static void ata_intel_31244_tf_write(struct ata_request *request); 79 static void ata_intel_31244_reset(device_t dev); 80 81 /* misc defines */ 82 #define INTEL_AHCI 1 83 #define INTEL_ICH5 2 84 #define INTEL_6CH 4 85 #define INTEL_6CH2 8 86 #define INTEL_ICH7 16 87 88 /* 89 * Intel chipset support functions 90 */ 91 static int 92 ata_intel_probe(device_t dev) 93 { 94 struct ata_pci_controller *ctlr = device_get_softc(dev); 95 static struct ata_chip_id ids[] = 96 {{ ATA_I82371FB, 0, 0, 2, ATA_WDMA2, "PIIX" }, 97 { ATA_I82371SB, 0, 0, 2, ATA_WDMA2, "PIIX3" }, 98 { ATA_I82371AB, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 99 { ATA_I82443MX, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 100 { ATA_I82451NX, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 101 { ATA_I82801AB, 0, 0, 2, ATA_UDMA2, "ICH0" }, 102 { ATA_I82801AA, 0, 0, 2, ATA_UDMA4, "ICH" }, 103 { ATA_I82372FB, 0, 0, 2, ATA_UDMA4, "ICH" }, 104 { ATA_I82801BA, 0, 0, 2, ATA_UDMA5, "ICH2" }, 105 { ATA_I82801BA_1, 0, 0, 2, ATA_UDMA5, "ICH2" }, 106 { ATA_I82801CA, 0, 0, 2, ATA_UDMA5, "ICH3" }, 107 { ATA_I82801CA_1, 0, 0, 2, ATA_UDMA5, "ICH3" }, 108 { ATA_I82801DB, 0, 0, 2, ATA_UDMA5, "ICH4" }, 109 { ATA_I82801DB_1, 0, 0, 2, ATA_UDMA5, "ICH4" }, 110 { ATA_I82801EB, 0, 0, 2, ATA_UDMA5, "ICH5" }, 111 { ATA_I82801EB_S1, 0, INTEL_ICH5, 2, ATA_SA150, "ICH5" }, 112 { ATA_I82801EB_R1, 0, INTEL_ICH5, 2, ATA_SA150, "ICH5" }, 113 { ATA_I6300ESB, 0, 0, 2, ATA_UDMA5, "6300ESB" }, 114 { ATA_I6300ESB_S1, 0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" }, 115 { ATA_I6300ESB_R1, 0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" }, 116 { ATA_I82801FB, 0, 0, 2, ATA_UDMA5, "ICH6" }, 117 { ATA_I82801FB_S1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6" }, 118 { ATA_I82801FB_R1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6" }, 119 { ATA_I82801FBM, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6M" }, 120 { ATA_I82801GB, 0, 0, 1, ATA_UDMA5, "ICH7" }, 121 { ATA_I82801GB_S1, 0, INTEL_ICH7, 0, ATA_SA300, "ICH7" }, 122 { ATA_I82801GB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" }, 123 { ATA_I82801GB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" }, 124 { ATA_I82801GBM_S1, 0, INTEL_ICH7, 0, ATA_SA150, "ICH7M" }, 125 { ATA_I82801GBM_R1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" }, 126 { ATA_I82801GBM_AH, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" }, 127 { ATA_I63XXESB2, 0, 0, 1, ATA_UDMA5, "63XXESB2" }, 128 { ATA_I63XXESB2_S1, 0, 0, 0, ATA_SA300, "63XXESB2" }, 129 { ATA_I63XXESB2_S2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 130 { ATA_I63XXESB2_R1, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 131 { ATA_I63XXESB2_R2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 132 { ATA_I82801HB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH8" }, 133 { ATA_I82801HB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH8" }, 134 { ATA_I82801HB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 135 { ATA_I82801HB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 136 { ATA_I82801HB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 137 { ATA_I82801HBM, 0, 0, 1, ATA_UDMA5, "ICH8M" }, 138 { ATA_I82801HBM_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH8M" }, 139 { ATA_I82801HBM_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" }, 140 { ATA_I82801HBM_S3, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" }, 141 { ATA_I82801IB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH9" }, 142 { ATA_I82801IB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9" }, 143 { ATA_I82801IB_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 144 { ATA_I82801IB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 145 { ATA_I82801IB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 146 { ATA_I82801IB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 147 { ATA_I82801JIB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, 148 { ATA_I82801JIB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 149 { ATA_I82801JIB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 150 { ATA_I82801JIB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, 151 { ATA_I82801JD_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, 152 { ATA_I82801JD_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 153 { ATA_I82801JD_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 154 { ATA_I82801JD_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, 155 { ATA_I82801JI_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, 156 { ATA_I82801JI_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 157 { ATA_I82801JI_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 158 { ATA_I82801JI_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, 159 { ATA_5Series_S1, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 160 { ATA_5Series_S2, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 161 { ATA_5Series_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 162 { ATA_5Series_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 163 { ATA_5Series_R1, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 164 { ATA_5Series_S3, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 165 { ATA_5Series_S4, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 166 { ATA_5Series_AH3, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 167 { ATA_5Series_R2, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 168 { ATA_5Series_S5, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 169 { ATA_5Series_S6, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 170 { ATA_5Series_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 171 { ATA_CPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Cougar Point" }, 172 { ATA_CPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Cougar Point" }, 173 { ATA_CPT_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, 174 { ATA_CPT_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, 175 { ATA_CPT_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, 176 { ATA_CPT_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, 177 { ATA_CPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" }, 178 { ATA_CPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" }, 179 { ATA_I31244, 0, 0, 2, ATA_SA150, "31244" }, 180 { ATA_ISCH, 0, 0, 1, ATA_UDMA5, "SCH" }, 181 { 0, 0, 0, 0, 0, 0}}; 182 183 if (pci_get_vendor(dev) != ATA_INTEL_ID) 184 return ENXIO; 185 186 if (!(ctlr->chip = ata_match_chip(dev, ids))) 187 return ENXIO; 188 189 ata_set_desc(dev); 190 ctlr->chipinit = ata_intel_chipinit; 191 return (BUS_PROBE_DEFAULT); 192 } 193 194 static int 195 ata_intel_chipinit(device_t dev) 196 { 197 struct ata_pci_controller *ctlr = device_get_softc(dev); 198 199 if (ata_setup_interrupt(dev, ata_generic_intr)) 200 return ENXIO; 201 202 ctlr->chipset_data = NULL; 203 204 /* good old PIIX needs special treatment (not implemented) */ 205 if (ctlr->chip->chipid == ATA_I82371FB) { 206 ctlr->setmode = ata_intel_old_setmode; 207 } 208 209 /* the intel 31244 needs special care if in DPA mode */ 210 else if (ctlr->chip->chipid == ATA_I31244) { 211 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) { 212 ctlr->r_type2 = SYS_RES_MEMORY; 213 ctlr->r_rid2 = PCIR_BAR(0); 214 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 215 &ctlr->r_rid2, 216 RF_ACTIVE))) 217 return ENXIO; 218 ctlr->channels = 4; 219 ctlr->ch_attach = ata_intel_31244_ch_attach; 220 ctlr->ch_detach = ata_intel_31244_ch_detach; 221 ctlr->reset = ata_intel_31244_reset; 222 } 223 ctlr->setmode = ata_sata_setmode; 224 ctlr->getrev = ata_sata_getrev; 225 } 226 /* SCH */ 227 else if (ctlr->chip->chipid == ATA_ISCH) { 228 ctlr->channels = 1; 229 ctlr->ch_attach = ata_intel_ch_attach; 230 ctlr->ch_detach = ata_pci_ch_detach; 231 ctlr->setmode = ata_intel_sch_setmode; 232 } 233 /* non SATA intel chips goes here */ 234 else if (ctlr->chip->max_dma < ATA_SA150) { 235 ctlr->channels = ctlr->chip->cfg2; 236 ctlr->ch_attach = ata_intel_ch_attach; 237 ctlr->ch_detach = ata_pci_ch_detach; 238 ctlr->setmode = ata_intel_new_setmode; 239 } 240 241 /* SATA parts can be either compat or AHCI */ 242 else { 243 /* force all ports active "the legacy way" */ 244 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f, 2); 245 246 ctlr->ch_attach = ata_intel_ch_attach; 247 ctlr->ch_detach = ata_pci_ch_detach; 248 ctlr->reset = ata_intel_reset; 249 250 /* 251 * if we have AHCI capability and AHCI or RAID mode enabled 252 * in BIOS we try for AHCI mode 253 */ 254 if ((ctlr->chip->cfg1 & INTEL_AHCI) && 255 (pci_read_config(dev, 0x90, 1) & 0xc0) && 256 (ata_ahci_chipinit(dev) != ENXIO)) 257 return 0; 258 259 /* BAR(5) may point to SATA interface registers */ 260 if ((ctlr->chip->cfg1 & INTEL_ICH7)) { 261 ctlr->r_type2 = SYS_RES_MEMORY; 262 ctlr->r_rid2 = PCIR_BAR(5); 263 ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 264 &ctlr->r_rid2, RF_ACTIVE); 265 if (ctlr->r_res2 != NULL) { 266 /* Set SCRAE bit to enable registers access. */ 267 pci_write_config(dev, 0x94, 268 pci_read_config(dev, 0x94, 4) | (1 << 9), 4); 269 /* Set Ports Implemented register bits. */ 270 ATA_OUTL(ctlr->r_res2, 0x0C, 271 ATA_INL(ctlr->r_res2, 0x0C) | 0xf); 272 } 273 } else { 274 ctlr->r_type2 = SYS_RES_IOPORT; 275 ctlr->r_rid2 = PCIR_BAR(5); 276 ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 277 &ctlr->r_rid2, RF_ACTIVE); 278 } 279 if (ctlr->r_res2 != NULL || 280 (ctlr->chip->cfg1 & INTEL_ICH5)) 281 ctlr->getrev = ata_intel_sata_getrev; 282 ctlr->setmode = ata_sata_setmode; 283 } 284 return 0; 285 } 286 287 static int 288 ata_intel_ch_attach(device_t dev) 289 { 290 struct ata_pci_controller *ctlr; 291 struct ata_channel *ch; 292 u_char *smap; 293 u_int map; 294 295 /* setup the usual register normal pci style */ 296 if (ata_pci_ch_attach(dev)) 297 return (ENXIO); 298 299 ctlr = device_get_softc(device_get_parent(dev)); 300 ch = device_get_softc(dev); 301 302 /* if r_res2 is valid it points to SATA interface registers */ 303 if (ctlr->r_res2) { 304 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 305 ch->r_io[ATA_IDX_ADDR].offset = 0x00; 306 ch->r_io[ATA_IDX_DATA].res = ctlr->r_res2; 307 ch->r_io[ATA_IDX_DATA].offset = 0x04; 308 } 309 310 ch->flags |= ATA_ALWAYS_DMASTAT; 311 if (ctlr->chip->max_dma >= ATA_SA150) { 312 smap = (u_char *)&ctlr->chipset_data + ch->unit * 2; 313 map = pci_read_config(device_get_parent(dev), 0x90, 1); 314 if (ctlr->chip->cfg1 & INTEL_ICH5) { 315 map &= 0x07; 316 if ((map & 0x04) == 0) { 317 ch->flags |= ATA_SATA; 318 ch->flags |= ATA_NO_SLAVE; 319 smap[0] = (map & 0x01) ^ ch->unit; 320 smap[1] = 0; 321 } else if ((map & 0x02) == 0 && ch->unit == 0) { 322 ch->flags |= ATA_SATA; 323 smap[0] = (map & 0x01) ? 1 : 0; 324 smap[1] = (map & 0x01) ? 0 : 1; 325 } else if ((map & 0x02) != 0 && ch->unit == 1) { 326 ch->flags |= ATA_SATA; 327 smap[0] = (map & 0x01) ? 1 : 0; 328 smap[1] = (map & 0x01) ? 0 : 1; 329 } 330 } else if (ctlr->chip->cfg1 & INTEL_6CH2) { 331 ch->flags |= ATA_SATA; 332 ch->flags |= ATA_NO_SLAVE; 333 smap[0] = (ch->unit == 0) ? 4 : 5; 334 smap[1] = 0; 335 } else { 336 map &= 0x03; 337 if (map == 0x00) { 338 ch->flags |= ATA_SATA; 339 smap[0] = (ch->unit == 0) ? 0 : 1; 340 smap[1] = (ch->unit == 0) ? 2 : 3; 341 } else if (map == 0x02 && ch->unit == 0) { 342 ch->flags |= ATA_SATA; 343 smap[0] = 0; 344 smap[1] = 2; 345 } else if (map == 0x01 && ch->unit == 1) { 346 ch->flags |= ATA_SATA; 347 smap[0] = 1; 348 smap[1] = 3; 349 } 350 } 351 if (ch->flags & ATA_SATA) { 352 if ((ctlr->chip->cfg1 & INTEL_ICH5)) { 353 ch->flags |= ATA_PERIODIC_POLL; 354 ch->hw.status = ata_intel_sata_status; 355 ch->hw.pm_read = ata_intel_sata_cscr_read; 356 ch->hw.pm_write = ata_intel_sata_cscr_write; 357 } else if (ctlr->r_res2) { 358 ch->flags |= ATA_PERIODIC_POLL; 359 ch->hw.status = ata_intel_sata_status; 360 if ((ctlr->chip->cfg1 & INTEL_ICH7)) { 361 ch->hw.pm_read = ata_intel_sata_ahci_read; 362 ch->hw.pm_write = ata_intel_sata_ahci_write; 363 } else { 364 ch->hw.pm_read = ata_intel_sata_sidpr_read; 365 ch->hw.pm_write = ata_intel_sata_sidpr_write; 366 }; 367 } 368 if (ch->hw.pm_write != NULL) { 369 ata_sata_scr_write(ch, 0, 370 ATA_SERROR, 0xffffffff); 371 if ((ch->flags & ATA_NO_SLAVE) == 0) { 372 ata_sata_scr_write(ch, 1, 373 ATA_SERROR, 0xffffffff); 374 } 375 } 376 } else 377 ctlr->setmode = ata_intel_new_setmode; 378 } else if (ctlr->chip->chipid != ATA_ISCH) 379 ch->flags |= ATA_CHECKS_CABLE; 380 return (0); 381 } 382 383 static void 384 ata_intel_reset(device_t dev) 385 { 386 device_t parent = device_get_parent(dev); 387 struct ata_pci_controller *ctlr = device_get_softc(parent); 388 struct ata_channel *ch = device_get_softc(dev); 389 int mask, pmask, timeout, devs; 390 u_char *smap; 391 392 /* In combined mode, skip SATA stuff for PATA channel. */ 393 if ((ch->flags & ATA_SATA) == 0) 394 return (ata_generic_reset(dev)); 395 396 /* Do hard-reset on respective SATA ports. */ 397 smap = (u_char *)&ctlr->chipset_data + ch->unit * 2; 398 mask = 1 << smap[0]; 399 if ((ch->flags & ATA_NO_SLAVE) == 0) 400 mask |= (1 << smap[1]); 401 pci_write_config(parent, 0x92, 402 pci_read_config(parent, 0x92, 2) & ~mask, 2); 403 DELAY(10); 404 pci_write_config(parent, 0x92, 405 pci_read_config(parent, 0x92, 2) | mask, 2); 406 407 /* Wait up to 1 sec for "connect well". */ 408 if (ctlr->chip->cfg1 & (INTEL_6CH | INTEL_6CH2)) 409 pmask = mask << 8; 410 else 411 pmask = mask << 4; 412 for (timeout = 0; timeout < 100 ; timeout++) { 413 if (((pci_read_config(parent, 0x92, 2) & pmask) == pmask) && 414 (ATA_IDX_INB(ch, ATA_STATUS) != 0xff)) 415 break; 416 ata_udelay(10000); 417 } 418 419 /* If any device found, do soft-reset. */ 420 if (ch->hw.pm_read != NULL) { 421 devs = ata_sata_phy_reset(dev, 0, 2); 422 if ((ch->flags & ATA_NO_SLAVE) == 0) 423 devs += ata_sata_phy_reset(dev, 1, 2); 424 } else 425 devs = 1; 426 if (devs) 427 ata_generic_reset(dev); 428 else 429 ch->devices = 0; 430 } 431 432 static int 433 ata_intel_old_setmode(device_t dev, int target, int mode) 434 { 435 device_t parent = device_get_parent(dev); 436 struct ata_pci_controller *ctlr = device_get_softc(parent); 437 438 mode = min(mode, ctlr->chip->max_dma); 439 return (mode); 440 } 441 442 static int 443 ata_intel_new_setmode(device_t dev, int target, int mode) 444 { 445 device_t parent = device_get_parent(dev); 446 struct ata_pci_controller *ctlr = device_get_softc(parent); 447 struct ata_channel *ch = device_get_softc(dev); 448 int devno = (ch->unit << 1) + target; 449 int piomode; 450 u_int32_t reg40 = pci_read_config(parent, 0x40, 4); 451 u_int8_t reg44 = pci_read_config(parent, 0x44, 1); 452 u_int8_t reg48 = pci_read_config(parent, 0x48, 1); 453 u_int16_t reg4a = pci_read_config(parent, 0x4a, 2); 454 u_int16_t reg54 = pci_read_config(parent, 0x54, 2); 455 u_int32_t mask40 = 0, new40 = 0; 456 u_int8_t mask44 = 0, new44 = 0; 457 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x00, 0x21, 0x23 }; 458 u_int8_t utimings[] = { 0x00, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02 }; 459 460 /* In combined mode, skip PATA stuff for SATA channel. */ 461 if (ch->flags & ATA_SATA) 462 return (ata_sata_setmode(dev, target, mode)); 463 464 mode = min(mode, ctlr->chip->max_dma); 465 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 466 !(reg54 & (0x10 << devno))) { 467 ata_print_cable(dev, "controller"); 468 mode = ATA_UDMA2; 469 } 470 /* Enable/disable UDMA and set timings. */ 471 if (mode >= ATA_UDMA0) { 472 pci_write_config(parent, 0x48, reg48 | (0x0001 << devno), 2); 473 pci_write_config(parent, 0x4a, 474 (reg4a & ~(0x3 << (devno << 2))) | 475 (utimings[mode & ATA_MODE_MASK] << (devno<<2)), 2); 476 piomode = ATA_PIO4; 477 } else { 478 pci_write_config(parent, 0x48, reg48 & ~(0x0001 << devno), 2); 479 pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (devno << 2))),2); 480 piomode = mode; 481 } 482 reg54 |= 0x0400; 483 /* Set UDMA reference clock (33/66/133MHz). */ 484 reg54 &= ~(0x1001 << devno); 485 if (mode >= ATA_UDMA5) 486 reg54 |= (0x1000 << devno); 487 else if (mode >= ATA_UDMA3) 488 reg54 |= (0x1 << devno); 489 pci_write_config(parent, 0x54, reg54, 2); 490 /* Allow PIO/WDMA timing controls. */ 491 reg40 &= ~0x00ff00ff; 492 reg40 |= 0x40774077; 493 /* Set PIO/WDMA timings. */ 494 if (target == 0) { 495 mask40 = 0x3300; 496 new40 = timings[ata_mode2idx(piomode)] << 8; 497 } else { 498 mask44 = 0x0f; 499 new44 = ((timings[ata_mode2idx(piomode)] & 0x30) >> 2) | 500 (timings[ata_mode2idx(piomode)] & 0x03); 501 } 502 if (ch->unit) { 503 mask40 <<= 16; 504 new40 <<= 16; 505 mask44 <<= 4; 506 new44 <<= 4; 507 } 508 pci_write_config(parent, 0x40, (reg40 & ~mask40) | new40, 4); 509 pci_write_config(parent, 0x44, (reg44 & ~mask44) | new44, 1); 510 return (mode); 511 } 512 513 static int 514 ata_intel_sch_setmode(device_t dev, int target, int mode) 515 { 516 device_t parent = device_get_parent(dev); 517 struct ata_pci_controller *ctlr = device_get_softc(parent); 518 u_int8_t dtim = 0x80 + (target << 2); 519 u_int32_t tim = pci_read_config(parent, dtim, 4); 520 int piomode; 521 522 mode = min(mode, ctlr->chip->max_dma); 523 if (mode >= ATA_UDMA0) { 524 tim |= (0x1 << 31); 525 tim &= ~(0x7 << 16); 526 tim |= ((mode & ATA_MODE_MASK) << 16); 527 piomode = ATA_PIO4; 528 } else if (mode >= ATA_WDMA0) { 529 tim &= ~(0x1 << 31); 530 tim &= ~(0x3 << 8); 531 tim |= ((mode & ATA_MODE_MASK) << 8); 532 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 : 533 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4; 534 } else 535 piomode = mode; 536 tim &= ~(0x7); 537 tim |= (piomode & 0x7); 538 pci_write_config(parent, dtim, tim, 4); 539 return (mode); 540 } 541 542 static int 543 ata_intel_sata_getrev(device_t dev, int target) 544 { 545 struct ata_channel *ch = device_get_softc(dev); 546 uint32_t status; 547 548 if (ata_sata_scr_read(ch, target, ATA_SSTATUS, &status) == 0) 549 return ((status & 0x0f0) >> 4); 550 return (0xff); 551 } 552 553 static int 554 ata_intel_sata_status(device_t dev) 555 { 556 struct ata_channel *ch = device_get_softc(dev); 557 558 ata_sata_phy_check_events(dev, 0); 559 if ((ch->flags & ATA_NO_SLAVE) == 0) 560 ata_sata_phy_check_events(dev, 1); 561 562 return ata_pci_status(dev); 563 } 564 565 static int 566 ata_intel_sata_ahci_read(device_t dev, int port, int reg, u_int32_t *result) 567 { 568 struct ata_pci_controller *ctlr; 569 struct ata_channel *ch; 570 device_t parent; 571 u_char *smap; 572 int offset; 573 574 parent = device_get_parent(dev); 575 ctlr = device_get_softc(parent); 576 ch = device_get_softc(dev); 577 port = (port == 1) ? 1 : 0; 578 smap = (u_char *)&ctlr->chipset_data + ch->unit * 2; 579 offset = 0x100 + smap[port] * 0x80; 580 switch (reg) { 581 case ATA_SSTATUS: 582 reg = 0x28; 583 break; 584 case ATA_SCONTROL: 585 reg = 0x2c; 586 break; 587 case ATA_SERROR: 588 reg = 0x30; 589 break; 590 default: 591 return (EINVAL); 592 } 593 *result = ATA_INL(ctlr->r_res2, offset + reg); 594 return (0); 595 } 596 597 static int 598 ata_intel_sata_cscr_read(device_t dev, int port, int reg, u_int32_t *result) 599 { 600 struct ata_pci_controller *ctlr; 601 struct ata_channel *ch; 602 device_t parent; 603 u_char *smap; 604 605 parent = device_get_parent(dev); 606 ctlr = device_get_softc(parent); 607 ch = device_get_softc(dev); 608 smap = (u_char *)&ctlr->chipset_data + ch->unit * 2; 609 port = (port == 1) ? 1 : 0; 610 switch (reg) { 611 case ATA_SSTATUS: 612 reg = 0; 613 break; 614 case ATA_SERROR: 615 reg = 1; 616 break; 617 case ATA_SCONTROL: 618 reg = 2; 619 break; 620 default: 621 return (EINVAL); 622 } 623 pci_write_config(parent, 0xa0, 624 0x50 + smap[port] * 0x10 + reg * 4, 4); 625 *result = pci_read_config(parent, 0xa4, 4); 626 return (0); 627 } 628 629 static int 630 ata_intel_sata_sidpr_read(device_t dev, int port, int reg, u_int32_t *result) 631 { 632 struct ata_pci_controller *ctlr; 633 struct ata_channel *ch; 634 device_t parent; 635 636 parent = device_get_parent(dev); 637 ctlr = device_get_softc(parent); 638 ch = device_get_softc(dev); 639 port = (port == 1) ? 1 : 0; 640 switch (reg) { 641 case ATA_SSTATUS: 642 reg = 0; 643 break; 644 case ATA_SCONTROL: 645 reg = 1; 646 break; 647 case ATA_SERROR: 648 reg = 2; 649 break; 650 default: 651 return (EINVAL); 652 } 653 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, ((ch->unit * 2 + port) << 8) + reg); 654 *result = ATA_IDX_INL(ch, ATA_IDX_DATA); 655 return (0); 656 } 657 658 static int 659 ata_intel_sata_ahci_write(device_t dev, int port, int reg, u_int32_t value) 660 { 661 struct ata_pci_controller *ctlr; 662 struct ata_channel *ch; 663 device_t parent; 664 u_char *smap; 665 int offset; 666 667 parent = device_get_parent(dev); 668 ctlr = device_get_softc(parent); 669 ch = device_get_softc(dev); 670 port = (port == 1) ? 1 : 0; 671 smap = (u_char *)&ctlr->chipset_data + ch->unit * 2; 672 offset = 0x100 + smap[port] * 0x80; 673 switch (reg) { 674 case ATA_SSTATUS: 675 reg = 0x28; 676 break; 677 case ATA_SCONTROL: 678 reg = 0x2c; 679 break; 680 case ATA_SERROR: 681 reg = 0x30; 682 break; 683 default: 684 return (EINVAL); 685 } 686 ATA_OUTL(ctlr->r_res2, offset + reg, value); 687 return (0); 688 } 689 690 static int 691 ata_intel_sata_cscr_write(device_t dev, int port, int reg, u_int32_t value) 692 { 693 struct ata_pci_controller *ctlr; 694 struct ata_channel *ch; 695 device_t parent; 696 u_char *smap; 697 698 parent = device_get_parent(dev); 699 ctlr = device_get_softc(parent); 700 ch = device_get_softc(dev); 701 smap = (u_char *)&ctlr->chipset_data + ch->unit * 2; 702 port = (port == 1) ? 1 : 0; 703 switch (reg) { 704 case ATA_SSTATUS: 705 reg = 0; 706 break; 707 case ATA_SERROR: 708 reg = 1; 709 break; 710 case ATA_SCONTROL: 711 reg = 2; 712 break; 713 default: 714 return (EINVAL); 715 } 716 pci_write_config(parent, 0xa0, 717 0x50 + smap[port] * 0x10 + reg * 4, 4); 718 pci_write_config(parent, 0xa4, value, 4); 719 return (0); 720 } 721 722 static int 723 ata_intel_sata_sidpr_write(device_t dev, int port, int reg, u_int32_t value) 724 { 725 struct ata_pci_controller *ctlr; 726 struct ata_channel *ch; 727 device_t parent; 728 729 parent = device_get_parent(dev); 730 ctlr = device_get_softc(parent); 731 ch = device_get_softc(dev); 732 port = (port == 1) ? 1 : 0; 733 switch (reg) { 734 case ATA_SSTATUS: 735 reg = 0; 736 break; 737 case ATA_SCONTROL: 738 reg = 1; 739 break; 740 case ATA_SERROR: 741 reg = 2; 742 break; 743 default: 744 return (EINVAL); 745 } 746 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, ((ch->unit * 2 + port) << 8) + reg); 747 ATA_IDX_OUTL(ch, ATA_IDX_DATA, value); 748 return (0); 749 } 750 751 static int 752 ata_intel_31244_ch_attach(device_t dev) 753 { 754 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 755 struct ata_channel *ch = device_get_softc(dev); 756 int i; 757 int ch_offset; 758 759 ata_pci_dmainit(dev); 760 761 ch_offset = 0x200 + ch->unit * 0x200; 762 763 for (i = ATA_DATA; i < ATA_MAX_RES; i++) 764 ch->r_io[i].res = ctlr->r_res2; 765 766 /* setup ATA registers */ 767 ch->r_io[ATA_DATA].offset = ch_offset + 0x00; 768 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06; 769 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08; 770 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c; 771 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; 772 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14; 773 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18; 774 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d; 775 ch->r_io[ATA_ERROR].offset = ch_offset + 0x04; 776 ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c; 777 ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28; 778 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29; 779 780 /* setup DMA registers */ 781 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100; 782 ch->r_io[ATA_SERROR].offset = ch_offset + 0x104; 783 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108; 784 785 /* setup SATA registers */ 786 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70; 787 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72; 788 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74; 789 790 ch->flags |= ATA_NO_SLAVE; 791 ch->flags |= ATA_SATA; 792 ata_pci_hw(dev); 793 ch->hw.status = ata_intel_31244_status; 794 ch->hw.tf_write = ata_intel_31244_tf_write; 795 796 /* enable PHY state change interrupt */ 797 ATA_OUTL(ctlr->r_res2, 0x4, 798 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3))); 799 return 0; 800 } 801 802 static int 803 ata_intel_31244_ch_detach(device_t dev) 804 { 805 806 ata_pci_dmafini(dev); 807 return (0); 808 } 809 810 static int 811 ata_intel_31244_status(device_t dev) 812 { 813 /* do we have any PHY events ? */ 814 ata_sata_phy_check_events(dev, -1); 815 816 /* any drive action to take care of ? */ 817 return ata_pci_status(dev); 818 } 819 820 static void 821 ata_intel_31244_tf_write(struct ata_request *request) 822 { 823 struct ata_channel *ch = device_get_softc(request->parent); 824 #ifndef ATA_CAM 825 struct ata_device *atadev = device_get_softc(request->dev); 826 #endif 827 828 if (request->flags & ATA_R_48BIT) { 829 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature); 830 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count); 831 ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) | 832 (request->u.ata.lba & 0x00ff)); 833 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) | 834 ((request->u.ata.lba >> 8) & 0x00ff)); 835 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) | 836 ((request->u.ata.lba >> 16) & 0x00ff)); 837 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit)); 838 } 839 else { 840 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 841 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 842 #ifndef ATA_CAM 843 if (atadev->flags & ATA_D_USE_CHS) { 844 int heads, sectors; 845 846 if (atadev->param.atavalid & ATA_FLAG_54_58) { 847 heads = atadev->param.current_heads; 848 sectors = atadev->param.current_sectors; 849 } 850 else { 851 heads = atadev->param.heads; 852 sectors = atadev->param.sectors; 853 } 854 ATA_IDX_OUTB(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1); 855 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 856 (request->u.ata.lba / (sectors * heads))); 857 ATA_IDX_OUTB(ch, ATA_CYL_MSB, 858 (request->u.ata.lba / (sectors * heads)) >> 8); 859 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit) | 860 (((request->u.ata.lba% (sectors * heads)) / 861 sectors) & 0xf)); 862 } 863 else { 864 #endif 865 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 866 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 867 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 868 ATA_IDX_OUTB(ch, ATA_DRIVE, 869 ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) | 870 ((request->u.ata.lba >> 24) & 0x0f)); 871 #ifndef ATA_CAM 872 } 873 #endif 874 } 875 } 876 877 static void 878 ata_intel_31244_reset(device_t dev) 879 { 880 struct ata_channel *ch = device_get_softc(dev); 881 882 if (ata_sata_phy_reset(dev, -1, 1)) 883 ata_generic_reset(dev); 884 else 885 ch->devices = 0; 886 } 887 888 ATA_DECLARE_DRIVER(ata_intel); 889 MODULE_DEPEND(ata_intel, ata_ahci, 1, 1, 1); 890