xref: /freebsd/sys/dev/ata/chipsets/ata-highpoint.c (revision 6549718b70f0e660a15685369afb4f9caf2215ce)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
3  *
4  * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer,
12  *    without modification, immediately at the beginning of the file.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  */
28 
29 #include <sys/param.h>
30 #include <sys/module.h>
31 #include <sys/systm.h>
32 #include <sys/kernel.h>
33 #include <sys/ata.h>
34 #include <sys/bus.h>
35 #include <sys/endian.h>
36 #include <sys/malloc.h>
37 #include <sys/lock.h>
38 #include <sys/mutex.h>
39 #include <sys/sema.h>
40 #include <sys/taskqueue.h>
41 #include <vm/uma.h>
42 #include <machine/stdarg.h>
43 #include <machine/resource.h>
44 #include <machine/bus.h>
45 #include <sys/rman.h>
46 #include <dev/pci/pcivar.h>
47 #include <dev/pci/pcireg.h>
48 #include <dev/ata/ata-all.h>
49 #include <dev/ata/ata-pci.h>
50 #include <ata_if.h>
51 
52 /* local prototypes */
53 static int ata_highpoint_chipinit(device_t dev);
54 static int ata_highpoint_ch_attach(device_t dev);
55 static int ata_highpoint_setmode(device_t dev, int target, int mode);
56 static int ata_highpoint_check_80pin(device_t dev, int mode);
57 
58 /* misc defines */
59 #define HPT_366		0
60 #define HPT_370		1
61 #define HPT_372		2
62 #define HPT_374		3
63 #define HPT_OLD		1
64 
65 /*
66  * HighPoint chipset support functions
67  */
68 static int
69 ata_highpoint_probe(device_t dev)
70 {
71     struct ata_pci_controller *ctlr = device_get_softc(dev);
72     const struct ata_chip_id *idx;
73     static const struct ata_chip_id ids[] =
74     {{ ATA_HPT374, 0x07, HPT_374, 0,       ATA_UDMA6, "HPT374" },
75      { ATA_HPT372, 0x02, HPT_372, 0,       ATA_UDMA6, "HPT372N" },
76      { ATA_HPT372, 0x01, HPT_372, 0,       ATA_UDMA6, "HPT372" },
77      { ATA_HPT371, 0x01, HPT_372, 0,       ATA_UDMA6, "HPT371" },
78      { ATA_HPT366, 0x05, HPT_372, 0,       ATA_UDMA6, "HPT372" },
79      { ATA_HPT366, 0x03, HPT_370, 0,       ATA_UDMA5, "HPT370" },
80      { ATA_HPT366, 0x02, HPT_366, 0,       ATA_UDMA4, "HPT368" },
81      { ATA_HPT366, 0x00, HPT_366, HPT_OLD, ATA_UDMA4, "HPT366" },
82      { ATA_HPT302, 0x01, HPT_372, 0,       ATA_UDMA6, "HPT302" },
83      { 0, 0, 0, 0, 0, 0}};
84     const char *channel;
85 
86     if (pci_get_vendor(dev) != ATA_HIGHPOINT_ID)
87         return ENXIO;
88 
89     if (!(idx = ata_match_chip(dev, ids)))
90 	return ENXIO;
91 
92     channel = "";
93     if (idx->cfg1 == HPT_374) {
94 	if (pci_get_function(dev) == 0)
95 	    channel = " (channel 0+1)";
96 	else if (pci_get_function(dev) == 1)
97 	    channel = " (channel 2+3)";
98     }
99     device_set_descf(dev, "Highpoint %s%s %s controller",
100 	idx->text, channel, ata_mode2str(idx->max_dma));
101     ctlr->chip = idx;
102     ctlr->chipinit = ata_highpoint_chipinit;
103     return (BUS_PROBE_LOW_PRIORITY);
104 }
105 
106 static int
107 ata_highpoint_chipinit(device_t dev)
108 {
109     struct ata_pci_controller *ctlr = device_get_softc(dev);
110 
111     if (ata_setup_interrupt(dev, ata_generic_intr))
112 	return ENXIO;
113 
114     if (ctlr->chip->cfg2 == HPT_OLD) {
115 	/* disable interrupt prediction */
116 	pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
117     }
118     else {
119 	/* disable interrupt prediction */
120 	pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
121 	pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
122 
123 	/* enable interrupts */
124 	pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
125 
126 	/* set clocks etc */
127 	if (ctlr->chip->cfg1 < HPT_372)
128 	    pci_write_config(dev, 0x5b, 0x22, 1);
129 	else
130 	    pci_write_config(dev, 0x5b,
131 			     (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
132     }
133     ctlr->ch_attach = ata_highpoint_ch_attach;
134     ctlr->ch_detach = ata_pci_ch_detach;
135     ctlr->setmode = ata_highpoint_setmode;
136     return 0;
137 }
138 
139 static int
140 ata_highpoint_ch_attach(device_t dev)
141 {
142 	struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
143 	struct ata_channel *ch = device_get_softc(dev);
144 
145 	/* setup the usual register normal pci style */
146 	if (ata_pci_ch_attach(dev))
147 		return (ENXIO);
148 	ch->flags |= ATA_ALWAYS_DMASTAT;
149 	ch->flags |= ATA_CHECKS_CABLE;
150 	if (ctlr->chip->cfg1 == HPT_366)
151 		ch->flags |= ATA_NO_ATAPI_DMA;
152 	return (0);
153 }
154 
155 static int
156 ata_highpoint_setmode(device_t dev, int target, int mode)
157 {
158 	device_t parent = device_get_parent(dev);
159 	struct ata_pci_controller *ctlr = device_get_softc(parent);
160 	struct ata_channel *ch = device_get_softc(dev);
161 	int devno = (ch->unit << 1) + target;
162 	static const uint32_t timings33[][4] = {
163 	/*    HPT366      HPT370      HPT372      HPT374           mode */
164 	{ 0x40d0a7aa, 0x06914e57, 0x0d029d5e, 0x0ac1f48a },     /* PIO 0 */
165 	{ 0x40d0a7a3, 0x06914e43, 0x0d029d26, 0x0ac1f465 },     /* PIO 1 */
166 	{ 0x40d0a753, 0x06514e33, 0x0c829ca6, 0x0a81f454 },     /* PIO 2 */
167 	{ 0x40c8a742, 0x06514e22, 0x0c829c84, 0x0a81f443 },     /* PIO 3 */
168 	{ 0x40c8a731, 0x06514e21, 0x0c829c62, 0x0a81f442 },     /* PIO 4 */
169 	{ 0x20c8a797, 0x26514e97, 0x2c82922e, 0x228082ea },     /* MWDMA 0 */
170 	{ 0x20c8a732, 0x26514e33, 0x2c829266, 0x22808254 },     /* MWDMA 1 */
171 	{ 0x20c8a731, 0x26514e21, 0x2c829262, 0x22808242 },     /* MWDMA 2 */
172 	{ 0x10c8a731, 0x16514e31, 0x1c829c62, 0x121882ea },     /* UDMA 0 */
173 	{ 0x10cba731, 0x164d4e31, 0x1c9a9c62, 0x12148254 },     /* UDMA 1 */
174 	{ 0x10caa731, 0x16494e31, 0x1c929c62, 0x120c8242 },     /* UDMA 2 */
175 	{ 0x10cfa731, 0x166d4e31, 0x1c8e9c62, 0x128c8242 },     /* UDMA 3 */
176 	{ 0x10c9a731, 0x16454e31, 0x1c8a9c62, 0x12ac8242 },     /* UDMA 4 */
177 	{ 0,          0x16454e31, 0x1c8a9c62, 0x12848242 },     /* UDMA 5 */
178 	{ 0,          0,          0x1c869c62, 0x12808242 }      /* UDMA 6 */
179 	};
180 
181 	mode = min(mode, ctlr->chip->max_dma);
182 	mode = ata_highpoint_check_80pin(dev, mode);
183 	/*
184 	 * most if not all HPT chips cant really handle that the device is
185 	 * running at ATA_UDMA6/ATA133 speed, so we cheat at set the device to
186          * a max of ATA_UDMA5/ATA100 to guard against suboptimal performance
187 	 */
188 	mode = min(mode, ATA_UDMA5);
189 	pci_write_config(parent, 0x40 + (devno << 2),
190 			 timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
191 	return (mode);
192 }
193 
194 static int
195 ata_highpoint_check_80pin(device_t dev, int mode)
196 {
197     device_t parent = device_get_parent(dev);
198     struct ata_pci_controller *ctlr = device_get_softc(parent);
199     struct ata_channel *ch = device_get_softc(dev);
200     u_int8_t reg, val, res;
201 
202     if (ctlr->chip->cfg1 == HPT_374 && pci_get_function(parent) == 1) {
203 	reg = ch->unit ? 0x57 : 0x53;
204 	val = pci_read_config(parent, reg, 1);
205 	pci_write_config(parent, reg, val | 0x80, 1);
206     }
207     else {
208 	reg = 0x5b;
209 	val = pci_read_config(parent, reg, 1);
210 	pci_write_config(parent, reg, val & 0xfe, 1);
211     }
212     res = pci_read_config(parent, 0x5a, 1) & (ch->unit ? 0x1:0x2);
213     pci_write_config(parent, reg, val, 1);
214 
215     if (ata_dma_check_80pin && mode > ATA_UDMA2 && res) {
216 	ata_print_cable(dev, "controller");
217 	mode = ATA_UDMA2;
218     }
219     return mode;
220 }
221 
222 ATA_DECLARE_DRIVER(ata_highpoint);
223