1 /*- 2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/module.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/ata.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/malloc.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 #include <sys/sema.h> 41 #include <sys/taskqueue.h> 42 #include <vm/uma.h> 43 #include <machine/stdarg.h> 44 #include <machine/resource.h> 45 #include <machine/bus.h> 46 #include <sys/rman.h> 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcireg.h> 49 #include <dev/ata/ata-all.h> 50 #include <dev/ata/ata-pci.h> 51 #include <ata_if.h> 52 53 /* local prototypes */ 54 static int ata_ati_chipinit(device_t dev); 55 static int ata_ati_dumb_ch_attach(device_t dev); 56 static int ata_ati_ixp700_ch_attach(device_t dev); 57 static int ata_ati_setmode(device_t dev, int target, int mode); 58 59 /* misc defines */ 60 #define SII_MEMIO 1 /* must match ata_siliconimage.c's definition */ 61 #define SII_BUG 0x04 /* must match ata_siliconimage.c's definition */ 62 63 #define ATI_SATA SII_MEMIO 64 #define ATI_PATA 0x02 65 #define ATI_AHCI 0x04 66 67 static int force_ahci = 1; 68 TUNABLE_INT("hw.ahci.force", &force_ahci); 69 70 /* 71 * ATI chipset support functions 72 */ 73 static int 74 ata_ati_probe(device_t dev) 75 { 76 struct ata_pci_controller *ctlr = device_get_softc(dev); 77 static const struct ata_chip_id ids[] = 78 {{ ATA_ATI_IXP200, 0x00, ATI_PATA, 0, ATA_UDMA5, "IXP200" }, 79 { ATA_ATI_IXP300, 0x00, ATI_PATA, 0, ATA_UDMA6, "IXP300" }, 80 { ATA_ATI_IXP300_S1, 0x00, ATI_SATA, SII_BUG, ATA_SA150, "IXP300" }, 81 { ATA_ATI_IXP400, 0x00, ATI_PATA, 0, ATA_UDMA6, "IXP400" }, 82 { ATA_ATI_IXP400_S1, 0x00, ATI_SATA, SII_BUG, ATA_SA150, "IXP400" }, 83 { ATA_ATI_IXP400_S2, 0x00, ATI_SATA, SII_BUG, ATA_SA150, "IXP400" }, 84 { ATA_ATI_IXP600, 0x00, ATI_PATA, 0, ATA_UDMA6, "IXP600" }, 85 { ATA_ATI_IXP600_S1, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP600" }, 86 { ATA_ATI_IXP700, 0x00, ATI_PATA, 0, ATA_UDMA6, "IXP700/800" }, 87 { ATA_ATI_IXP700_S1, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP700/800" }, 88 { ATA_ATI_IXP700_S2, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP700/800" }, 89 { ATA_ATI_IXP700_S3, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP700/800" }, 90 { ATA_ATI_IXP700_S4, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP700/800" }, 91 { ATA_ATI_IXP800_S1, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP800" }, 92 { ATA_ATI_IXP800_S2, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP800" }, 93 { ATA_AMD_HUDSON2, 0x00, ATI_PATA, 0, ATA_UDMA6, "Hudson-2" }, 94 { ATA_AMD_HUDSON2_S1, 0x00, ATI_AHCI, 0, ATA_SA300, "Hudson-2" }, 95 { ATA_AMD_HUDSON2_S2, 0x00, ATI_AHCI, 0, ATA_SA300, "Hudson-2" }, 96 { ATA_AMD_HUDSON2_S3, 0x00, ATI_AHCI, 0, ATA_SA300, "Hudson-2" }, 97 { ATA_AMD_HUDSON2_S4, 0x00, ATI_AHCI, 0, ATA_SA300, "Hudson-2" }, 98 { ATA_AMD_HUDSON2_S5, 0x00, ATI_AHCI, 0, ATA_SA300, "Hudson-2" }, 99 { 0, 0, 0, 0, 0, 0}}; 100 101 if (pci_get_vendor(dev) != ATA_ATI_ID) 102 return ENXIO; 103 104 if (!(ctlr->chip = ata_match_chip(dev, ids))) 105 return ENXIO; 106 107 ata_set_desc(dev); 108 109 switch (ctlr->chip->cfg1) { 110 case ATI_PATA: 111 ctlr->chipinit = ata_ati_chipinit; 112 break; 113 case ATI_SATA: 114 /* 115 * the ATI SATA controller is actually a SiI 3112 controller 116 */ 117 ctlr->chipinit = ata_sii_chipinit; 118 break; 119 case ATI_AHCI: 120 if (force_ahci == 1 || pci_get_subclass(dev) != PCIS_STORAGE_IDE) 121 ctlr->chipinit = ata_ahci_chipinit; 122 else 123 ctlr->chipinit = ata_ati_chipinit; 124 break; 125 } 126 return (BUS_PROBE_DEFAULT); 127 } 128 129 static int 130 ata_ati_chipinit(device_t dev) 131 { 132 struct ata_pci_controller *ctlr = device_get_softc(dev); 133 device_t smbdev; 134 uint8_t satacfg; 135 136 if (ata_setup_interrupt(dev, ata_generic_intr)) 137 return ENXIO; 138 139 if (ctlr->chip->cfg1 == ATI_AHCI) { 140 ctlr->ch_attach = ata_ati_dumb_ch_attach; 141 ctlr->setmode = ata_sata_setmode; 142 return (0); 143 } 144 switch (ctlr->chip->chipid) { 145 case ATA_ATI_IXP600: 146 /* IXP600 only has 1 PATA channel */ 147 ctlr->channels = 1; 148 break; 149 case ATA_ATI_IXP700: 150 /* 151 * When "combined mode" is enabled, an additional PATA channel is 152 * emulated with two SATA ports and appears on this device. 153 * This mode can only be detected via SMB controller. 154 */ 155 smbdev = pci_find_device(ATA_ATI_ID, 0x4385); 156 if (smbdev != NULL) { 157 satacfg = pci_read_config(smbdev, 0xad, 1); 158 if (bootverbose) 159 device_printf(dev, "SATA controller %s (%s%s channel)\n", 160 (satacfg & 0x01) == 0 ? "disabled" : "enabled", 161 (satacfg & 0x08) == 0 ? "" : "combined mode, ", 162 (satacfg & 0x10) == 0 ? "primary" : "secondary"); 163 ctlr->chipset_data = (void *)(uintptr_t)satacfg; 164 /* 165 * If SATA controller is enabled but combined mode is disabled, 166 * we have only one PATA channel. Ignore a non-existent channel. 167 */ 168 if ((satacfg & 0x09) == 0x01) 169 ctlr->ichannels &= ~(1 << ((satacfg & 0x10) >> 4)); 170 else { 171 ctlr->ch_attach = ata_ati_ixp700_ch_attach; 172 } 173 } 174 break; 175 } 176 177 ctlr->setmode = ata_ati_setmode; 178 return 0; 179 } 180 181 static int 182 ata_ati_dumb_ch_attach(device_t dev) 183 { 184 struct ata_channel *ch = device_get_softc(dev); 185 186 if (ata_pci_ch_attach(dev)) 187 return ENXIO; 188 ch->flags |= ATA_SATA; 189 return (0); 190 } 191 192 static int 193 ata_ati_ixp700_ch_attach(device_t dev) 194 { 195 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 196 struct ata_channel *ch = device_get_softc(dev); 197 uint8_t satacfg = (uint8_t)(uintptr_t)ctlr->chipset_data; 198 199 /* Setup the usual register normal pci style. */ 200 if (ata_pci_ch_attach(dev)) 201 return ENXIO; 202 203 /* One of channels is PATA, another is SATA. */ 204 if (ch->unit == ((satacfg & 0x10) >> 4)) 205 ch->flags |= ATA_SATA; 206 return (0); 207 } 208 209 static int 210 ata_ati_setmode(device_t dev, int target, int mode) 211 { 212 device_t parent = device_get_parent(dev); 213 struct ata_pci_controller *ctlr = device_get_softc(parent); 214 struct ata_channel *ch = device_get_softc(dev); 215 int devno = (ch->unit << 1) + target; 216 int offset = (devno ^ 0x01) << 3; 217 int piomode; 218 static const uint8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 }; 219 static const uint8_t dmatimings[] = { 0x77, 0x21, 0x20 }; 220 221 mode = min(mode, ctlr->chip->max_dma); 222 if (mode >= ATA_UDMA0) { 223 /* Set UDMA mode, enable UDMA, set WDMA2/PIO4 */ 224 pci_write_config(parent, 0x56, 225 (pci_read_config(parent, 0x56, 2) & 226 ~(0xf << (devno << 2))) | 227 ((mode & ATA_MODE_MASK) << (devno << 2)), 2); 228 pci_write_config(parent, 0x54, 229 pci_read_config(parent, 0x54, 1) | 230 (0x01 << devno), 1); 231 pci_write_config(parent, 0x44, 232 (pci_read_config(parent, 0x44, 4) & 233 ~(0xff << offset)) | 234 (dmatimings[2] << offset), 4); 235 piomode = ATA_PIO4; 236 } else if (mode >= ATA_WDMA0) { 237 /* Disable UDMA, set WDMA mode and timings, calculate PIO. */ 238 pci_write_config(parent, 0x54, 239 pci_read_config(parent, 0x54, 1) & 240 ~(0x01 << devno), 1); 241 pci_write_config(parent, 0x44, 242 (pci_read_config(parent, 0x44, 4) & 243 ~(0xff << offset)) | 244 (dmatimings[mode & ATA_MODE_MASK] << offset), 4); 245 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 : 246 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4; 247 } else { 248 /* Disable UDMA, set requested PIO. */ 249 pci_write_config(parent, 0x54, 250 pci_read_config(parent, 0x54, 1) & 251 ~(0x01 << devno), 1); 252 piomode = mode; 253 } 254 /* Set PIO mode and timings, calculated above. */ 255 pci_write_config(parent, 0x4a, 256 (pci_read_config(parent, 0x4a, 2) & 257 ~(0xf << (devno << 2))) | 258 ((piomode - ATA_PIO0) << (devno<<2)),2); 259 pci_write_config(parent, 0x40, 260 (pci_read_config(parent, 0x40, 4) & 261 ~(0xff << offset)) | 262 (piotimings[ata_mode2idx(piomode)] << offset), 4); 263 return (mode); 264 } 265 266 ATA_DECLARE_DRIVER(ata_ati); 267 MODULE_DEPEND(ata_ati, ata_ahci, 1, 1, 1); 268 MODULE_DEPEND(ata_ati, ata_sii, 1, 1, 1); 269