1 /*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ata.h" 31 #include <sys/param.h> 32 #include <sys/module.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/ata.h> 36 #include <sys/bus.h> 37 #include <sys/endian.h> 38 #include <sys/malloc.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/sema.h> 42 #include <sys/taskqueue.h> 43 #include <vm/uma.h> 44 #include <machine/stdarg.h> 45 #include <machine/resource.h> 46 #include <machine/bus.h> 47 #include <sys/rman.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/ata/ata-all.h> 51 #include <dev/ata/ata-pci.h> 52 #include <ata_if.h> 53 54 /* local prototypes */ 55 static int ata_ati_chipinit(device_t dev); 56 static int ata_ati_setmode(device_t dev, int target, int mode); 57 58 /* misc defines */ 59 #define ATI_PATA 0x01 60 #define ATI_SATA 0x02 61 #define ATI_AHCI 0x04 62 #define SII_MEMIO 1 63 #define SII_BUG 0x04 64 65 66 /* 67 * ATI chipset support functions 68 */ 69 static int 70 ata_ati_probe(device_t dev) 71 { 72 struct ata_pci_controller *ctlr = device_get_softc(dev); 73 static struct ata_chip_id ids[] = 74 {{ ATA_ATI_IXP200, 0x00, ATI_PATA, 0, ATA_UDMA5, "IXP200" }, 75 { ATA_ATI_IXP300, 0x00, ATI_PATA, 0, ATA_UDMA6, "IXP300" }, 76 { ATA_ATI_IXP300_S1, 0x00, ATI_SATA, 0, ATA_SA150, "IXP300" }, 77 { ATA_ATI_IXP400, 0x00, ATI_PATA, 0, ATA_UDMA6, "IXP400" }, 78 { ATA_ATI_IXP400_S1, 0x00, ATI_SATA, 0, ATA_SA150, "IXP400" }, 79 { ATA_ATI_IXP400_S2, 0x00, ATI_SATA, 0, ATA_SA150, "IXP400" }, 80 { ATA_ATI_IXP600, 0x00, ATI_PATA, 0, ATA_UDMA6, "IXP600" }, 81 { ATA_ATI_IXP600_S1, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP600" }, 82 { ATA_ATI_IXP700, 0x00, ATI_PATA, 0, ATA_UDMA6, "IXP700/800" }, 83 { ATA_ATI_IXP700_S1, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP700/800" }, 84 { ATA_ATI_IXP700_S2, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP700/800" }, 85 { ATA_ATI_IXP700_S3, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP700/800" }, 86 { ATA_ATI_IXP700_S4, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP700/800" }, 87 { ATA_ATI_IXP800_S1, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP800" }, 88 { ATA_ATI_IXP800_S2, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP800" }, 89 { 0, 0, 0, 0, 0, 0}}; 90 91 if (pci_get_vendor(dev) != ATA_ATI_ID) 92 return ENXIO; 93 94 if (!(ctlr->chip = ata_match_chip(dev, ids))) 95 return ENXIO; 96 97 ata_set_desc(dev); 98 99 switch (ctlr->chip->cfg1) { 100 case ATI_PATA: 101 ctlr->chipinit = ata_ati_chipinit; 102 break; 103 case ATI_SATA: 104 /* 105 * the ATI SATA controller is actually a SiI 3112 controller 106 * cfg values below much match those in ata-siliconimage.c 107 */ 108 ctlr->chip->cfg1 = SII_MEMIO; 109 ctlr->chip->cfg2 = SII_BUG; 110 ctlr->chipinit = ata_sii_chipinit; 111 break; 112 case ATI_AHCI: 113 ctlr->chipinit = ata_ahci_chipinit; 114 break; 115 } 116 return (BUS_PROBE_DEFAULT); 117 } 118 119 static int 120 ata_ati_chipinit(device_t dev) 121 { 122 struct ata_pci_controller *ctlr = device_get_softc(dev); 123 device_t smbdev; 124 int satacfg; 125 126 if (ata_setup_interrupt(dev, ata_generic_intr)) 127 return ENXIO; 128 129 switch (ctlr->chip->chipid) { 130 case ATA_ATI_IXP600: 131 /* IXP600 only has 1 PATA channel */ 132 ctlr->channels = 1; 133 break; 134 case ATA_ATI_IXP700: 135 /* 136 * When "combined mode" is enabled, an additional PATA channel is 137 * emulated with two SATA ports and appears on this device. 138 * This mode can only be detected via SMB controller. 139 */ 140 smbdev = pci_find_device(ATA_ATI_ID, 0x4385); 141 if (smbdev != NULL) { 142 satacfg = pci_read_config(smbdev, 0xad, 1); 143 if (bootverbose) 144 device_printf(dev, "SATA controller %s (%s%s channel)\n", 145 (satacfg & 0x01) == 0 ? "disabled" : "enabled", 146 (satacfg & 0x08) == 0 ? "" : "combined mode, ", 147 (satacfg & 0x10) == 0 ? "primary" : "secondary"); 148 149 /* 150 * If SATA controller is enabled but combined mode is disabled, 151 * we have only one PATA channel. Ignore a non-existent channel. 152 */ 153 if ((satacfg & 0x09) == 0x01) 154 ctlr->ichannels &= ~(1 << ((satacfg & 0x10) >> 4)); 155 } 156 break; 157 } 158 159 ctlr->setmode = ata_ati_setmode; 160 return 0; 161 } 162 163 static int 164 ata_ati_setmode(device_t dev, int target, int mode) 165 { 166 device_t parent = device_get_parent(dev); 167 struct ata_pci_controller *ctlr = device_get_softc(parent); 168 struct ata_channel *ch = device_get_softc(dev); 169 int devno = (ch->unit << 1) + target; 170 int offset = (devno ^ 0x01) << 3; 171 int piomode; 172 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 }; 173 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 }; 174 175 mode = min(mode, ctlr->chip->max_dma); 176 if (mode >= ATA_UDMA0) { 177 /* Set UDMA mode, enable UDMA, set WDMA2/PIO4 */ 178 pci_write_config(parent, 0x56, 179 (pci_read_config(parent, 0x56, 2) & 180 ~(0xf << (devno << 2))) | 181 ((mode & ATA_MODE_MASK) << (devno << 2)), 2); 182 pci_write_config(parent, 0x54, 183 pci_read_config(parent, 0x54, 1) | 184 (0x01 << devno), 1); 185 pci_write_config(parent, 0x44, 186 (pci_read_config(parent, 0x44, 4) & 187 ~(0xff << offset)) | 188 (dmatimings[2] << offset), 4); 189 piomode = ATA_PIO4; 190 } else if (mode >= ATA_WDMA0) { 191 /* Disable UDMA, set WDMA mode and timings, calculate PIO. */ 192 pci_write_config(parent, 0x54, 193 pci_read_config(parent, 0x54, 1) & 194 ~(0x01 << devno), 1); 195 pci_write_config(parent, 0x44, 196 (pci_read_config(parent, 0x44, 4) & 197 ~(0xff << offset)) | 198 (dmatimings[mode & ATA_MODE_MASK] << offset), 4); 199 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 : 200 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4; 201 } else { 202 /* Disable UDMA, set requested PIO. */ 203 pci_write_config(parent, 0x54, 204 pci_read_config(parent, 0x54, 1) & 205 ~(0x01 << devno), 1); 206 piomode = mode; 207 } 208 /* Set PIO mode and timings, calculated above. */ 209 pci_write_config(parent, 0x4a, 210 (pci_read_config(parent, 0x4a, 2) & 211 ~(0xf << (devno << 2))) | 212 ((piomode - ATA_PIO0) << (devno<<2)),2); 213 pci_write_config(parent, 0x40, 214 (pci_read_config(parent, 0x40, 4) & 215 ~(0xff << offset)) | 216 (piotimings[ata_mode2idx(piomode)] << offset), 4); 217 return (mode); 218 } 219 220 ATA_DECLARE_DRIVER(ata_ati); 221 MODULE_DEPEND(ata_ati, ata_ahci, 1, 1, 1); 222 MODULE_DEPEND(ata_ati, ata_sii, 1, 1, 1); 223