1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification, immediately at the beginning of the file. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/param.h> 30 #include <sys/module.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/ata.h> 34 #include <sys/bus.h> 35 #include <sys/endian.h> 36 #include <sys/malloc.h> 37 #include <sys/lock.h> 38 #include <sys/mutex.h> 39 #include <sys/sema.h> 40 #include <sys/taskqueue.h> 41 #include <vm/uma.h> 42 #include <machine/stdarg.h> 43 #include <machine/resource.h> 44 #include <machine/bus.h> 45 #include <sys/rman.h> 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcireg.h> 48 #include <dev/ata/ata-all.h> 49 #include <dev/ata/ata-pci.h> 50 #include <ata_if.h> 51 52 /* local prototypes */ 53 static int ata_ali_chipinit(device_t dev); 54 static int ata_ali_chipdeinit(device_t dev); 55 static int ata_ali_ch_attach(device_t dev); 56 static int ata_ali_sata_ch_attach(device_t dev); 57 static void ata_ali_reset(device_t dev); 58 static int ata_ali_setmode(device_t dev, int target, int mode); 59 60 /* misc defines */ 61 #define ALI_OLD 0x01 62 #define ALI_NEW 0x02 63 #define ALI_SATA 0x04 64 65 struct ali_sata_resources { 66 struct resource *bars[4]; 67 }; 68 69 /* 70 * Acer Labs Inc (ALI) chipset support functions 71 */ 72 static int 73 ata_ali_probe(device_t dev) 74 { 75 struct ata_pci_controller *ctlr = device_get_softc(dev); 76 static const struct ata_chip_id ids[] = 77 {{ ATA_ALI_5289, 0x00, 2, ALI_SATA, ATA_SA150, "M5289" }, 78 { ATA_ALI_5288, 0x00, 4, ALI_SATA, ATA_SA300, "M5288" }, 79 { ATA_ALI_5287, 0x00, 4, ALI_SATA, ATA_SA150, "M5287" }, 80 { ATA_ALI_5281, 0x00, 2, ALI_SATA, ATA_SA150, "M5281" }, 81 { ATA_ALI_5228, 0xc5, 0, ALI_NEW, ATA_UDMA6, "M5228" }, 82 { ATA_ALI_5229, 0xc5, 0, ALI_NEW, ATA_UDMA6, "M5229" }, 83 { ATA_ALI_5229, 0xc4, 0, ALI_NEW, ATA_UDMA5, "M5229" }, 84 { ATA_ALI_5229, 0xc2, 0, ALI_NEW, ATA_UDMA4, "M5229" }, 85 { ATA_ALI_5229, 0x20, 0, ALI_OLD, ATA_UDMA2, "M5229" }, 86 { ATA_ALI_5229, 0x00, 0, ALI_OLD, ATA_WDMA2, "M5229" }, 87 { 0, 0, 0, 0, 0, 0}}; 88 89 if (pci_get_vendor(dev) != ATA_ACER_LABS_ID) 90 return ENXIO; 91 92 if (!(ctlr->chip = ata_match_chip(dev, ids))) 93 return ENXIO; 94 95 ata_set_desc(dev); 96 ctlr->chipinit = ata_ali_chipinit; 97 ctlr->chipdeinit = ata_ali_chipdeinit; 98 return (BUS_PROBE_LOW_PRIORITY); 99 } 100 101 static int 102 ata_ali_chipinit(device_t dev) 103 { 104 struct ata_pci_controller *ctlr = device_get_softc(dev); 105 struct ali_sata_resources *res; 106 int i, rid; 107 108 if (ata_setup_interrupt(dev, ata_generic_intr)) 109 return ENXIO; 110 111 switch (ctlr->chip->cfg2) { 112 case ALI_SATA: 113 ctlr->channels = ctlr->chip->cfg1; 114 ctlr->ch_attach = ata_ali_sata_ch_attach; 115 ctlr->ch_detach = ata_pci_ch_detach; 116 ctlr->setmode = ata_sata_setmode; 117 ctlr->getrev = ata_sata_getrev; 118 119 /* Allocate resources for later use by channel attach routines. */ 120 res = malloc(sizeof(struct ali_sata_resources), M_ATAPCI, M_WAITOK); 121 for (i = 0; i < 4; i++) { 122 rid = PCIR_BAR(i); 123 res->bars[i] = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 124 RF_ACTIVE); 125 if (res->bars[i] == NULL) { 126 device_printf(dev, "Failed to allocate BAR %d\n", i); 127 for (i--; i >=0; i--) 128 bus_release_resource(dev, SYS_RES_IOPORT, 129 PCIR_BAR(i), res->bars[i]); 130 free(res, M_ATAPCI); 131 return ENXIO; 132 } 133 } 134 ctlr->chipset_data = res; 135 break; 136 137 case ALI_NEW: 138 /* use device interrupt as byte count end */ 139 pci_write_config(dev, 0x4a, pci_read_config(dev, 0x4a, 1) | 0x20, 1); 140 141 /* enable cable detection and UDMA support on revisions < 0xc7 */ 142 if (ctlr->chip->chiprev < 0xc7) 143 pci_write_config(dev, 0x4b, pci_read_config(dev, 0x4b, 1) | 144 0x09, 1); 145 146 /* enable ATAPI UDMA mode (even if we are going to do PIO) */ 147 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 148 (ctlr->chip->chiprev >= 0xc7 ? 0x03 : 0x01), 1); 149 150 /* only chips with revision > 0xc4 can do 48bit DMA */ 151 if (ctlr->chip->chiprev <= 0xc4) 152 device_printf(dev, 153 "using PIO transfers above 137GB as workaround for " 154 "48bit DMA access bug, expect reduced performance\n"); 155 ctlr->ch_attach = ata_ali_ch_attach; 156 ctlr->ch_detach = ata_pci_ch_detach; 157 ctlr->reset = ata_ali_reset; 158 ctlr->setmode = ata_ali_setmode; 159 break; 160 161 case ALI_OLD: 162 /* deactivate the ATAPI FIFO and enable ATAPI UDMA */ 163 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x03, 1); 164 ctlr->setmode = ata_ali_setmode; 165 break; 166 } 167 return 0; 168 } 169 170 static int 171 ata_ali_chipdeinit(device_t dev) 172 { 173 struct ata_pci_controller *ctlr = device_get_softc(dev); 174 struct ali_sata_resources *res; 175 int i; 176 177 if (ctlr->chip->cfg2 == ALI_SATA) { 178 res = ctlr->chipset_data; 179 for (i = 0; i < 4; i++) { 180 if (res->bars[i] != NULL) { 181 bus_release_resource(dev, SYS_RES_IOPORT, 182 PCIR_BAR(i), res->bars[i]); 183 } 184 } 185 free(res, M_ATAPCI); 186 ctlr->chipset_data = NULL; 187 } 188 return (0); 189 } 190 191 static int 192 ata_ali_ch_attach(device_t dev) 193 { 194 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 195 struct ata_channel *ch = device_get_softc(dev); 196 197 /* setup the usual register normal pci style */ 198 if (ata_pci_ch_attach(dev)) 199 return ENXIO; 200 201 if (ctlr->chip->cfg2 & ALI_NEW && ctlr->chip->chiprev < 0xc7) 202 ch->flags |= ATA_CHECKS_CABLE; 203 /* older chips can't do 48bit DMA transfers */ 204 if (ctlr->chip->chiprev <= 0xc4) { 205 ch->flags |= ATA_NO_48BIT_DMA; 206 if (ch->dma.max_iosize > 256 * 512) 207 ch->dma.max_iosize = 256 * 512; 208 } 209 if (ctlr->chip->cfg2 & ALI_NEW) 210 ch->flags |= ATA_NO_ATAPI_DMA; 211 212 return 0; 213 } 214 215 static int 216 ata_ali_sata_ch_attach(device_t dev) 217 { 218 device_t parent = device_get_parent(dev); 219 struct ata_pci_controller *ctlr = device_get_softc(parent); 220 struct ata_channel *ch = device_get_softc(dev); 221 struct ali_sata_resources *res; 222 struct resource *io = NULL, *ctlio = NULL; 223 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2); 224 int i; 225 226 res = ctlr->chipset_data; 227 if (unit01) { 228 io = res->bars[2]; 229 ctlio = res->bars[3]; 230 } else { 231 io = res->bars[0]; 232 ctlio = res->bars[1]; 233 } 234 ata_pci_dmainit(dev); 235 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) { 236 ch->r_io[i].res = io; 237 ch->r_io[i].offset = i + (unit10 ? 8 : 0); 238 } 239 ch->r_io[ATA_CONTROL].res = ctlio; 240 ch->r_io[ATA_CONTROL].offset = 2 + (unit10 ? 4 : 0); 241 ch->r_io[ATA_IDX_ADDR].res = io; 242 ata_default_registers(dev); 243 if (ctlr->r_res1) { 244 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) { 245 ch->r_io[i].res = ctlr->r_res1; 246 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE); 247 } 248 } 249 ch->flags |= ATA_NO_SLAVE; 250 ch->flags |= ATA_SATA; 251 252 /* XXX SOS PHY handling awkward in ALI chip not supported yet */ 253 ata_pci_hw(dev); 254 return 0; 255 } 256 257 static void 258 ata_ali_reset(device_t dev) 259 { 260 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 261 struct ata_channel *ch = device_get_softc(dev); 262 device_t *children; 263 int nchildren, i; 264 265 ata_generic_reset(dev); 266 267 /* 268 * workaround for datacorruption bug found on at least SUN Blade-100 269 * find the ISA function on the southbridge and disable then enable 270 * the ATA channel tristate buffer 271 */ 272 if (ctlr->chip->chiprev == 0xc3 || ctlr->chip->chiprev == 0xc2) { 273 if (!device_get_children(GRANDPARENT(dev), &children, &nchildren)) { 274 for (i = 0; i < nchildren; i++) { 275 if (pci_get_devid(children[i]) == ATA_ALI_1533) { 276 pci_write_config(children[i], 0x58, 277 pci_read_config(children[i], 0x58, 1) & 278 ~(0x04 << ch->unit), 1); 279 pci_write_config(children[i], 0x58, 280 pci_read_config(children[i], 0x58, 1) | 281 (0x04 << ch->unit), 1); 282 break; 283 } 284 } 285 free(children, M_TEMP); 286 } 287 } 288 } 289 290 static int 291 ata_ali_setmode(device_t dev, int target, int mode) 292 { 293 device_t parent = device_get_parent(dev); 294 struct ata_pci_controller *ctlr = device_get_softc(parent); 295 struct ata_channel *ch = device_get_softc(dev); 296 int devno = (ch->unit << 1) + target; 297 int piomode; 298 static const uint32_t piotimings[] = 299 { 0x006d0003, 0x00580002, 0x00440001, 0x00330001, 300 0x00310001, 0x006d0003, 0x00330001, 0x00310001 }; 301 static const uint8_t udma[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f, 302 0x0d}; 303 uint32_t word54; 304 305 mode = min(mode, ctlr->chip->max_dma); 306 307 if (ctlr->chip->cfg2 & ALI_NEW && ctlr->chip->chiprev < 0xc7) { 308 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 309 pci_read_config(parent, 0x4a, 1) & (1 << ch->unit)) { 310 ata_print_cable(dev, "controller"); 311 mode = ATA_UDMA2; 312 } 313 } 314 if (ctlr->chip->cfg2 & ALI_OLD) { 315 /* doesn't support ATAPI DMA on write */ 316 ch->flags |= ATA_ATAPI_DMA_RO; 317 if (ch->devices & ATA_ATAPI_MASTER && 318 ch->devices & ATA_ATAPI_SLAVE) { 319 /* doesn't support ATAPI DMA on two ATAPI devices */ 320 device_printf(dev, "two atapi devices on this channel," 321 " no DMA\n"); 322 mode = min(mode, ATA_PIO_MAX); 323 } 324 } 325 /* Set UDMA mode */ 326 word54 = pci_read_config(parent, 0x54, 4); 327 if (mode >= ATA_UDMA0) { 328 word54 &= ~(0x000f000f << (devno << 2)); 329 word54 |= (((udma[mode&ATA_MODE_MASK]<<16)|0x05)<<(devno<<2)); 330 piomode = ATA_PIO4; 331 } 332 else { 333 word54 &= ~(0x0008000f << (devno << 2)); 334 piomode = mode; 335 } 336 pci_write_config(parent, 0x54, word54, 4); 337 /* Set PIO/WDMA mode */ 338 pci_write_config(parent, 0x58 + (ch->unit << 2), 339 piotimings[ata_mode2idx(piomode)], 4); 340 return (mode); 341 } 342 343 ATA_DECLARE_DRIVER(ata_ali); 344