1 /*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ata.h" 31 #include <sys/param.h> 32 #include <sys/module.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/ata.h> 36 #include <sys/bus.h> 37 #include <sys/endian.h> 38 #include <sys/malloc.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/sema.h> 42 #include <sys/taskqueue.h> 43 #include <vm/uma.h> 44 #include <machine/stdarg.h> 45 #include <machine/resource.h> 46 #include <machine/bus.h> 47 #include <sys/rman.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/ata/ata-all.h> 51 #include <dev/ata/ata-pci.h> 52 #include <ata_if.h> 53 54 /* local prototypes */ 55 static int ata_ali_chipinit(device_t dev); 56 static int ata_ali_ch_attach(device_t dev); 57 static int ata_ali_sata_ch_attach(device_t dev); 58 static void ata_ali_reset(device_t dev); 59 static int ata_ali_setmode(device_t dev, int target, int mode); 60 61 /* misc defines */ 62 #define ALI_OLD 0x01 63 #define ALI_NEW 0x02 64 #define ALI_SATA 0x04 65 66 struct ali_sata_resources { 67 struct resource *bars[4]; 68 }; 69 70 /* 71 * Acer Labs Inc (ALI) chipset support functions 72 */ 73 static int 74 ata_ali_probe(device_t dev) 75 { 76 struct ata_pci_controller *ctlr = device_get_softc(dev); 77 static struct ata_chip_id ids[] = 78 {{ ATA_ALI_5289, 0x00, 2, ALI_SATA, ATA_SA150, "M5289" }, 79 { ATA_ALI_5288, 0x00, 4, ALI_SATA, ATA_SA300, "M5288" }, 80 { ATA_ALI_5287, 0x00, 4, ALI_SATA, ATA_SA150, "M5287" }, 81 { ATA_ALI_5281, 0x00, 2, ALI_SATA, ATA_SA150, "M5281" }, 82 { ATA_ALI_5229, 0xc5, 0, ALI_NEW, ATA_UDMA6, "M5229" }, 83 { ATA_ALI_5229, 0xc4, 0, ALI_NEW, ATA_UDMA5, "M5229" }, 84 { ATA_ALI_5229, 0xc2, 0, ALI_NEW, ATA_UDMA4, "M5229" }, 85 { ATA_ALI_5229, 0x20, 0, ALI_OLD, ATA_UDMA2, "M5229" }, 86 { ATA_ALI_5229, 0x00, 0, ALI_OLD, ATA_WDMA2, "M5229" }, 87 { 0, 0, 0, 0, 0, 0}}; 88 89 if (pci_get_vendor(dev) != ATA_ACER_LABS_ID) 90 return ENXIO; 91 92 if (!(ctlr->chip = ata_match_chip(dev, ids))) 93 return ENXIO; 94 95 ata_set_desc(dev); 96 ctlr->chipinit = ata_ali_chipinit; 97 return (BUS_PROBE_DEFAULT); 98 } 99 100 static int 101 ata_ali_chipinit(device_t dev) 102 { 103 struct ata_pci_controller *ctlr = device_get_softc(dev); 104 struct ali_sata_resources *res; 105 int i, rid; 106 107 if (ata_setup_interrupt(dev, ata_generic_intr)) 108 return ENXIO; 109 110 switch (ctlr->chip->cfg2) { 111 case ALI_SATA: 112 ctlr->channels = ctlr->chip->cfg1; 113 ctlr->ch_attach = ata_ali_sata_ch_attach; 114 ctlr->ch_detach = ata_pci_ch_detach; 115 ctlr->setmode = ata_sata_setmode; 116 ctlr->getrev = ata_sata_getrev; 117 118 /* AHCI mode is correctly supported only on the ALi 5288. */ 119 if ((ctlr->chip->chipid == ATA_ALI_5288) && 120 (ata_ahci_chipinit(dev) != ENXIO)) 121 return 0; 122 123 /* Allocate resources for later use by channel attach routines. */ 124 res = malloc(sizeof(struct ali_sata_resources), M_TEMP, M_WAITOK); 125 for (i = 0; i < 4; i++) { 126 rid = PCIR_BAR(i); 127 res->bars[i] = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 128 RF_ACTIVE); 129 if (res->bars[i] == NULL) { 130 device_printf(dev, "Failed to allocate BAR %d\n", i); 131 for (i--; i >=0; i--) 132 bus_release_resource(dev, SYS_RES_IOPORT, 133 PCIR_BAR(i), res->bars[i]); 134 free(res, M_TEMP); 135 } 136 } 137 ctlr->chipset_data = res; 138 break; 139 140 case ALI_NEW: 141 /* use device interrupt as byte count end */ 142 pci_write_config(dev, 0x4a, pci_read_config(dev, 0x4a, 1) | 0x20, 1); 143 144 /* enable cable detection and UDMA support on revisions < 0xc7 */ 145 if (ctlr->chip->chiprev < 0xc7) 146 pci_write_config(dev, 0x4b, pci_read_config(dev, 0x4b, 1) | 147 0x09, 1); 148 149 /* enable ATAPI UDMA mode (even if we are going to do PIO) */ 150 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 151 (ctlr->chip->chiprev >= 0xc7 ? 0x03 : 0x01), 1); 152 153 /* only chips with revision > 0xc4 can do 48bit DMA */ 154 if (ctlr->chip->chiprev <= 0xc4) 155 device_printf(dev, 156 "using PIO transfers above 137GB as workaround for " 157 "48bit DMA access bug, expect reduced performance\n"); 158 ctlr->ch_attach = ata_ali_ch_attach; 159 ctlr->ch_detach = ata_pci_ch_detach; 160 ctlr->reset = ata_ali_reset; 161 ctlr->setmode = ata_ali_setmode; 162 break; 163 164 case ALI_OLD: 165 /* deactivate the ATAPI FIFO and enable ATAPI UDMA */ 166 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x03, 1); 167 ctlr->setmode = ata_ali_setmode; 168 break; 169 } 170 return 0; 171 } 172 173 static int 174 ata_ali_ch_attach(device_t dev) 175 { 176 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 177 struct ata_channel *ch = device_get_softc(dev); 178 179 /* setup the usual register normal pci style */ 180 if (ata_pci_ch_attach(dev)) 181 return ENXIO; 182 183 if (ctlr->chip->cfg2 & ALI_NEW && ctlr->chip->chiprev < 0xc7) 184 ch->flags |= ATA_CHECKS_CABLE; 185 /* older chips can't do 48bit DMA transfers */ 186 if (ctlr->chip->chiprev <= 0xc4) 187 ch->flags |= ATA_NO_48BIT_DMA; 188 189 return 0; 190 } 191 192 static int 193 ata_ali_sata_ch_attach(device_t dev) 194 { 195 device_t parent = device_get_parent(dev); 196 struct ata_pci_controller *ctlr = device_get_softc(parent); 197 struct ata_channel *ch = device_get_softc(dev); 198 struct ali_sata_resources *res; 199 struct resource *io = NULL, *ctlio = NULL; 200 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2); 201 int i; 202 203 res = ctlr->chipset_data; 204 if (unit01) { 205 io = res->bars[2]; 206 ctlio = res->bars[3]; 207 } else { 208 io = res->bars[0]; 209 ctlio = res->bars[1]; 210 } 211 212 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) { 213 ch->r_io[i].res = io; 214 ch->r_io[i].offset = i + (unit10 ? 8 : 0); 215 } 216 ch->r_io[ATA_CONTROL].res = ctlio; 217 ch->r_io[ATA_CONTROL].offset = 2 + (unit10 ? 4 : 0); 218 ch->r_io[ATA_IDX_ADDR].res = io; 219 ata_default_registers(dev); 220 if (ctlr->r_res1) { 221 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) { 222 ch->r_io[i].res = ctlr->r_res1; 223 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE); 224 } 225 } 226 ch->flags |= ATA_NO_SLAVE; 227 ch->flags |= ATA_SATA; 228 229 /* XXX SOS PHY handling awkward in ALI chip not supported yet */ 230 ata_pci_hw(dev); 231 return 0; 232 } 233 234 static void 235 ata_ali_reset(device_t dev) 236 { 237 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 238 struct ata_channel *ch = device_get_softc(dev); 239 device_t *children; 240 int nchildren, i; 241 242 ata_generic_reset(dev); 243 244 /* 245 * workaround for datacorruption bug found on at least SUN Blade-100 246 * find the ISA function on the southbridge and disable then enable 247 * the ATA channel tristate buffer 248 */ 249 if (ctlr->chip->chiprev == 0xc3 || ctlr->chip->chiprev == 0xc2) { 250 if (!device_get_children(GRANDPARENT(dev), &children, &nchildren)) { 251 for (i = 0; i < nchildren; i++) { 252 if (pci_get_devid(children[i]) == ATA_ALI_1533) { 253 pci_write_config(children[i], 0x58, 254 pci_read_config(children[i], 0x58, 1) & 255 ~(0x04 << ch->unit), 1); 256 pci_write_config(children[i], 0x58, 257 pci_read_config(children[i], 0x58, 1) | 258 (0x04 << ch->unit), 1); 259 break; 260 } 261 } 262 free(children, M_TEMP); 263 } 264 } 265 } 266 267 static int 268 ata_ali_setmode(device_t dev, int target, int mode) 269 { 270 device_t parent = device_get_parent(dev); 271 struct ata_pci_controller *ctlr = device_get_softc(parent); 272 struct ata_channel *ch = device_get_softc(dev); 273 int devno = (ch->unit << 1) + target; 274 int piomode; 275 u_int32_t piotimings[] = 276 { 0x006d0003, 0x00580002, 0x00440001, 0x00330001, 277 0x00310001, 0x006d0003, 0x00330001, 0x00310001 }; 278 u_int8_t udma[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f, 0x0d}; 279 u_int32_t word54; 280 281 mode = min(mode, ctlr->chip->max_dma); 282 283 if (ctlr->chip->cfg2 & ALI_NEW && ctlr->chip->chiprev < 0xc7) { 284 if (mode > ATA_UDMA2 && 285 pci_read_config(parent, 0x4a, 1) & (1 << ch->unit)) { 286 ata_print_cable(dev, "controller"); 287 mode = ATA_UDMA2; 288 } 289 } 290 if (ctlr->chip->cfg2 & ALI_OLD) { 291 /* doesn't support ATAPI DMA on write */ 292 ch->flags |= ATA_ATAPI_DMA_RO; 293 if (ch->devices & ATA_ATAPI_MASTER && 294 ch->devices & ATA_ATAPI_SLAVE) { 295 /* doesn't support ATAPI DMA on two ATAPI devices */ 296 device_printf(dev, "two atapi devices on this channel," 297 " no DMA\n"); 298 mode = min(mode, ATA_PIO_MAX); 299 } 300 } 301 /* Set UDMA mode */ 302 word54 = pci_read_config(parent, 0x54, 4); 303 if (mode >= ATA_UDMA0) { 304 word54 &= ~(0x000f000f << (devno << 2)); 305 word54 |= (((udma[mode&ATA_MODE_MASK]<<16)|0x05)<<(devno<<2)); 306 piomode = ATA_PIO4; 307 } 308 else { 309 word54 &= ~(0x0008000f << (devno << 2)); 310 piomode = mode; 311 } 312 pci_write_config(parent, 0x54, word54, 4); 313 /* Set PIO/WDMA mode */ 314 pci_write_config(parent, 0x58 + (ch->unit << 2), 315 piotimings[ata_mode2idx(piomode)], 4); 316 return (mode); 317 } 318 319 ATA_DECLARE_DRIVER(ata_ali); 320 MODULE_DEPEND(ata_ali, ata_ahci, 1, 1, 1); 321