1 /*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ata.h" 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/ata.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/malloc.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 #include <sys/sema.h> 41 #include <sys/taskqueue.h> 42 #include <vm/uma.h> 43 #include <machine/stdarg.h> 44 #include <machine/resource.h> 45 #include <machine/bus.h> 46 #include <sys/rman.h> 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcireg.h> 49 #include <dev/ata/ata-all.h> 50 #include <dev/ata/ata-pci.h> 51 #include <ata_if.h> 52 53 void 54 ata_sata_phy_check_events(device_t dev) 55 { 56 struct ata_channel *ch = device_get_softc(dev); 57 u_int32_t error = ATA_IDX_INL(ch, ATA_SERROR); 58 59 /* clear error bits/interrupt */ 60 ATA_IDX_OUTL(ch, ATA_SERROR, error); 61 62 /* if we have a connection event deal with it */ 63 if (error & ATA_SE_PHY_CHANGED) { 64 if (bootverbose) { 65 u_int32_t status = ATA_IDX_INL(ch, ATA_SSTATUS); 66 if (((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1) || 67 ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2)) { 68 device_printf(dev, "CONNECT requested\n"); 69 } else 70 device_printf(dev, "DISCONNECT requested\n"); 71 } 72 taskqueue_enqueue(taskqueue_thread, &ch->conntask); 73 } 74 } 75 76 int 77 ata_sata_scr_read(struct ata_channel *ch, int port, int reg, uint32_t *val) 78 { 79 int r; 80 81 if (port < 0) { 82 *val = ATA_IDX_INL(ch, reg); 83 return (0); 84 } else { 85 switch (reg) { 86 case ATA_SSTATUS: 87 r = 0; 88 break; 89 case ATA_SERROR: 90 r = 1; 91 break; 92 case ATA_SCONTROL: 93 r = 2; 94 break; 95 default: 96 return (EINVAL); 97 } 98 return (ch->hw.pm_read(ch->dev, port, r, val)); 99 } 100 } 101 102 int 103 ata_sata_scr_write(struct ata_channel *ch, int port, int reg, uint32_t val) 104 { 105 int r; 106 107 if (port < 0) { 108 ATA_IDX_OUTL(ch, reg, val); 109 return (0); 110 } else { 111 switch (reg) { 112 case ATA_SERROR: 113 r = 1; 114 break; 115 case ATA_SCONTROL: 116 r = 2; 117 break; 118 default: 119 return (EINVAL); 120 } 121 return (ch->hw.pm_write(ch->dev, port, r, val)); 122 } 123 } 124 125 static int 126 ata_sata_connect(struct ata_channel *ch, int port) 127 { 128 u_int32_t status; 129 int timeout; 130 131 /* wait up to 1 second for "connect well" */ 132 for (timeout = 0; timeout < 100 ; timeout++) { 133 if (ata_sata_scr_read(ch, port, ATA_SSTATUS, &status)) 134 return (0); 135 if ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1 || 136 (status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2) 137 break; 138 ata_udelay(10000); 139 } 140 if (timeout >= 100) { 141 if (bootverbose) { 142 if (port < 0) { 143 device_printf(ch->dev, "SATA connect timeout status=%08x\n", 144 status); 145 } else { 146 device_printf(ch->dev, "p%d: SATA connect timeout status=%08x\n", 147 port, status); 148 } 149 } 150 return 0; 151 } 152 if (bootverbose) { 153 if (port < 0) { 154 device_printf(ch->dev, "SATA connect time=%dms status=%08x\n", 155 timeout * 10, status); 156 } else { 157 device_printf(ch->dev, "p%d: SATA connect time=%dms status=%08x\n", 158 port, timeout * 10, status); 159 } 160 } 161 162 /* clear SATA error register */ 163 ata_sata_scr_write(ch, port, ATA_SERROR, 0xffffffff); 164 165 return 1; 166 } 167 168 int 169 ata_sata_phy_reset(device_t dev, int port, int quick) 170 { 171 struct ata_channel *ch = device_get_softc(dev); 172 int loop, retry; 173 uint32_t val; 174 175 if (quick) { 176 if (ata_sata_scr_read(ch, port, ATA_SCONTROL, &val)) 177 return (0); 178 if ((val & ATA_SC_DET_MASK) == ATA_SC_DET_IDLE) 179 return ata_sata_connect(ch, port); 180 } 181 182 if (bootverbose) { 183 if (port < 0) { 184 device_printf(dev, "hardware reset ...\n"); 185 } else { 186 device_printf(dev, "p%d: hardware reset ...\n", port); 187 } 188 } 189 for (retry = 0; retry < 10; retry++) { 190 for (loop = 0; loop < 10; loop++) { 191 if (ata_sata_scr_write(ch, port, ATA_SCONTROL, ATA_SC_DET_RESET)) 192 return (0); 193 ata_udelay(100); 194 if (ata_sata_scr_read(ch, port, ATA_SCONTROL, &val)) 195 return (0); 196 if ((val & ATA_SC_DET_MASK) == ATA_SC_DET_RESET) 197 break; 198 } 199 ata_udelay(5000); 200 for (loop = 0; loop < 10; loop++) { 201 if (ata_sata_scr_write(ch, port, ATA_SCONTROL, 202 ATA_SC_DET_IDLE | 203 ATA_SC_IPM_DIS_PARTIAL | 204 ATA_SC_IPM_DIS_SLUMBER)) 205 return (0); 206 ata_udelay(100); 207 if (ata_sata_scr_read(ch, port, ATA_SCONTROL, &val)) 208 return (0); 209 if ((val & ATA_SC_DET_MASK) == 0) 210 return ata_sata_connect(ch, port); 211 } 212 } 213 return 0; 214 } 215 216 void 217 ata_sata_setmode(device_t dev, int mode) 218 { 219 struct ata_device *atadev = device_get_softc(dev); 220 221 /* 222 * if we detect that the device isn't a real SATA device we limit 223 * the transfer mode to UDMA5/ATA100. 224 * this works around the problems some devices has with the 225 * Marvell 88SX8030 SATA->PATA converters and UDMA6/ATA133. 226 */ 227 if (atadev->param.satacapabilities != 0x0000 && 228 atadev->param.satacapabilities != 0xffff) { 229 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 230 231 /* on some drives we need to set the transfer mode */ 232 ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, 233 ata_limit_mode(dev, mode, ATA_UDMA6)); 234 235 /* query SATA STATUS for the speed */ 236 if (ch->r_io[ATA_SSTATUS].res && 237 ((ATA_IDX_INL(ch, ATA_SSTATUS) & ATA_SS_CONWELL_MASK) == 238 ATA_SS_CONWELL_GEN2)) 239 atadev->mode = ATA_SA300; 240 else 241 atadev->mode = ATA_SA150; 242 } 243 else { 244 mode = ata_limit_mode(dev, mode, ATA_UDMA5); 245 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) 246 atadev->mode = mode; 247 } 248 } 249 250 int 251 ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis) 252 { 253 struct ata_device *atadev = device_get_softc(request->dev); 254 255 if (request->flags & ATA_R_ATAPI) { 256 fis[0] = 0x27; /* host to device */ 257 fis[1] = 0x80 | (atadev->unit & 0x0f); 258 fis[2] = ATA_PACKET_CMD; 259 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) 260 fis[3] = ATA_F_DMA; 261 else { 262 fis[5] = request->transfersize; 263 fis[6] = request->transfersize >> 8; 264 } 265 fis[7] = ATA_D_LBA; 266 fis[15] = ATA_A_4BIT; 267 return 20; 268 } 269 else { 270 ata_modify_if_48bit(request); 271 fis[0] = 0x27; /* host to device */ 272 fis[1] = 0x80 | (atadev->unit & 0x0f); 273 fis[2] = request->u.ata.command; 274 fis[3] = request->u.ata.feature; 275 fis[4] = request->u.ata.lba; 276 fis[5] = request->u.ata.lba >> 8; 277 fis[6] = request->u.ata.lba >> 16; 278 fis[7] = ATA_D_LBA; 279 if (!(atadev->flags & ATA_D_48BIT_ACTIVE)) 280 fis[7] |= (ATA_D_IBM | (request->u.ata.lba >> 24 & 0x0f)); 281 fis[8] = request->u.ata.lba >> 24; 282 fis[9] = request->u.ata.lba >> 32; 283 fis[10] = request->u.ata.lba >> 40; 284 fis[11] = request->u.ata.feature >> 8; 285 fis[12] = request->u.ata.count; 286 fis[13] = request->u.ata.count >> 8; 287 fis[15] = ATA_A_4BIT; 288 return 20; 289 } 290 return 0; 291 } 292 293 void 294 ata_pm_identify(device_t dev) 295 { 296 struct ata_channel *ch = device_get_softc(dev); 297 u_int32_t pm_chipid, pm_revision, pm_ports; 298 int port; 299 300 /* get PM vendor & product data */ 301 if (ch->hw.pm_read(dev, ATA_PM, 0, &pm_chipid)) { 302 device_printf(dev, "error getting PM vendor data\n"); 303 return; 304 } 305 306 /* get PM revision data */ 307 if (ch->hw.pm_read(dev, ATA_PM, 1, &pm_revision)) { 308 device_printf(dev, "error getting PM revison data\n"); 309 return; 310 } 311 312 /* get number of HW ports on the PM */ 313 if (ch->hw.pm_read(dev, ATA_PM, 2, &pm_ports)) { 314 device_printf(dev, "error getting PM port info\n"); 315 return; 316 } 317 pm_ports &= 0x0000000f; 318 319 /* chip specific quirks */ 320 switch (pm_chipid) { 321 case 0x37261095: 322 /* This PM declares 6 ports, while only 5 of them are real. 323 * Port 5 is enclosure management bridge port, which has implementation 324 * problems, causing probe faults. Hide it for now. */ 325 device_printf(dev, "SiI 3726 (rev=%x) Port Multiplier with %d (5) ports\n", 326 pm_revision, pm_ports); 327 pm_ports = 5; 328 break; 329 330 case 0x47261095: 331 /* This PM declares 7 ports, while only 5 of them are real. 332 * Port 5 is some fake "Config Disk" with 640 sectors size, 333 * port 6 is enclosure management bridge port. 334 * Both fake ports has implementation problems, causing 335 * probe faults. Hide them for now. */ 336 device_printf(dev, "SiI 4726 (rev=%x) Port Multiplier with %d (5) ports\n", 337 pm_revision, pm_ports); 338 pm_ports = 5; 339 break; 340 341 default: 342 device_printf(dev, "Port Multiplier (id=%08x rev=%x) with %d ports\n", 343 pm_chipid, pm_revision, pm_ports); 344 } 345 346 /* realloc space for needed DMA slots */ 347 ch->dma.dma_slots = pm_ports; 348 349 /* reset all ports and register if anything connected */ 350 for (port=0; port < pm_ports; port++) { 351 u_int32_t signature; 352 353 if (!ata_sata_phy_reset(dev, port, 1)) 354 continue; 355 356 /* 357 * XXX: I have no idea how to properly wait for PMP port hardreset 358 * completion. Without this delay soft reset does not completes 359 * successfully. 360 */ 361 DELAY(1000000); 362 363 signature = ch->hw.softreset(dev, port); 364 365 if (bootverbose) 366 device_printf(dev, "p%d: SIGNATURE=%08x\n", port, signature); 367 368 /* figure out whats there */ 369 switch (signature >> 16) { 370 case 0x0000: 371 ch->devices |= (ATA_ATA_MASTER << port); 372 continue; 373 case 0xeb14: 374 ch->devices |= (ATA_ATAPI_MASTER << port); 375 continue; 376 } 377 } 378 } 379