1 /*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ata.h" 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/ata.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/malloc.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 #include <sys/sema.h> 41 #include <sys/taskqueue.h> 42 #include <vm/uma.h> 43 #include <machine/stdarg.h> 44 #include <machine/resource.h> 45 #include <machine/bus.h> 46 #include <sys/rman.h> 47 #include <dev/ata/ata-all.h> 48 #include <ata_if.h> 49 50 void 51 ata_sata_phy_check_events(device_t dev, int port) 52 { 53 struct ata_channel *ch = device_get_softc(dev); 54 u_int32_t error, status; 55 56 ata_sata_scr_read(ch, port, ATA_SERROR, &error); 57 /* Clear set error bits/interrupt. */ 58 if (error) 59 ata_sata_scr_write(ch, port, ATA_SERROR, error); 60 61 /* if we have a connection event deal with it */ 62 if ((error & ATA_SE_PHY_CHANGED) && (ch->pm_level == 0)) { 63 if (bootverbose) { 64 ata_sata_scr_read(ch, port, ATA_SSTATUS, &status); 65 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 66 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 67 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) { 68 device_printf(dev, "CONNECT requested\n"); 69 } else 70 device_printf(dev, "DISCONNECT requested\n"); 71 } 72 taskqueue_enqueue(taskqueue_thread, &ch->conntask); 73 } 74 } 75 76 int 77 ata_sata_scr_read(struct ata_channel *ch, int port, int reg, uint32_t *val) 78 { 79 80 if (ch->hw.pm_read != NULL) 81 return (ch->hw.pm_read(ch->dev, port, reg, val)); 82 if (ch->r_io[reg].res) { 83 *val = ATA_IDX_INL(ch, reg); 84 return (0); 85 } 86 return (-1); 87 } 88 89 int 90 ata_sata_scr_write(struct ata_channel *ch, int port, int reg, uint32_t val) 91 { 92 93 if (ch->hw.pm_write != NULL) 94 return (ch->hw.pm_write(ch->dev, port, reg, val)); 95 if (ch->r_io[reg].res) { 96 ATA_IDX_OUTL(ch, reg, val); 97 return (0); 98 } 99 return (-1); 100 } 101 102 static int 103 ata_sata_connect(struct ata_channel *ch, int port, int quick) 104 { 105 u_int32_t status; 106 int timeout, t; 107 108 /* wait up to 1 second for "connect well" */ 109 timeout = (quick == 2) ? 0 : 100; 110 t = 0; 111 while (1) { 112 if (ata_sata_scr_read(ch, port, ATA_SSTATUS, &status)) 113 return (0); 114 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 115 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 116 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) 117 break; 118 if (++t > timeout) 119 break; 120 ata_udelay(10000); 121 } 122 if (bootverbose) { 123 if (t > timeout) { 124 if (port < 0) { 125 device_printf(ch->dev, "SATA connect timeout status=%08x\n", 126 status); 127 } else { 128 device_printf(ch->dev, "p%d: SATA connect timeout status=%08x\n", 129 port, status); 130 } 131 } else if (port < 0) { 132 device_printf(ch->dev, "SATA connect time=%dms status=%08x\n", 133 t * 10, status); 134 } else { 135 device_printf(ch->dev, "p%d: SATA connect time=%dms status=%08x\n", 136 port, t * 10, status); 137 } 138 } 139 140 /* clear SATA error register */ 141 ata_sata_scr_write(ch, port, ATA_SERROR, 0xffffffff); 142 143 return ((t > timeout) ? 0 : 1); 144 } 145 146 int 147 ata_sata_phy_reset(device_t dev, int port, int quick) 148 { 149 struct ata_channel *ch = device_get_softc(dev); 150 int loop, retry; 151 uint32_t val; 152 153 if (quick) { 154 if (ata_sata_scr_read(ch, port, ATA_SCONTROL, &val)) 155 return (0); 156 if ((val & ATA_SC_DET_MASK) == ATA_SC_DET_IDLE) { 157 ata_sata_scr_write(ch, port, ATA_SCONTROL, 158 ATA_SC_DET_IDLE | ((ch->pm_level > 0) ? 0 : 159 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER)); 160 return ata_sata_connect(ch, port, quick); 161 } 162 } 163 164 if (bootverbose) { 165 if (port < 0) { 166 device_printf(dev, "hardware reset ...\n"); 167 } else { 168 device_printf(dev, "p%d: hardware reset ...\n", port); 169 } 170 } 171 for (retry = 0; retry < 10; retry++) { 172 for (loop = 0; loop < 10; loop++) { 173 if (ata_sata_scr_write(ch, port, ATA_SCONTROL, ATA_SC_DET_RESET)) 174 return (0); 175 ata_udelay(100); 176 if (ata_sata_scr_read(ch, port, ATA_SCONTROL, &val)) 177 return (0); 178 if ((val & ATA_SC_DET_MASK) == ATA_SC_DET_RESET) 179 break; 180 } 181 ata_udelay(5000); 182 for (loop = 0; loop < 10; loop++) { 183 if (ata_sata_scr_write(ch, port, ATA_SCONTROL, 184 ATA_SC_DET_IDLE | ((ch->pm_level > 0) ? 0 : 185 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))) 186 return (0); 187 ata_udelay(100); 188 if (ata_sata_scr_read(ch, port, ATA_SCONTROL, &val)) 189 return (0); 190 if ((val & ATA_SC_DET_MASK) == 0) 191 return ata_sata_connect(ch, port, 0); 192 } 193 } 194 return 0; 195 } 196 197 int 198 ata_sata_setmode(device_t dev, int target, int mode) 199 { 200 201 return (min(mode, ATA_UDMA5)); 202 } 203 204 int 205 ata_sata_getrev(device_t dev, int target) 206 { 207 struct ata_channel *ch = device_get_softc(dev); 208 209 if (ch->r_io[ATA_SSTATUS].res) 210 return ((ATA_IDX_INL(ch, ATA_SSTATUS) & 0x0f0) >> 4); 211 return (0xff); 212 } 213 214 int 215 ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis) 216 { 217 218 if (request->flags & ATA_R_ATAPI) { 219 fis[0] = 0x27; /* host to device */ 220 fis[1] = 0x80 | (request->unit & 0x0f); 221 fis[2] = ATA_PACKET_CMD; 222 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) 223 fis[3] = ATA_F_DMA; 224 else { 225 fis[5] = request->transfersize; 226 fis[6] = request->transfersize >> 8; 227 } 228 fis[7] = ATA_D_LBA; 229 fis[15] = ATA_A_4BIT; 230 return 20; 231 } 232 else { 233 fis[0] = 0x27; /* host to device */ 234 fis[1] = 0x80 | (request->unit & 0x0f); 235 fis[2] = request->u.ata.command; 236 fis[3] = request->u.ata.feature; 237 fis[4] = request->u.ata.lba; 238 fis[5] = request->u.ata.lba >> 8; 239 fis[6] = request->u.ata.lba >> 16; 240 fis[7] = ATA_D_LBA; 241 if (!(request->flags & ATA_R_48BIT)) 242 fis[7] |= (ATA_D_IBM | (request->u.ata.lba >> 24 & 0x0f)); 243 fis[8] = request->u.ata.lba >> 24; 244 fis[9] = request->u.ata.lba >> 32; 245 fis[10] = request->u.ata.lba >> 40; 246 fis[11] = request->u.ata.feature >> 8; 247 fis[12] = request->u.ata.count; 248 fis[13] = request->u.ata.count >> 8; 249 fis[15] = ATA_A_4BIT; 250 return 20; 251 } 252 return 0; 253 } 254 255 void 256 ata_pm_identify(device_t dev) 257 { 258 struct ata_channel *ch = device_get_softc(dev); 259 u_int32_t pm_chipid, pm_revision, pm_ports; 260 int port; 261 262 /* get PM vendor & product data */ 263 if (ch->hw.pm_read(dev, ATA_PM, 0, &pm_chipid)) { 264 device_printf(dev, "error getting PM vendor data\n"); 265 return; 266 } 267 268 /* get PM revision data */ 269 if (ch->hw.pm_read(dev, ATA_PM, 1, &pm_revision)) { 270 device_printf(dev, "error getting PM revison data\n"); 271 return; 272 } 273 274 /* get number of HW ports on the PM */ 275 if (ch->hw.pm_read(dev, ATA_PM, 2, &pm_ports)) { 276 device_printf(dev, "error getting PM port info\n"); 277 return; 278 } 279 pm_ports &= 0x0000000f; 280 281 /* chip specific quirks */ 282 switch (pm_chipid) { 283 case 0x37261095: 284 /* This PM declares 6 ports, while only 5 of them are real. 285 * Port 5 is enclosure management bridge port, which has implementation 286 * problems, causing probe faults. Hide it for now. */ 287 device_printf(dev, "SiI 3726 (rev=%x) Port Multiplier with %d (5) ports\n", 288 pm_revision, pm_ports); 289 pm_ports = 5; 290 break; 291 292 case 0x47261095: 293 /* This PM declares 7 ports, while only 5 of them are real. 294 * Port 5 is some fake "Config Disk" with 640 sectors size, 295 * port 6 is enclosure management bridge port. 296 * Both fake ports has implementation problems, causing 297 * probe faults. Hide them for now. */ 298 device_printf(dev, "SiI 4726 (rev=%x) Port Multiplier with %d (5) ports\n", 299 pm_revision, pm_ports); 300 pm_ports = 5; 301 break; 302 303 default: 304 device_printf(dev, "Port Multiplier (id=%08x rev=%x) with %d ports\n", 305 pm_chipid, pm_revision, pm_ports); 306 } 307 308 /* reset all ports and register if anything connected */ 309 for (port=0; port < pm_ports; port++) { 310 u_int32_t signature; 311 312 if (!ata_sata_phy_reset(dev, port, 1)) 313 continue; 314 315 /* 316 * XXX: I have no idea how to properly wait for PMP port hardreset 317 * completion. Without this delay soft reset does not completes 318 * successfully. 319 */ 320 DELAY(1000000); 321 322 signature = ch->hw.softreset(dev, port); 323 324 if (bootverbose) 325 device_printf(dev, "p%d: SIGNATURE=%08x\n", port, signature); 326 327 /* figure out whats there */ 328 switch (signature >> 16) { 329 case 0x0000: 330 ch->devices |= (ATA_ATA_MASTER << port); 331 continue; 332 case 0xeb14: 333 ch->devices |= (ATA_ATAPI_MASTER << port); 334 continue; 335 } 336 } 337 } 338