1 /*- 2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ata.h" 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/ata.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/malloc.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 #include <sys/sema.h> 41 #include <sys/taskqueue.h> 42 #include <vm/uma.h> 43 #include <machine/stdarg.h> 44 #include <machine/resource.h> 45 #include <machine/bus.h> 46 #include <sys/rman.h> 47 #include <dev/ata/ata-all.h> 48 #include <ata_if.h> 49 50 void 51 ata_sata_phy_check_events(device_t dev, int port) 52 { 53 struct ata_channel *ch = device_get_softc(dev); 54 u_int32_t error, status; 55 56 ata_sata_scr_read(ch, port, ATA_SERROR, &error); 57 58 /* Check that SError value is sane. */ 59 if (error == 0xffffffff) 60 return; 61 62 /* Clear set error bits/interrupt. */ 63 if (error) 64 ata_sata_scr_write(ch, port, ATA_SERROR, error); 65 66 /* if we have a connection event deal with it */ 67 if ((error & ATA_SE_PHY_CHANGED) && (ch->pm_level == 0)) { 68 if (bootverbose) { 69 ata_sata_scr_read(ch, port, ATA_SSTATUS, &status); 70 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 71 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 72 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) { 73 device_printf(dev, "CONNECT requested\n"); 74 } else 75 device_printf(dev, "DISCONNECT requested\n"); 76 } 77 taskqueue_enqueue(taskqueue_thread, &ch->conntask); 78 } 79 } 80 81 int 82 ata_sata_scr_read(struct ata_channel *ch, int port, int reg, uint32_t *val) 83 { 84 85 if (ch->hw.pm_read != NULL) 86 return (ch->hw.pm_read(ch->dev, port, reg, val)); 87 if (ch->r_io[reg].res) { 88 *val = ATA_IDX_INL(ch, reg); 89 return (0); 90 } 91 return (-1); 92 } 93 94 int 95 ata_sata_scr_write(struct ata_channel *ch, int port, int reg, uint32_t val) 96 { 97 98 if (ch->hw.pm_write != NULL) 99 return (ch->hw.pm_write(ch->dev, port, reg, val)); 100 if (ch->r_io[reg].res) { 101 ATA_IDX_OUTL(ch, reg, val); 102 return (0); 103 } 104 return (-1); 105 } 106 107 static int 108 ata_sata_connect(struct ata_channel *ch, int port, int quick) 109 { 110 u_int32_t status; 111 int timeout, t; 112 113 /* wait up to 1 second for "connect well" */ 114 timeout = (quick == 2) ? 0 : 100; 115 t = 0; 116 while (1) { 117 if (ata_sata_scr_read(ch, port, ATA_SSTATUS, &status)) 118 return (0); 119 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 120 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 121 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) 122 break; 123 if (++t > timeout) 124 break; 125 ata_udelay(10000); 126 } 127 if (bootverbose) { 128 if (t > timeout) { 129 if (port < 0) { 130 device_printf(ch->dev, "SATA connect timeout status=%08x\n", 131 status); 132 } else { 133 device_printf(ch->dev, "p%d: SATA connect timeout status=%08x\n", 134 port, status); 135 } 136 } else if (port < 0) { 137 device_printf(ch->dev, "SATA connect time=%dms status=%08x\n", 138 t * 10, status); 139 } else { 140 device_printf(ch->dev, "p%d: SATA connect time=%dms status=%08x\n", 141 port, t * 10, status); 142 } 143 } 144 145 /* clear SATA error register */ 146 ata_sata_scr_write(ch, port, ATA_SERROR, 0xffffffff); 147 148 return ((t > timeout) ? 0 : 1); 149 } 150 151 int 152 ata_sata_phy_reset(device_t dev, int port, int quick) 153 { 154 struct ata_channel *ch = device_get_softc(dev); 155 int loop, retry; 156 uint32_t val; 157 158 if (quick) { 159 if (ata_sata_scr_read(ch, port, ATA_SCONTROL, &val)) 160 return (0); 161 if ((val & ATA_SC_DET_MASK) == ATA_SC_DET_IDLE) { 162 ata_sata_scr_write(ch, port, ATA_SCONTROL, 163 ATA_SC_DET_IDLE | ((ch->pm_level > 0) ? 0 : 164 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER)); 165 return ata_sata_connect(ch, port, quick); 166 } 167 } 168 169 if (bootverbose) { 170 if (port < 0) { 171 device_printf(dev, "hard reset ...\n"); 172 } else { 173 device_printf(dev, "p%d: hard reset ...\n", port); 174 } 175 } 176 for (retry = 0; retry < 10; retry++) { 177 for (loop = 0; loop < 10; loop++) { 178 if (ata_sata_scr_write(ch, port, ATA_SCONTROL, ATA_SC_DET_RESET)) 179 goto fail; 180 ata_udelay(100); 181 if (ata_sata_scr_read(ch, port, ATA_SCONTROL, &val)) 182 goto fail; 183 if ((val & ATA_SC_DET_MASK) == ATA_SC_DET_RESET) 184 break; 185 } 186 ata_udelay(5000); 187 for (loop = 0; loop < 10; loop++) { 188 if (ata_sata_scr_write(ch, port, ATA_SCONTROL, 189 ATA_SC_DET_IDLE | ((ch->pm_level > 0) ? 0 : 190 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))) 191 goto fail; 192 ata_udelay(100); 193 if (ata_sata_scr_read(ch, port, ATA_SCONTROL, &val)) 194 goto fail; 195 if ((val & ATA_SC_DET_MASK) == 0) 196 return ata_sata_connect(ch, port, 0); 197 } 198 } 199 fail: 200 /* Clear SATA error register. */ 201 ata_sata_scr_write(ch, port, ATA_SERROR, 0xffffffff); 202 203 if (bootverbose) { 204 if (port < 0) { 205 device_printf(dev, "hard reset failed\n"); 206 } else { 207 device_printf(dev, "p%d: hard reset failed\n", port); 208 } 209 } 210 return (0); 211 } 212 213 int 214 ata_sata_setmode(device_t dev, int target, int mode) 215 { 216 217 return (min(mode, ATA_UDMA5)); 218 } 219 220 int 221 ata_sata_getrev(device_t dev, int target) 222 { 223 struct ata_channel *ch = device_get_softc(dev); 224 225 if (ch->r_io[ATA_SSTATUS].res) 226 return ((ATA_IDX_INL(ch, ATA_SSTATUS) & 0x0f0) >> 4); 227 return (0xff); 228 } 229 230 int 231 ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis) 232 { 233 234 if (request->flags & ATA_R_ATAPI) { 235 fis[0] = 0x27; /* host to device */ 236 fis[1] = 0x80 | (request->unit & 0x0f); 237 fis[2] = ATA_PACKET_CMD; 238 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) 239 fis[3] = ATA_F_DMA; 240 else { 241 fis[5] = request->transfersize; 242 fis[6] = request->transfersize >> 8; 243 } 244 fis[7] = ATA_D_LBA; 245 fis[15] = ATA_A_4BIT; 246 return 20; 247 } 248 else { 249 fis[0] = 0x27; /* host to device */ 250 fis[1] = 0x80 | (request->unit & 0x0f); 251 fis[2] = request->u.ata.command; 252 fis[3] = request->u.ata.feature; 253 fis[4] = request->u.ata.lba; 254 fis[5] = request->u.ata.lba >> 8; 255 fis[6] = request->u.ata.lba >> 16; 256 fis[7] = ATA_D_LBA; 257 if (!(request->flags & ATA_R_48BIT)) 258 fis[7] |= (ATA_D_IBM | (request->u.ata.lba >> 24 & 0x0f)); 259 fis[8] = request->u.ata.lba >> 24; 260 fis[9] = request->u.ata.lba >> 32; 261 fis[10] = request->u.ata.lba >> 40; 262 fis[11] = request->u.ata.feature >> 8; 263 fis[12] = request->u.ata.count; 264 fis[13] = request->u.ata.count >> 8; 265 fis[15] = ATA_A_4BIT; 266 return 20; 267 } 268 return 0; 269 } 270 271 void 272 ata_pm_identify(device_t dev) 273 { 274 struct ata_channel *ch = device_get_softc(dev); 275 u_int32_t pm_chipid, pm_revision, pm_ports; 276 int port; 277 278 /* get PM vendor & product data */ 279 if (ch->hw.pm_read(dev, ATA_PM, 0, &pm_chipid)) { 280 device_printf(dev, "error getting PM vendor data\n"); 281 return; 282 } 283 284 /* get PM revision data */ 285 if (ch->hw.pm_read(dev, ATA_PM, 1, &pm_revision)) { 286 device_printf(dev, "error getting PM revison data\n"); 287 return; 288 } 289 290 /* get number of HW ports on the PM */ 291 if (ch->hw.pm_read(dev, ATA_PM, 2, &pm_ports)) { 292 device_printf(dev, "error getting PM port info\n"); 293 return; 294 } 295 pm_ports &= 0x0000000f; 296 297 /* chip specific quirks */ 298 switch (pm_chipid) { 299 case 0x37261095: 300 /* This PM declares 6 ports, while only 5 of them are real. 301 * Port 5 is enclosure management bridge port, which has implementation 302 * problems, causing probe faults. Hide it for now. */ 303 device_printf(dev, "SiI 3726 (rev=%x) Port Multiplier with %d (5) ports\n", 304 pm_revision, pm_ports); 305 pm_ports = 5; 306 break; 307 308 case 0x47261095: 309 /* This PM declares 7 ports, while only 5 of them are real. 310 * Port 5 is some fake "Config Disk" with 640 sectors size, 311 * port 6 is enclosure management bridge port. 312 * Both fake ports has implementation problems, causing 313 * probe faults. Hide them for now. */ 314 device_printf(dev, "SiI 4726 (rev=%x) Port Multiplier with %d (5) ports\n", 315 pm_revision, pm_ports); 316 pm_ports = 5; 317 break; 318 319 default: 320 device_printf(dev, "Port Multiplier (id=%08x rev=%x) with %d ports\n", 321 pm_chipid, pm_revision, pm_ports); 322 } 323 324 /* reset all ports and register if anything connected */ 325 for (port=0; port < pm_ports; port++) { 326 u_int32_t signature; 327 328 if (!ata_sata_phy_reset(dev, port, 1)) 329 continue; 330 331 /* 332 * XXX: I have no idea how to properly wait for PMP port hardreset 333 * completion. Without this delay soft reset does not completes 334 * successfully. 335 */ 336 DELAY(1000000); 337 338 signature = ch->hw.softreset(dev, port); 339 340 if (bootverbose) 341 device_printf(dev, "p%d: SIGNATURE=%08x\n", port, signature); 342 343 /* figure out whats there */ 344 switch (signature >> 16) { 345 case 0x0000: 346 ch->devices |= (ATA_ATA_MASTER << port); 347 continue; 348 case 0xeb14: 349 ch->devices |= (ATA_ATAPI_MASTER << port); 350 continue; 351 } 352 } 353 } 354