xref: /freebsd/sys/dev/ata/ata-sata.c (revision 145992504973bd16cf3518af9ba5ce185fefa82a)
1 /*-
2  * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer,
10  *    without modification, immediately at the beginning of the file.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25  */
26 
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29 
30 #include "opt_ata.h"
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/ata.h>
35 #include <sys/bus.h>
36 #include <sys/endian.h>
37 #include <sys/malloc.h>
38 #include <sys/lock.h>
39 #include <sys/mutex.h>
40 #include <sys/sema.h>
41 #include <sys/taskqueue.h>
42 #include <vm/uma.h>
43 #include <machine/stdarg.h>
44 #include <machine/resource.h>
45 #include <machine/bus.h>
46 #include <sys/rman.h>
47 #include <dev/ata/ata-all.h>
48 #include <ata_if.h>
49 
50 void
51 ata_sata_phy_check_events(device_t dev, int port)
52 {
53     struct ata_channel *ch = device_get_softc(dev);
54     u_int32_t error, status;
55 
56     if (ata_sata_scr_read(ch, port, ATA_SERROR, &error))
57 	return;
58 
59     /* Check that SError value is sane. */
60     if (error == 0xffffffff)
61 	return;
62 
63     /* Clear set error bits/interrupt. */
64     if (error)
65 	ata_sata_scr_write(ch, port, ATA_SERROR, error);
66 
67     /* if we have a connection event deal with it */
68     if ((error & ATA_SE_PHY_CHANGED) && (ch->pm_level == 0)) {
69 	if (bootverbose) {
70 	    if (ata_sata_scr_read(ch, port, ATA_SSTATUS, &status)) {
71 		    device_printf(dev, "PHYRDY change\n");
72 	    } else if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) &&
73 		((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) &&
74 		((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) {
75 		    device_printf(dev, "CONNECT requested\n");
76 	    } else
77 		    device_printf(dev, "DISCONNECT requested\n");
78 	}
79 	taskqueue_enqueue(taskqueue_thread, &ch->conntask);
80     }
81 }
82 
83 int
84 ata_sata_scr_read(struct ata_channel *ch, int port, int reg, uint32_t *val)
85 {
86 
87     if (ch->hw.pm_read != NULL)
88 	return (ch->hw.pm_read(ch->dev, port, reg, val));
89     if (ch->r_io[reg].res) {
90 	*val = ATA_IDX_INL(ch, reg);
91 	return (0);
92     }
93     return (-1);
94 }
95 
96 int
97 ata_sata_scr_write(struct ata_channel *ch, int port, int reg, uint32_t val)
98 {
99 
100     if (ch->hw.pm_write != NULL)
101 	return (ch->hw.pm_write(ch->dev, port, reg, val));
102     if (ch->r_io[reg].res) {
103 	ATA_IDX_OUTL(ch, reg, val);
104 	return (0);
105     }
106     return (-1);
107 }
108 
109 static int
110 ata_sata_connect(struct ata_channel *ch, int port, int quick)
111 {
112     u_int32_t status;
113     int timeout, t;
114 
115     /* wait up to 1 second for "connect well" */
116     timeout = (quick == 2) ? 0 : 100;
117     t = 0;
118     while (1) {
119 	if (ata_sata_scr_read(ch, port, ATA_SSTATUS, &status))
120 	    return (0);
121 	if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) &&
122 	    ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) &&
123 	    ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE))
124 	    break;
125 	if (++t > timeout)
126 	    break;
127 	ata_udelay(10000);
128     }
129     if (bootverbose) {
130 	if (t > timeout) {
131 	    if (port < 0) {
132 		device_printf(ch->dev, "SATA connect timeout status=%08x\n",
133 		    status);
134 	    } else {
135 		device_printf(ch->dev, "p%d: SATA connect timeout status=%08x\n",
136 		    port, status);
137 	    }
138 	} else if (port < 0) {
139 	    device_printf(ch->dev, "SATA connect time=%dms status=%08x\n",
140 		t * 10, status);
141 	} else {
142 	    device_printf(ch->dev, "p%d: SATA connect time=%dms status=%08x\n",
143 		port, t * 10, status);
144 	}
145     }
146 
147     /* clear SATA error register */
148     ata_sata_scr_write(ch, port, ATA_SERROR, 0xffffffff);
149 
150     return ((t > timeout) ? 0 : 1);
151 }
152 
153 int
154 ata_sata_phy_reset(device_t dev, int port, int quick)
155 {
156     struct ata_channel *ch = device_get_softc(dev);
157     int loop, retry, sata_rev;
158     uint32_t val, val1;
159 
160 #ifdef ATA_CAM
161     sata_rev = ch->user[port < 0 ? 0 : port].revision;
162     if (sata_rev > 0)
163 	quick = 0;
164 #else
165     sata_rev = 0;
166 #endif
167 
168     if (quick) {
169 	if (ata_sata_scr_read(ch, port, ATA_SCONTROL, &val))
170 	    return (0);
171 	if ((val & ATA_SC_DET_MASK) == ATA_SC_DET_IDLE) {
172 	    ata_sata_scr_write(ch, port, ATA_SCONTROL,
173 		ATA_SC_DET_IDLE | ((ch->pm_level > 0) ? 0 :
174 		ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER));
175 	    return ata_sata_connect(ch, port, quick);
176 	}
177     }
178 
179     if (bootverbose) {
180 	if (port < 0) {
181 	    device_printf(dev, "hard reset ...\n");
182 	} else {
183 	    device_printf(dev, "p%d: hard reset ...\n", port);
184 	}
185     }
186     if (sata_rev == 1)
187 	val1 = ATA_SC_SPD_SPEED_GEN1;
188     else if (sata_rev == 2)
189 	val1 = ATA_SC_SPD_SPEED_GEN2;
190     else if (sata_rev == 3)
191 	val1 = ATA_SC_SPD_SPEED_GEN3;
192     else
193 	val1 = 0;
194     for (retry = 0; retry < 10; retry++) {
195 	for (loop = 0; loop < 10; loop++) {
196 	    if (ata_sata_scr_write(ch, port, ATA_SCONTROL, ATA_SC_DET_RESET |
197 		    val1 | ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))
198 		goto fail;
199 	    ata_udelay(100);
200 	    if (ata_sata_scr_read(ch, port, ATA_SCONTROL, &val))
201 		goto fail;
202 	    if ((val & ATA_SC_DET_MASK) == ATA_SC_DET_RESET)
203 		break;
204 	}
205 	ata_udelay(5000);
206 	for (loop = 0; loop < 10; loop++) {
207 	    if (ata_sata_scr_write(ch, port, ATA_SCONTROL,
208 		    ATA_SC_DET_IDLE | val1 | ((ch->pm_level > 0) ? 0 :
209 		    ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER)))
210 		goto fail;
211 	    ata_udelay(100);
212 	    if (ata_sata_scr_read(ch, port, ATA_SCONTROL, &val))
213 		goto fail;
214 	    if ((val & ATA_SC_DET_MASK) == 0)
215 		return ata_sata_connect(ch, port, 0);
216 	}
217     }
218 fail:
219     /* Clear SATA error register. */
220     ata_sata_scr_write(ch, port, ATA_SERROR, 0xffffffff);
221 
222     if (bootverbose) {
223 	if (port < 0) {
224 	    device_printf(dev, "hard reset failed\n");
225 	} else {
226 	    device_printf(dev, "p%d: hard reset failed\n", port);
227 	}
228     }
229     return (0);
230 }
231 
232 int
233 ata_sata_setmode(device_t dev, int target, int mode)
234 {
235 
236 	return (min(mode, ATA_UDMA5));
237 }
238 
239 int
240 ata_sata_getrev(device_t dev, int target)
241 {
242 	struct ata_channel *ch = device_get_softc(dev);
243 
244 	if (ch->r_io[ATA_SSTATUS].res)
245 		return ((ATA_IDX_INL(ch, ATA_SSTATUS) & 0x0f0) >> 4);
246 	return (0xff);
247 }
248 
249 int
250 ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis)
251 {
252 
253     if (request->flags & ATA_R_ATAPI) {
254 	fis[0] = 0x27;  		/* host to device */
255 	fis[1] = 0x80 | (request->unit & 0x0f);
256 	fis[2] = ATA_PACKET_CMD;
257 	if (request->flags & (ATA_R_READ | ATA_R_WRITE))
258 	    fis[3] = ATA_F_DMA;
259 	else {
260 	    fis[5] = request->transfersize;
261 	    fis[6] = request->transfersize >> 8;
262 	}
263 	fis[7] = ATA_D_LBA;
264 	fis[15] = ATA_A_4BIT;
265 	return 20;
266     }
267     else {
268 	fis[0] = 0x27;			/* host to device */
269 	fis[1] = 0x80 | (request->unit & 0x0f);
270 	fis[2] = request->u.ata.command;
271 	fis[3] = request->u.ata.feature;
272 	fis[4] = request->u.ata.lba;
273 	fis[5] = request->u.ata.lba >> 8;
274 	fis[6] = request->u.ata.lba >> 16;
275 	fis[7] = ATA_D_LBA;
276 	if (!(request->flags & ATA_R_48BIT))
277 	    fis[7] |= (ATA_D_IBM | (request->u.ata.lba >> 24 & 0x0f));
278 	fis[8] = request->u.ata.lba >> 24;
279 	fis[9] = request->u.ata.lba >> 32;
280 	fis[10] = request->u.ata.lba >> 40;
281 	fis[11] = request->u.ata.feature >> 8;
282 	fis[12] = request->u.ata.count;
283 	fis[13] = request->u.ata.count >> 8;
284 	fis[15] = ATA_A_4BIT;
285 	return 20;
286     }
287     return 0;
288 }
289 
290 void
291 ata_pm_identify(device_t dev)
292 {
293     struct ata_channel *ch = device_get_softc(dev);
294     u_int32_t pm_chipid, pm_revision, pm_ports;
295     int port;
296 
297     /* get PM vendor & product data */
298     if (ch->hw.pm_read(dev, ATA_PM, 0, &pm_chipid)) {
299 	device_printf(dev, "error getting PM vendor data\n");
300 	return;
301     }
302 
303     /* get PM revision data */
304     if (ch->hw.pm_read(dev, ATA_PM, 1, &pm_revision)) {
305 	device_printf(dev, "error getting PM revison data\n");
306 	return;
307     }
308 
309     /* get number of HW ports on the PM */
310     if (ch->hw.pm_read(dev, ATA_PM, 2, &pm_ports)) {
311 	device_printf(dev, "error getting PM port info\n");
312 	return;
313     }
314     pm_ports &= 0x0000000f;
315 
316     /* chip specific quirks */
317     switch (pm_chipid) {
318     case 0x37261095:
319 	/* This PM declares 6 ports, while only 5 of them are real.
320 	 * Port 5 is enclosure management bridge port, which has implementation
321 	 * problems, causing probe faults. Hide it for now. */
322 	device_printf(dev, "SiI 3726 (rev=%x) Port Multiplier with %d (5) ports\n",
323 		      pm_revision, pm_ports);
324 	pm_ports = 5;
325 	break;
326 
327     case 0x47261095:
328 	/* This PM declares 7 ports, while only 5 of them are real.
329 	 * Port 5 is some fake "Config  Disk" with 640 sectors size,
330 	 * port 6 is enclosure management bridge port.
331 	 * Both fake ports has implementation problems, causing
332 	 * probe faults. Hide them for now. */
333 	device_printf(dev, "SiI 4726 (rev=%x) Port Multiplier with %d (5) ports\n",
334 		      pm_revision, pm_ports);
335 	pm_ports = 5;
336 	break;
337 
338     default:
339 	device_printf(dev, "Port Multiplier (id=%08x rev=%x) with %d ports\n",
340 		      pm_chipid, pm_revision, pm_ports);
341     }
342 
343     /* reset all ports and register if anything connected */
344     for (port=0; port < pm_ports; port++) {
345 	u_int32_t signature;
346 
347 	if (!ata_sata_phy_reset(dev, port, 1))
348 	    continue;
349 
350 	/*
351 	 * XXX: I have no idea how to properly wait for PMP port hardreset
352 	 * completion. Without this delay soft reset does not completes
353 	 * successfully.
354 	 */
355 	DELAY(1000000);
356 
357 	signature = ch->hw.softreset(dev, port);
358 
359 	if (bootverbose)
360 	    device_printf(dev, "p%d: SIGNATURE=%08x\n", port, signature);
361 
362 	/* figure out whats there */
363 	switch (signature >> 16) {
364 	case 0x0000:
365 	    ch->devices |= (ATA_ATA_MASTER << port);
366 	    continue;
367 	case 0xeb14:
368 	    ch->devices |= (ATA_ATAPI_MASTER << port);
369 	    continue;
370 	}
371     }
372 }
373