1 /*- 2 * Copyright (c) 1998,1999,2000,2001,2002 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #include "opt_ata.h" 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/module.h> 36 #include <sys/bus.h> 37 #include <sys/malloc.h> 38 #include <machine/stdarg.h> 39 #include <machine/resource.h> 40 #include <machine/bus.h> 41 #ifdef __alpha__ 42 #include <machine/md_var.h> 43 #endif 44 #include <sys/rman.h> 45 #include <pci/pcivar.h> 46 #include <pci/pcireg.h> 47 #include <dev/ata/ata-all.h> 48 49 /* device structures */ 50 struct ata_pci_controller { 51 struct resource *bmio; 52 int bmaddr; 53 struct resource *irq; 54 int irqcnt; 55 }; 56 57 /* misc defines */ 58 #define IOMASK 0xfffffffc 59 #define GRANDPARENT(dev) device_get_parent(device_get_parent(dev)) 60 #define ATA_MASTERDEV(dev) ((pci_get_progif(dev) & 0x80) && \ 61 (pci_get_progif(dev) & 0x05) != 0x05) 62 63 int 64 ata_find_dev(device_t dev, u_int32_t devid, u_int32_t revid) 65 { 66 device_t *children; 67 int nchildren, i; 68 69 if (device_get_children(device_get_parent(dev), &children, &nchildren)) 70 return 0; 71 72 for (i = 0; i < nchildren; i++) { 73 if (pci_get_devid(children[i]) == devid && 74 pci_get_revid(children[i]) >= revid) { 75 free(children, M_TEMP); 76 return 1; 77 } 78 } 79 free(children, M_TEMP); 80 return 0; 81 } 82 83 static void 84 ata_via_southbridge_fixup(device_t dev) 85 { 86 device_t *children; 87 int nchildren, i; 88 89 if (device_get_children(device_get_parent(dev), &children, &nchildren)) 90 return; 91 92 for (i = 0; i < nchildren; i++) { 93 if (pci_get_devid(children[i]) == 0x03051106 || /* VIA VT8363 */ 94 pci_get_devid(children[i]) == 0x03911106 || /* VIA VT8371 */ 95 pci_get_devid(children[i]) == 0x31021106 || /* VIA VT8662 */ 96 pci_get_devid(children[i]) == 0x31121106) { /* VIA VT8361 */ 97 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1); 98 99 if ((reg76 & 0xf0) != 0xd0) { 100 device_printf(dev, 101 "Correcting VIA config for southbridge data corruption bug\n"); 102 pci_write_config(children[i], 0x75, 0x80, 1); 103 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1); 104 } 105 break; 106 } 107 } 108 free(children, M_TEMP); 109 } 110 111 static const char * 112 ata_pci_match(device_t dev) 113 { 114 if (pci_get_class(dev) != PCIC_STORAGE) 115 return NULL; 116 117 switch (pci_get_devid(dev)) { 118 /* supported chipsets */ 119 case 0x12308086: 120 return "Intel PIIX ATA controller"; 121 122 case 0x70108086: 123 return "Intel PIIX3 ATA controller"; 124 125 case 0x71118086: 126 case 0x71998086: 127 case 0x84ca8086: 128 return "Intel PIIX4 ATA33 controller"; 129 130 case 0x24218086: 131 return "Intel ICH0 ATA33 controller"; 132 133 case 0x24118086: 134 case 0x76018086: 135 return "Intel ICH ATA66 controller"; 136 137 case 0x244a8086: 138 case 0x244b8086: 139 return "Intel ICH2 ATA100 controller"; 140 141 case 0x248a8086: 142 case 0x248b8086: 143 return "Intel ICH3 ATA100 controller"; 144 145 case 0x24cb8086: 146 return "Intel ICH4 ATA100 controller"; 147 148 case 0x522910b9: 149 if (pci_get_revid(dev) >= 0xc4) 150 return "AcerLabs Aladdin ATA100 controller"; 151 else if (pci_get_revid(dev) >= 0xc2) 152 return "AcerLabs Aladdin ATA66 controller"; 153 else if (pci_get_revid(dev) >= 0x20) 154 return "AcerLabs Aladdin ATA33 controller"; 155 else 156 return "AcerLabs Aladdin ATA controller"; 157 158 case 0x05711106: 159 if (ata_find_dev(dev, 0x05861106, 0x02)) 160 return "VIA 82C586 ATA33 controller"; 161 if (ata_find_dev(dev, 0x05861106, 0)) 162 return "VIA 82C586 ATA controller"; 163 if (ata_find_dev(dev, 0x05961106, 0x12)) 164 return "VIA 82C596 ATA66 controller"; 165 if (ata_find_dev(dev, 0x05961106, 0)) 166 return "VIA 82C596 ATA33 controller"; 167 if (ata_find_dev(dev, 0x06861106, 0x40)) 168 return "VIA 82C686 ATA100 controller"; 169 if (ata_find_dev(dev, 0x06861106, 0x10)) 170 return "VIA 82C686 ATA66 controller"; 171 if (ata_find_dev(dev, 0x06861106, 0)) 172 return "VIA 82C686 ATA33 controller"; 173 if (ata_find_dev(dev, 0x82311106, 0)) 174 return "VIA 8231 ATA100 controller"; 175 if (ata_find_dev(dev, 0x30741106, 0) || 176 ata_find_dev(dev, 0x31091106, 0)) 177 return "VIA 8233 ATA100 controller"; 178 if (ata_find_dev(dev, 0x31471106, 0)) 179 return "VIA 8233 ATA133 controller"; 180 if (ata_find_dev(dev, 0x31771106, 0)) 181 return "VIA 8235 ATA133 controller"; 182 return "VIA Apollo ATA controller"; 183 184 case 0x55131039: 185 if (ata_find_dev(dev, 0x06301039, 0x30) || 186 ata_find_dev(dev, 0x06331039, 0) || 187 ata_find_dev(dev, 0x06351039, 0) || 188 ata_find_dev(dev, 0x06401039, 0) || 189 ata_find_dev(dev, 0x06451039, 0) || 190 ata_find_dev(dev, 0x06501039, 0) || 191 ata_find_dev(dev, 0x07301039, 0) || 192 ata_find_dev(dev, 0x07331039, 0) || 193 ata_find_dev(dev, 0x07351039, 0) || 194 ata_find_dev(dev, 0x07401039, 0) || 195 ata_find_dev(dev, 0x07451039, 0) || 196 ata_find_dev(dev, 0x07501039, 0)) 197 return "SiS 5591 ATA100 controller"; 198 else if (ata_find_dev(dev, 0x05301039, 0) || 199 ata_find_dev(dev, 0x05401039, 0) || 200 ata_find_dev(dev, 0x06201039, 0) || 201 ata_find_dev(dev, 0x06301039, 0)) 202 return "SiS 5591 ATA66 controller"; 203 else 204 return "SiS 5591 ATA33 controller"; 205 206 case 0x06801095: 207 return "Sil 0680 ATA133 controller"; 208 209 case 0x06491095: 210 return "CMD 649 ATA100 controller"; 211 212 case 0x06481095: 213 return "CMD 648 ATA66 controller"; 214 215 case 0x06461095: 216 return "CMD 646 ATA controller"; 217 218 case 0xc6931080: 219 if (pci_get_subclass(dev) == PCIS_STORAGE_IDE) 220 return "Cypress 82C693 ATA controller"; 221 return NULL; 222 223 case 0x01021078: 224 return "Cyrix 5530 ATA33 controller"; 225 226 case 0x74091022: 227 return "AMD 756 ATA66 controller"; 228 229 case 0x74111022: 230 return "AMD 766 ATA100 controller"; 231 232 case 0x74411022: 233 return "AMD 768 ATA100 controller"; 234 235 case 0x01bc10de: 236 return "nVIDIA nForce ATA100 controller"; 237 238 case 0x02111166: 239 return "ServerWorks ROSB4 ATA33 controller"; 240 241 case 0x02121166: 242 if (pci_get_revid(dev) >= 0x92) 243 return "ServerWorks CSB5 ATA100 controller"; 244 else 245 return "ServerWorks CSB5 ATA66 controller"; 246 247 case 0x4d33105a: 248 return "Promise ATA33 controller"; 249 250 case 0x0d38105a: 251 case 0x4d38105a: 252 return "Promise ATA66 controller"; 253 254 case 0x0d30105a: 255 case 0x4d30105a: 256 return "Promise ATA100 controller"; 257 258 case 0x4d68105a: 259 case 0x6268105a: 260 { 261 uintptr_t devid = 0; 262 263 /* test if we are behind the right type of bridge */ 264 if (!BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), 265 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && 266 devid == 0x00221011 && 267 pci_get_class(GRANDPARENT(dev)) == PCIC_BRIDGE) { 268 static long start = 0, end = 0; 269 270 /* we belive we are on a TX4, now do our (simple) magic */ 271 if (pci_get_slot(dev) == 1) { 272 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end); 273 return "Promise TX4 ATA100 controller (channel 0+1)"; 274 } 275 else if (pci_get_slot(dev) == 2 && start && end) { 276 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end); 277 start = end = 0; 278 return "Promise TX4 ATA100 controller (channel 2+3)"; 279 } 280 else 281 start = end = 0; 282 } 283 } 284 return "Promise TX2 ATA100 controller"; 285 286 case 0x4d69105a: 287 case 0x5275105a: 288 case 0x6269105a: 289 case 0x7275105a: 290 return "Promise TX2 ATA133 controller"; 291 292 case 0x00041103: 293 switch (pci_get_revid(dev)) { 294 case 0x00: 295 case 0x01: 296 return "HighPoint HPT366 ATA66 controller"; 297 case 0x02: 298 return "HighPoint HPT368 ATA66 controller"; 299 case 0x03: 300 case 0x04: 301 return "HighPoint HPT370 ATA100 controller"; 302 case 0x05: 303 return "HighPoint HPT372 ATA133 controller"; 304 } 305 return NULL; 306 307 case 0x00051103: 308 switch (pci_get_revid(dev)) { 309 case 0x01: 310 return "HighPoint HPT372 ATA133 controller"; 311 } 312 return NULL; 313 314 case 0x00081103: 315 switch (pci_get_revid(dev)) { 316 case 0x07: 317 return "HighPoint HPT374 ATA133 controller"; 318 } 319 return NULL; 320 321 case 0x000116ca: 322 return "Cenatek Rocket Drive controller"; 323 324 /* unsupported but known chipsets, generic DMA only */ 325 case 0x10001042: 326 case 0x10011042: 327 return "RZ 100? ATA controller !WARNING! buggy chip data loss possible"; 328 329 case 0x06401095: 330 return "CMD 640 ATA controller !WARNING! buggy chip data loss possible"; 331 332 /* unknown chipsets, try generic DMA if it seems possible */ 333 default: 334 if (pci_get_class(dev) == PCIC_STORAGE && 335 (pci_get_subclass(dev) == PCIS_STORAGE_IDE)) 336 return "Generic PCI ATA controller"; 337 } 338 return NULL; 339 } 340 341 static int 342 ata_pci_probe(device_t dev) 343 { 344 const char *desc = ata_pci_match(dev); 345 346 if (desc) { 347 device_set_desc(dev, desc); 348 return 0; 349 } 350 else 351 return ENXIO; 352 } 353 354 static int 355 ata_pci_add_child(device_t dev, int unit) 356 { 357 device_t child; 358 359 /* check if this is located at one of the std addresses */ 360 if (ATA_MASTERDEV(dev)) { 361 if (!(child = device_add_child(dev, "ata", unit))) 362 return ENOMEM; 363 } 364 else { 365 if (!(child = 366 device_add_child(dev, "ata", 367 devclass_find_free_unit(ata_devclass, 2)))) 368 return ENOMEM; 369 } 370 return 0; 371 } 372 373 static int 374 ata_pci_attach(device_t dev) 375 { 376 struct ata_pci_controller *controller = device_get_softc(dev); 377 u_int8_t class, subclass; 378 u_int32_t type, cmd; 379 int rid; 380 381 /* set up vendor-specific stuff */ 382 type = pci_get_devid(dev); 383 class = pci_get_class(dev); 384 subclass = pci_get_subclass(dev); 385 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 386 387 if (!(cmd & PCIM_CMD_PORTEN)) { 388 device_printf(dev, "ATA channel disabled by BIOS\n"); 389 return 0; 390 } 391 392 #ifdef __sparc64__ 393 if (!(cmd & PCIM_CMD_BUSMASTEREN)) { 394 pci_write_config(dev, PCIR_COMMAND, cmd | PCIM_CMD_BUSMASTEREN, 2); 395 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 396 } 397 #endif 398 /* is busmastering supported ? */ 399 if ((cmd & (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) == 400 (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) { 401 402 /* is there a valid port range to connect to ? */ 403 rid = 0x20; 404 controller->bmio = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 405 0, ~0, 1, RF_ACTIVE); 406 if (!controller->bmio) 407 device_printf(dev, "Busmastering DMA not configured\n"); 408 } 409 else 410 device_printf(dev, "Busmastering DMA not supported\n"); 411 412 /* do extra chipset specific setups */ 413 switch (type) { 414 415 case 0x522910b9: /* AcerLabs Aladdin need to activate the ATAPI FIFO */ 416 pci_write_config(dev, 0x53, 417 (pci_read_config(dev, 0x53, 1) & ~0x01) | 0x02, 1); 418 break; 419 420 case 0x0d30105a: /* Promise 66 & 100 (before TX2) need the clock changed */ 421 case 0x4d30105a: 422 case 0x0d38105a: 423 case 0x4d38105a: 424 ATA_OUTB(controller->bmio, 0x11, ATA_INB(controller->bmio, 0x11)|0x0a); 425 /* FALLTHROUGH */ 426 427 case 0x4d33105a: /* Promise (before TX2) need burst mode turned on */ 428 ATA_OUTB(controller->bmio, 0x1f, ATA_INB(controller->bmio, 0x1f)|0x01); 429 break; 430 431 case 0x00041103: /* HighPoint HPT366/368/370/372 default setup */ 432 if (pci_get_revid(dev) < 2) { /* HPT366 */ 433 /* turn off interrupt prediction */ 434 pci_write_config(dev, 0x51, 435 (pci_read_config(dev, 0x51, 1) & ~0x80), 1); 436 break; 437 } 438 if (pci_get_revid(dev) < 5) { /* HPT368/370 */ 439 /* turn off interrupt prediction */ 440 pci_write_config(dev, 0x51, 441 (pci_read_config(dev, 0x51, 1) & ~0x03), 1); 442 pci_write_config(dev, 0x55, 443 (pci_read_config(dev, 0x55, 1) & ~0x03), 1); 444 445 /* turn on interrupts */ 446 pci_write_config(dev, 0x5a, 447 (pci_read_config(dev, 0x5a, 1) & ~0x10), 1); 448 449 /* set clocks etc */ 450 pci_write_config(dev, 0x5b, 0x22, 1); 451 break; 452 } 453 /* FALLTHROUGH */ 454 455 case 0x00051103: /* HighPoint HPT372 default setup */ 456 case 0x00081103: /* HighPoint HPT374 default setup */ 457 /* turn off interrupt prediction */ 458 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1); 459 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1); 460 461 /* turn on interrupts */ 462 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1); 463 464 /* set clocks etc */ 465 pci_write_config(dev, 0x5b, 466 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1); 467 break; 468 469 case 0x05711106: /* VIA 82C586, '596, '686 default setup */ 470 /* prepare for ATA-66 on the 82C686a and 82C596b */ 471 if ((ata_find_dev(dev, 0x06861106, 0x10) && 472 !ata_find_dev(dev, 0x06861106, 0x40)) || 473 ata_find_dev(dev, 0x05961106, 0x12)) 474 pci_write_config(dev, 0x50, 0x030b030b, 4); 475 476 /* the southbridge might need the data corruption fix */ 477 if (ata_find_dev(dev, 0x06861106, 0x40) || 478 ata_find_dev(dev, 0x82311106, 0x10)) 479 ata_via_southbridge_fixup(dev); 480 /* FALLTHROUGH */ 481 482 case 0x74091022: /* AMD 756 default setup */ 483 case 0x74111022: /* AMD 766 default setup */ 484 case 0x74411022: /* AMD 768 default setup */ 485 case 0x01bc10de: /* nVIDIA nForce default setup */ 486 /* set prefetch, postwrite */ 487 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1); 488 489 /* set fifo configuration half'n'half */ 490 pci_write_config(dev, 0x43, 491 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1); 492 493 /* set status register read retry */ 494 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1); 495 496 /* set DMA read & end-of-sector fifo flush */ 497 pci_write_config(dev, 0x46, 498 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1); 499 500 /* set sector size */ 501 pci_write_config(dev, 0x60, DEV_BSIZE, 2); 502 pci_write_config(dev, 0x68, DEV_BSIZE, 2); 503 break; 504 505 case 0x02111166: /* ServerWorks ROSB4 enable UDMA33 */ 506 pci_write_config(dev, 0x64, 507 (pci_read_config(dev, 0x64, 4) & ~0x00002000) | 508 0x00004000, 4); 509 break; 510 511 case 0x02121166: /* ServerWorks CSB5 enable UDMA66/100 depending on rev */ 512 pci_write_config(dev, 0x5a, 513 (pci_read_config(dev, 0x5a, 1) & ~0x40) | 514 (pci_get_revid(dev) >= 0x92) ? 0x03 : 0x02, 1); 515 break; 516 517 case 0x06801095: /* Sil 0680 set ATA reference clock speed */ 518 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 519 pci_write_config(dev, 0x8a, 520 (pci_read_config(dev, 0x8a, 1) & 0x0F) | 0x10, 1); 521 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 522 device_printf(dev, "Sil 0680 could not set clock\n"); 523 break; 524 525 case 0x06461095: /* CMD 646 enable interrupts, set DMA read mode */ 526 pci_write_config(dev, 0x71, 0x01, 1); 527 break; 528 529 case 0x10001042: /* RZ 100? known bad, no DMA */ 530 case 0x10011042: 531 case 0x06401095: /* CMD 640 known bad, no DMA */ 532 controller->bmio = NULL; 533 device_printf(dev, "Busmastering DMA disabled\n"); 534 } 535 536 if (controller->bmio) { 537 controller->bmaddr = rman_get_start(controller->bmio); 538 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev, 539 SYS_RES_IOPORT, rid, controller->bmio); 540 controller->bmio = NULL; 541 } 542 543 /* 544 * the Cypress chip is a mess, it contains two ATA functions, but 545 * both channels are visible on the first one. 546 * simply ignore the second function for now, as the right 547 * solution (ignoring the second channel on the first function) 548 * doesn't work with the crappy ATA interrupt setup on the alpha. 549 */ 550 if (pci_get_devid(dev) == 0xc6931080 && pci_get_function(dev) > 1) 551 return 0; 552 553 ata_pci_add_child(dev, 0); 554 555 if (ATA_MASTERDEV(dev) || pci_read_config(dev, 0x18, 4) & IOMASK) 556 ata_pci_add_child(dev, 1); 557 558 return bus_generic_attach(dev); 559 } 560 561 static int 562 ata_pci_intr(struct ata_channel *ch) 563 { 564 u_int8_t dmastat; 565 566 /* 567 * since we might share the IRQ with another device, and in some 568 * cases with our twin channel, we only want to process interrupts 569 * that we know this channel generated. 570 */ 571 switch (ch->chiptype) { 572 case 0x00041103: /* HighPoint HPT366/368/370/372 */ 573 case 0x00051103: /* HighPoint HPT372 */ 574 case 0x00081103: /* HighPoint HPT374 */ 575 if (((dmastat = ata_dmastatus(ch)) & 576 (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) != ATA_BMSTAT_INTERRUPT) 577 return 1; 578 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT); 579 DELAY(1); 580 return 0; 581 582 case 0x06481095: /* CMD 648 */ 583 case 0x06491095: /* CMD 649 */ 584 if (!(pci_read_config(device_get_parent(ch->dev), 0x71, 1) & 585 (ch->unit ? 0x08 : 0x04))) 586 return 1; 587 break; 588 589 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */ 590 case 0x0d38105a: /* Promise Fasttrak 66 */ 591 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */ 592 case 0x0d30105a: /* Promise OEM ATA100 */ 593 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */ 594 if (!(ATA_INL(ch->r_bmio, (ch->unit ? 0x14 : 0x1c)) & 595 (ch->unit ? 0x00004000 : 0x00000400))) 596 return 1; 597 break; 598 599 case 0x4d68105a: /* Promise TX2 ATA100 */ 600 case 0x6268105a: /* Promise TX2 ATA100 */ 601 case 0x4d69105a: /* Promise TX2 ATA133 */ 602 case 0x5275105a: /* Promise TX2 ATA133 */ 603 case 0x6269105a: /* Promise TX2 ATA133 */ 604 case 0x7275105a: /* Promise TX2 ATA133 */ 605 ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b); 606 if (!(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x20)) 607 return 1; 608 break; 609 } 610 611 if (ch->flags & ATA_DMA_ACTIVE) { 612 if (!((dmastat = ata_dmastatus(ch)) & ATA_BMSTAT_INTERRUPT)) 613 return 1; 614 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT); 615 DELAY(1); 616 } 617 return 0; 618 } 619 620 static int 621 ata_pci_print_child(device_t dev, device_t child) 622 { 623 struct ata_channel *ch = device_get_softc(child); 624 int retval = 0; 625 626 retval += bus_print_child_header(dev, child); 627 retval += printf(": at 0x%lx", rman_get_start(ch->r_io)); 628 629 if (ATA_MASTERDEV(dev)) 630 retval += printf(" irq %d", 14 + ch->unit); 631 632 retval += bus_print_child_footer(dev, child); 633 634 return retval; 635 } 636 637 static struct resource * 638 ata_pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 639 u_long start, u_long end, u_long count, u_int flags) 640 { 641 struct ata_pci_controller *controller = device_get_softc(dev); 642 struct resource *res = NULL; 643 int unit = ((struct ata_channel *)device_get_softc(child))->unit; 644 int myrid; 645 646 if (type == SYS_RES_IOPORT) { 647 switch (*rid) { 648 case ATA_IOADDR_RID: 649 if (ATA_MASTERDEV(dev)) { 650 myrid = 0; 651 start = (unit ? ATA_SECONDARY : ATA_PRIMARY); 652 end = start + ATA_IOSIZE - 1; 653 count = ATA_IOSIZE; 654 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 655 SYS_RES_IOPORT, &myrid, 656 start, end, count, flags); 657 } 658 else { 659 myrid = 0x10 + 8 * unit; 660 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev, 661 SYS_RES_IOPORT, &myrid, 662 start, end, count, flags); 663 } 664 break; 665 666 case ATA_ALTADDR_RID: 667 if (ATA_MASTERDEV(dev)) { 668 myrid = 0; 669 start = (unit ? ATA_SECONDARY : ATA_PRIMARY) + ATA_ALTOFFSET; 670 end = start + ATA_ALTIOSIZE - 1; 671 count = ATA_ALTIOSIZE; 672 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 673 SYS_RES_IOPORT, &myrid, 674 start, end, count, flags); 675 } 676 else { 677 myrid = 0x14 + 8 * unit; 678 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev, 679 SYS_RES_IOPORT, &myrid, 680 start, end, count, flags); 681 if (res) { 682 start = rman_get_start(res) + 2; 683 end = start + ATA_ALTIOSIZE - 1; 684 count = ATA_ALTIOSIZE; 685 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev, 686 SYS_RES_IOPORT, myrid, res); 687 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev, 688 SYS_RES_IOPORT, &myrid, 689 start, end, count, flags); 690 } 691 } 692 break; 693 694 case ATA_BMADDR_RID: 695 if (controller->bmaddr) { 696 myrid = 0x20; 697 start = (unit == 0 ? 698 controller->bmaddr : controller->bmaddr+ATA_BMIOSIZE); 699 end = start + ATA_BMIOSIZE - 1; 700 count = ATA_BMIOSIZE; 701 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 702 SYS_RES_IOPORT, &myrid, 703 start, end, count, flags); 704 } 705 } 706 return res; 707 } 708 709 if (type == SYS_RES_IRQ && *rid == ATA_IRQ_RID) { 710 if (ATA_MASTERDEV(dev)) { 711 #ifdef __alpha__ 712 return alpha_platform_alloc_ide_intr(unit); 713 #else 714 int irq = (unit == 0 ? 14 : 15); 715 716 return BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 717 SYS_RES_IRQ, rid, irq, irq, 1, flags); 718 #endif 719 } 720 else { 721 /* primary and secondary channels share interrupt, keep track */ 722 if (!controller->irq) 723 controller->irq = BUS_ALLOC_RESOURCE(device_get_parent(dev), 724 dev, SYS_RES_IRQ, 725 rid, 0, ~0, 1, flags); 726 controller->irqcnt++; 727 return controller->irq; 728 } 729 } 730 return 0; 731 } 732 733 static int 734 ata_pci_release_resource(device_t dev, device_t child, int type, int rid, 735 struct resource *r) 736 { 737 struct ata_pci_controller *controller = device_get_softc(dev); 738 int unit = ((struct ata_channel *)device_get_softc(child))->unit; 739 740 if (type == SYS_RES_IOPORT) { 741 switch (rid) { 742 case ATA_IOADDR_RID: 743 if (ATA_MASTERDEV(dev)) 744 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 745 SYS_RES_IOPORT, 0x0, r); 746 else 747 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev, 748 SYS_RES_IOPORT, 0x10 + 8 * unit, r); 749 break; 750 751 case ATA_ALTADDR_RID: 752 if (ATA_MASTERDEV(dev)) 753 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 754 SYS_RES_IOPORT, 0x0, r); 755 else 756 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev, 757 SYS_RES_IOPORT, 0x14 + 8 * unit, r); 758 break; 759 760 case ATA_BMADDR_RID: 761 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 762 SYS_RES_IOPORT, 0x20, r); 763 default: 764 return ENOENT; 765 } 766 } 767 if (type == SYS_RES_IRQ) { 768 if (rid != ATA_IRQ_RID) 769 return ENOENT; 770 771 if (ATA_MASTERDEV(dev)) { 772 #ifdef __alpha__ 773 return alpha_platform_release_ide_intr(unit, r); 774 #else 775 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 776 SYS_RES_IRQ, rid, r); 777 #endif 778 } 779 else { 780 /* primary and secondary channels share interrupt, keep track */ 781 if (--controller->irqcnt) 782 return 0; 783 controller->irq = NULL; 784 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev, 785 SYS_RES_IRQ, rid, r); 786 } 787 } 788 return EINVAL; 789 } 790 791 static int 792 ata_pci_setup_intr(device_t dev, device_t child, struct resource *irq, 793 int flags, driver_intr_t *intr, void *arg, 794 void **cookiep) 795 { 796 if (ATA_MASTERDEV(dev)) { 797 #ifdef __alpha__ 798 return alpha_platform_setup_ide_intr(child, irq, intr, arg, cookiep); 799 #else 800 return BUS_SETUP_INTR(device_get_parent(dev), child, irq, 801 flags, intr, arg, cookiep); 802 #endif 803 } 804 else 805 return BUS_SETUP_INTR(device_get_parent(dev), dev, irq, 806 flags, intr, arg, cookiep); 807 } 808 809 static int 810 ata_pci_teardown_intr(device_t dev, device_t child, struct resource *irq, 811 void *cookie) 812 { 813 if (ATA_MASTERDEV(dev)) { 814 #ifdef __alpha__ 815 return alpha_platform_teardown_ide_intr(child, irq, cookie); 816 #else 817 return BUS_TEARDOWN_INTR(device_get_parent(dev), child, irq, cookie); 818 #endif 819 } 820 else 821 return BUS_TEARDOWN_INTR(device_get_parent(dev), dev, irq, cookie); 822 } 823 824 static device_method_t ata_pci_methods[] = { 825 /* device interface */ 826 DEVMETHOD(device_probe, ata_pci_probe), 827 DEVMETHOD(device_attach, ata_pci_attach), 828 DEVMETHOD(device_shutdown, bus_generic_shutdown), 829 DEVMETHOD(device_suspend, bus_generic_suspend), 830 DEVMETHOD(device_resume, bus_generic_resume), 831 832 /* bus methods */ 833 DEVMETHOD(bus_print_child, ata_pci_print_child), 834 DEVMETHOD(bus_alloc_resource, ata_pci_alloc_resource), 835 DEVMETHOD(bus_release_resource, ata_pci_release_resource), 836 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 837 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 838 DEVMETHOD(bus_setup_intr, ata_pci_setup_intr), 839 DEVMETHOD(bus_teardown_intr, ata_pci_teardown_intr), 840 { 0, 0 } 841 }; 842 843 static driver_t ata_pci_driver = { 844 "atapci", 845 ata_pci_methods, 846 sizeof(struct ata_pci_controller), 847 }; 848 849 static devclass_t ata_pci_devclass; 850 851 DRIVER_MODULE(atapci, pci, ata_pci_driver, ata_pci_devclass, 0, 0); 852 853 static int 854 ata_pcisub_probe(device_t dev) 855 { 856 struct ata_channel *ch = device_get_softc(dev); 857 device_t *children; 858 int count, i; 859 860 /* find channel number on this controller */ 861 device_get_children(device_get_parent(dev), &children, &count); 862 for (i = 0; i < count; i++) { 863 if (children[i] == dev) 864 ch->unit = i; 865 } 866 free(children, M_TEMP); 867 ch->chiptype = pci_get_devid(device_get_parent(dev)); 868 ch->intr_func = ata_pci_intr; 869 return ata_probe(dev); 870 } 871 872 static device_method_t ata_pcisub_methods[] = { 873 /* device interface */ 874 DEVMETHOD(device_probe, ata_pcisub_probe), 875 DEVMETHOD(device_attach, ata_attach), 876 DEVMETHOD(device_detach, ata_detach), 877 DEVMETHOD(device_resume, ata_resume), 878 { 0, 0 } 879 }; 880 881 static driver_t ata_pcisub_driver = { 882 "ata", 883 ata_pcisub_methods, 884 sizeof(struct ata_channel), 885 }; 886 887 DRIVER_MODULE(ata, atapci, ata_pcisub_driver, ata_devclass, 0, 0); 888