1 /*- 2 * Copyright (c) 1998,1999,2000,2001,2002 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #include "opt_ata.h" 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/module.h> 36 #include <sys/bus.h> 37 #include <sys/malloc.h> 38 #include <machine/stdarg.h> 39 #include <machine/resource.h> 40 #include <machine/bus.h> 41 #ifdef __alpha__ 42 #include <machine/md_var.h> 43 #endif 44 #include <sys/rman.h> 45 #include <pci/pcivar.h> 46 #include <pci/pcireg.h> 47 #include <dev/ata/ata-all.h> 48 49 /* device structures */ 50 struct ata_pci_controller { 51 struct resource *bmio; 52 int bmaddr; 53 struct resource *irq; 54 int irqcnt; 55 int lock; 56 }; 57 58 /* misc defines */ 59 #define IOMASK 0xfffffffc 60 #define GRANDPARENT(dev) device_get_parent(device_get_parent(dev)) 61 #define ATA_MASTERDEV(dev) ((pci_get_progif(dev) & 0x80) && \ 62 (pci_get_progif(dev) & 0x05) != 0x05) 63 64 int 65 ata_find_dev(device_t dev, u_int32_t devid, u_int32_t revid) 66 { 67 device_t *children; 68 int nchildren, i; 69 70 if (device_get_children(device_get_parent(dev), &children, &nchildren)) 71 return 0; 72 73 for (i = 0; i < nchildren; i++) { 74 if (pci_get_devid(children[i]) == devid && 75 pci_get_revid(children[i]) >= revid) { 76 free(children, M_TEMP); 77 return 1; 78 } 79 } 80 free(children, M_TEMP); 81 return 0; 82 } 83 84 static void 85 ata_via_southbridge_fixup(device_t dev) 86 { 87 device_t *children; 88 int nchildren, i; 89 90 if (device_get_children(device_get_parent(dev), &children, &nchildren)) 91 return; 92 93 for (i = 0; i < nchildren; i++) { 94 if (pci_get_devid(children[i]) == 0x03051106 || /* VIA VT8363 */ 95 pci_get_devid(children[i]) == 0x03911106 || /* VIA VT8371 */ 96 pci_get_devid(children[i]) == 0x31021106 || /* VIA VT8662 */ 97 pci_get_devid(children[i]) == 0x31121106) { /* VIA VT8361 */ 98 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1); 99 100 if ((reg76 & 0xf0) != 0xd0) { 101 device_printf(dev, 102 "Correcting VIA config for southbridge data corruption bug\n"); 103 pci_write_config(children[i], 0x75, 0x80, 1); 104 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1); 105 } 106 break; 107 } 108 } 109 free(children, M_TEMP); 110 } 111 112 static const char * 113 ata_pci_match(device_t dev) 114 { 115 if (pci_get_class(dev) != PCIC_STORAGE) 116 return NULL; 117 118 switch (pci_get_devid(dev)) { 119 /* supported chipsets */ 120 case 0x12308086: 121 return "Intel PIIX ATA controller"; 122 123 case 0x70108086: 124 return "Intel PIIX3 ATA controller"; 125 126 case 0x71118086: 127 case 0x71998086: 128 case 0x84ca8086: 129 return "Intel PIIX4 ATA33 controller"; 130 131 case 0x24218086: 132 return "Intel ICH0 ATA33 controller"; 133 134 case 0x24118086: 135 case 0x76018086: 136 return "Intel ICH ATA66 controller"; 137 138 case 0x244a8086: 139 case 0x244b8086: 140 return "Intel ICH2 ATA100 controller"; 141 142 case 0x248a8086: 143 case 0x248b8086: 144 return "Intel ICH3 ATA100 controller"; 145 146 case 0x24cb8086: 147 return "Intel ICH4 ATA100 controller"; 148 149 case 0x522910b9: 150 if (pci_get_revid(dev) >= 0xc4) 151 return "AcerLabs Aladdin ATA100 controller"; 152 else if (pci_get_revid(dev) >= 0xc2) 153 return "AcerLabs Aladdin ATA66 controller"; 154 else if (pci_get_revid(dev) >= 0x20) 155 return "AcerLabs Aladdin ATA33 controller"; 156 else 157 return "AcerLabs Aladdin ATA controller"; 158 159 case 0x05711106: 160 if (ata_find_dev(dev, 0x05861106, 0x02)) 161 return "VIA 82C586 ATA33 controller"; 162 if (ata_find_dev(dev, 0x05861106, 0)) 163 return "VIA 82C586 ATA controller"; 164 if (ata_find_dev(dev, 0x05961106, 0x12)) 165 return "VIA 82C596 ATA66 controller"; 166 if (ata_find_dev(dev, 0x05961106, 0)) 167 return "VIA 82C596 ATA33 controller"; 168 if (ata_find_dev(dev, 0x06861106, 0x40)) 169 return "VIA 82C686 ATA100 controller"; 170 if (ata_find_dev(dev, 0x06861106, 0x10)) 171 return "VIA 82C686 ATA66 controller"; 172 if (ata_find_dev(dev, 0x06861106, 0)) 173 return "VIA 82C686 ATA33 controller"; 174 if (ata_find_dev(dev, 0x82311106, 0)) 175 return "VIA 8231 ATA100 controller"; 176 if (ata_find_dev(dev, 0x30741106, 0) || 177 ata_find_dev(dev, 0x31091106, 0)) 178 return "VIA 8233 ATA100 controller"; 179 if (ata_find_dev(dev, 0x31471106, 0)) 180 return "VIA 8233 ATA133 controller"; 181 if (ata_find_dev(dev, 0x31771106, 0)) 182 return "VIA 8235 ATA133 controller"; 183 return "VIA Apollo ATA controller"; 184 185 case 0x55131039: 186 if (ata_find_dev(dev, 0x06301039, 0x30) || 187 ata_find_dev(dev, 0x06331039, 0) || 188 ata_find_dev(dev, 0x06351039, 0) || 189 ata_find_dev(dev, 0x06401039, 0) || 190 ata_find_dev(dev, 0x06451039, 0) || 191 ata_find_dev(dev, 0x06501039, 0) || 192 ata_find_dev(dev, 0x07301039, 0) || 193 ata_find_dev(dev, 0x07331039, 0) || 194 ata_find_dev(dev, 0x07351039, 0) || 195 ata_find_dev(dev, 0x07401039, 0) || 196 ata_find_dev(dev, 0x07451039, 0) || 197 ata_find_dev(dev, 0x07501039, 0)) 198 return "SiS 5591 ATA100 controller"; 199 else if (ata_find_dev(dev, 0x05301039, 0) || 200 ata_find_dev(dev, 0x05401039, 0) || 201 ata_find_dev(dev, 0x06201039, 0) || 202 ata_find_dev(dev, 0x06301039, 0)) 203 return "SiS 5591 ATA66 controller"; 204 else 205 return "SiS 5591 ATA33 controller"; 206 207 case 0x06801095: 208 return "Sil 0680 ATA133 controller"; 209 210 case 0x06491095: 211 return "CMD 649 ATA100 controller"; 212 213 case 0x06481095: 214 return "CMD 648 ATA66 controller"; 215 216 case 0x06461095: 217 return "CMD 646 ATA controller"; 218 219 case 0xc6931080: 220 if (pci_get_subclass(dev) == PCIS_STORAGE_IDE) 221 return "Cypress 82C693 ATA controller"; 222 return NULL; 223 224 case 0x01021078: 225 return "Cyrix 5530 ATA33 controller"; 226 227 case 0x74091022: 228 return "AMD 756 ATA66 controller"; 229 230 case 0x74111022: 231 return "AMD 766 ATA100 controller"; 232 233 case 0x74411022: 234 return "AMD 768 ATA100 controller"; 235 236 case 0x01bc10de: 237 return "nVidia nForce ATA100 controller"; 238 239 case 0x006510de: 240 return "nVidia nForce ATA133 controller"; 241 242 case 0x02111166: 243 return "ServerWorks ROSB4 ATA33 controller"; 244 245 case 0x02121166: 246 if (pci_get_revid(dev) >= 0x92) 247 return "ServerWorks CSB5 ATA100 controller"; 248 else 249 return "ServerWorks CSB5 ATA66 controller"; 250 251 case 0x4d33105a: 252 return "Promise ATA33 controller"; 253 254 case 0x0d38105a: 255 case 0x4d38105a: 256 return "Promise ATA66 controller"; 257 258 case 0x0d30105a: 259 case 0x4d30105a: 260 return "Promise ATA100 controller"; 261 262 case 0x4d68105a: 263 case 0x6268105a: 264 { 265 uintptr_t devid = 0; 266 267 /* test if we are behind the right type of bridge */ 268 if (!BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), 269 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && 270 devid == 0x00221011 && 271 pci_get_class(GRANDPARENT(dev)) == PCIC_BRIDGE) { 272 static long start = 0, end = 0; 273 274 /* we belive we are on a TX4, now do our (simple) magic */ 275 if (pci_get_slot(dev) == 1) { 276 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end); 277 return "Promise TX4 ATA100 controller (channel 0+1)"; 278 } 279 else if (pci_get_slot(dev) == 2 && start && end) { 280 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end); 281 start = end = 0; 282 return "Promise TX4 ATA100 controller (channel 2+3)"; 283 } 284 else 285 start = end = 0; 286 } 287 } 288 return "Promise TX2 ATA100 controller"; 289 290 case 0x4d69105a: 291 case 0x5275105a: 292 case 0x6269105a: 293 case 0x7275105a: 294 return "Promise TX2 ATA133 controller"; 295 296 case 0x00041103: 297 switch (pci_get_revid(dev)) { 298 case 0x00: 299 case 0x01: 300 return "HighPoint HPT366 ATA66 controller"; 301 case 0x02: 302 return "HighPoint HPT368 ATA66 controller"; 303 case 0x03: 304 case 0x04: 305 return "HighPoint HPT370 ATA100 controller"; 306 case 0x05: 307 return "HighPoint HPT372 ATA133 controller"; 308 } 309 return NULL; 310 311 case 0x00051103: 312 switch (pci_get_revid(dev)) { 313 case 0x01: 314 return "HighPoint HPT372 ATA133 controller"; 315 } 316 return NULL; 317 318 case 0x00081103: 319 switch (pci_get_revid(dev)) { 320 case 0x07: 321 if (pci_get_function(dev) == 0) 322 return "HighPoint HPT374 ATA133 controller (channel 0+1)"; 323 if (pci_get_function(dev) == 1) 324 return "HighPoint HPT374 ATA133 controller (channel 2+3)"; 325 return "HighPoint HPT374 ATA133 controller"; 326 } 327 return NULL; 328 329 case 0x00051191: 330 return "Acard ATP850 ATA-33 controller"; 331 332 case 0x00061191: 333 case 0x00071191: 334 return "Acard ATP860 ATA-66 controller"; 335 336 case 0x00081191: 337 case 0x00091191: 338 return "Acard ATP865 ATA-133 controller"; 339 340 case 0x000116ca: 341 return "Cenatek Rocket Drive controller"; 342 343 /* unsupported but known chipsets, generic DMA only */ 344 case 0x10001042: 345 case 0x10011042: 346 return "RZ 100? ATA controller !WARNING! buggy chip data loss possible"; 347 348 case 0x06401095: 349 return "CMD 640 ATA controller !WARNING! buggy chip data loss possible"; 350 351 /* unknown chipsets, try generic DMA if it seems possible */ 352 default: 353 if (pci_get_class(dev) == PCIC_STORAGE && 354 (pci_get_subclass(dev) == PCIS_STORAGE_IDE)) 355 return "Generic PCI ATA controller"; 356 } 357 return NULL; 358 } 359 360 static int 361 ata_pci_probe(device_t dev) 362 { 363 const char *desc = ata_pci_match(dev); 364 365 if (desc) { 366 device_set_desc(dev, desc); 367 return 0; 368 } 369 else 370 return ENXIO; 371 } 372 373 static int 374 ata_pci_add_child(device_t dev, int unit) 375 { 376 /* check if this is located at one of the std addresses */ 377 if (ATA_MASTERDEV(dev)) { 378 if (!device_add_child(dev, "ata", unit)) 379 return ENOMEM; 380 } 381 else { 382 if (!device_add_child(dev, "ata", 383 devclass_find_free_unit(ata_devclass, 2))) 384 return ENOMEM; 385 } 386 return 0; 387 } 388 389 static int 390 ata_pci_attach(device_t dev) 391 { 392 struct ata_pci_controller *controller = device_get_softc(dev); 393 u_int8_t class, subclass; 394 u_int32_t type, cmd; 395 int rid; 396 397 /* set up vendor-specific stuff */ 398 type = pci_get_devid(dev); 399 class = pci_get_class(dev); 400 subclass = pci_get_subclass(dev); 401 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 402 403 if (!(cmd & PCIM_CMD_PORTEN)) { 404 device_printf(dev, "ATA channel disabled by BIOS\n"); 405 return 0; 406 } 407 408 #ifdef __sparc64__ 409 if (!(cmd & PCIM_CMD_BUSMASTEREN)) { 410 pci_write_config(dev, PCIR_COMMAND, cmd | PCIM_CMD_BUSMASTEREN, 2); 411 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 412 } 413 #endif 414 /* is busmastering supported ? */ 415 if ((cmd & (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) == 416 (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) { 417 418 /* is there a valid port range to connect to ? */ 419 rid = 0x20; 420 controller->bmio = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 421 0, ~0, 1, RF_ACTIVE); 422 if (!controller->bmio) 423 device_printf(dev, "Busmastering DMA not configured\n"); 424 } 425 else 426 device_printf(dev, "Busmastering DMA not supported\n"); 427 428 /* do extra chipset specific setups */ 429 switch (type) { 430 431 case 0x522910b9: /* AcerLabs Aladdin need to activate the ATAPI FIFO */ 432 pci_write_config(dev, 0x53, 433 (pci_read_config(dev, 0x53, 1) & ~0x01) | 0x02, 1); 434 break; 435 436 case 0x0d30105a: /* Promise 66 & 100 (before TX2) need the clock changed */ 437 case 0x4d30105a: 438 case 0x0d38105a: 439 case 0x4d38105a: 440 ATA_OUTB(controller->bmio, 0x11, ATA_INB(controller->bmio, 0x11)|0x0a); 441 /* FALLTHROUGH */ 442 443 case 0x4d33105a: /* Promise (before TX2) need burst mode turned on */ 444 ATA_OUTB(controller->bmio, 0x1f, ATA_INB(controller->bmio, 0x1f)|0x01); 445 break; 446 447 case 0x00041103: /* HighPoint HPT366/368/370/372 default setup */ 448 if (pci_get_revid(dev) < 2) { /* HPT366 */ 449 /* turn off interrupt prediction */ 450 pci_write_config(dev, 0x51, 451 (pci_read_config(dev, 0x51, 1) & ~0x80), 1); 452 break; 453 } 454 if (pci_get_revid(dev) < 5) { /* HPT368/370 */ 455 /* turn off interrupt prediction */ 456 pci_write_config(dev, 0x51, 457 (pci_read_config(dev, 0x51, 1) & ~0x03), 1); 458 pci_write_config(dev, 0x55, 459 (pci_read_config(dev, 0x55, 1) & ~0x03), 1); 460 461 /* turn on interrupts */ 462 pci_write_config(dev, 0x5a, 463 (pci_read_config(dev, 0x5a, 1) & ~0x10), 1); 464 465 /* set clocks etc */ 466 pci_write_config(dev, 0x5b, 0x22, 1); 467 break; 468 } 469 /* FALLTHROUGH */ 470 471 case 0x00051103: /* HighPoint HPT372 default setup */ 472 case 0x00081103: /* HighPoint HPT374 default setup */ 473 /* turn off interrupt prediction */ 474 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1); 475 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1); 476 477 /* turn on interrupts */ 478 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1); 479 480 /* set clocks etc */ 481 pci_write_config(dev, 0x5b, 482 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1); 483 break; 484 485 case 0x05711106: /* VIA 82C586, '596, '686 default setup */ 486 /* prepare for ATA-66 on the 82C686a and 82C596b */ 487 if ((ata_find_dev(dev, 0x06861106, 0x10) && 488 !ata_find_dev(dev, 0x06861106, 0x40)) || 489 ata_find_dev(dev, 0x05961106, 0x12)) 490 pci_write_config(dev, 0x50, 0x030b030b, 4); 491 492 /* the southbridge might need the data corruption fix */ 493 if (ata_find_dev(dev, 0x06861106, 0x40) || 494 ata_find_dev(dev, 0x82311106, 0x10)) 495 ata_via_southbridge_fixup(dev); 496 /* FALLTHROUGH */ 497 498 case 0x74091022: /* AMD 756 default setup */ 499 case 0x74111022: /* AMD 766 default setup */ 500 case 0x74411022: /* AMD 768 default setup */ 501 case 0x01bc10de: /* nVIDIA nForce default setup */ 502 /* set prefetch, postwrite */ 503 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1); 504 505 /* set fifo configuration half'n'half */ 506 pci_write_config(dev, 0x43, 507 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1); 508 509 /* set status register read retry */ 510 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1); 511 512 /* set DMA read & end-of-sector fifo flush */ 513 pci_write_config(dev, 0x46, 514 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1); 515 516 /* set sector size */ 517 pci_write_config(dev, 0x60, DEV_BSIZE, 2); 518 pci_write_config(dev, 0x68, DEV_BSIZE, 2); 519 break; 520 521 case 0x02111166: /* ServerWorks ROSB4 enable UDMA33 */ 522 pci_write_config(dev, 0x64, 523 (pci_read_config(dev, 0x64, 4) & ~0x00002000) | 524 0x00004000, 4); 525 break; 526 527 case 0x02121166: /* ServerWorks CSB5 enable UDMA66/100 depending on rev */ 528 pci_write_config(dev, 0x5a, 529 (pci_read_config(dev, 0x5a, 1) & ~0x40) | 530 (pci_get_revid(dev) >= 0x92) ? 0x03 : 0x02, 1); 531 break; 532 533 case 0x06801095: /* Sil 0680 set ATA reference clock speed */ 534 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 535 pci_write_config(dev, 0x8a, 536 (pci_read_config(dev, 0x8a, 1) & 0x0F) | 0x10, 1); 537 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 538 device_printf(dev, "Sil 0680 could not set clock\n"); 539 break; 540 541 case 0x06461095: /* CMD 646 enable interrupts, set DMA read mode */ 542 pci_write_config(dev, 0x71, 0x01, 1); 543 break; 544 545 case 0x10001042: /* RZ 100? known bad, no DMA */ 546 case 0x10011042: 547 case 0x06401095: /* CMD 640 known bad, no DMA */ 548 controller->bmio = NULL; 549 device_printf(dev, "Busmastering DMA disabled\n"); 550 } 551 552 if (controller->bmio) { 553 controller->bmaddr = rman_get_start(controller->bmio); 554 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev, 555 SYS_RES_IOPORT, rid, controller->bmio); 556 controller->bmio = NULL; 557 } 558 controller->lock = -1; 559 560 /* 561 * the Cypress chip is a mess, it contains two ATA functions, but 562 * both channels are visible on the first one. 563 * simply ignore the second function for now, as the right 564 * solution (ignoring the second channel on the first function) 565 * doesn't work with the crappy ATA interrupt setup on the alpha. 566 */ 567 if (pci_get_devid(dev) == 0xc6931080 && pci_get_function(dev) > 1) 568 return 0; 569 570 ata_pci_add_child(dev, 0); 571 572 if (ATA_MASTERDEV(dev) || pci_read_config(dev, 0x18, 4) & IOMASK) 573 ata_pci_add_child(dev, 1); 574 575 return bus_generic_attach(dev); 576 } 577 578 static int 579 ata_pci_intr(struct ata_channel *ch) 580 { 581 u_int8_t dmastat; 582 583 /* 584 * since we might share the IRQ with another device, and in some 585 * cases with our twin channel, we only want to process interrupts 586 * that we know this channel generated. 587 */ 588 switch (ch->chiptype) { 589 case 0x00041103: /* HighPoint HPT366/368/370/372 */ 590 case 0x00051103: /* HighPoint HPT372 */ 591 case 0x00081103: /* HighPoint HPT374 */ 592 if (((dmastat = ata_dmastatus(ch)) & 593 (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) != ATA_BMSTAT_INTERRUPT) 594 return 0; 595 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT); 596 DELAY(1); 597 return 1; 598 599 case 0x06481095: /* CMD 648 */ 600 case 0x06491095: /* CMD 649 */ 601 if (!(pci_read_config(device_get_parent(ch->dev), 0x71, 1) & 602 (ch->unit ? 0x08 : 0x04))) 603 return 0; 604 break; 605 606 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */ 607 case 0x0d38105a: /* Promise Fasttrak 66 */ 608 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */ 609 case 0x0d30105a: /* Promise OEM ATA100 */ 610 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */ 611 if (!(ATA_INL(ch->r_bmio, (ch->unit ? 0x14 : 0x1c)) & 612 (ch->unit ? 0x00004000 : 0x00000400))) 613 return 0; 614 break; 615 616 case 0x4d68105a: /* Promise TX2 ATA100 */ 617 case 0x6268105a: /* Promise TX2 ATA100 */ 618 case 0x4d69105a: /* Promise TX2 ATA133 */ 619 case 0x5275105a: /* Promise TX2 ATA133 */ 620 case 0x6269105a: /* Promise TX2 ATA133 */ 621 case 0x7275105a: /* Promise TX2 ATA133 */ 622 ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b); 623 if (!(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x20)) 624 return 0; 625 break; 626 627 case 0x00051191: /* Acard ATP850 */ 628 { 629 struct ata_pci_controller *scp = 630 device_get_softc(device_get_parent(ch->dev)); 631 632 if (ch->unit != scp->lock) 633 return 0; 634 } 635 /* FALLTHROUGH */ 636 637 case 0x00061191: /* Acard ATP860 */ 638 case 0x00071191: /* Acard ATP860R */ 639 case 0x00081191: /* Acard ATP865 */ 640 case 0x00091191: /* Acard ATP865R */ 641 if (ch->flags & ATA_DMA_ACTIVE) { 642 if (!((dmastat = ata_dmastatus(ch)) & ATA_BMSTAT_INTERRUPT)) 643 return 0; 644 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat|ATA_BMSTAT_INTERRUPT); 645 DELAY(1); 646 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, 647 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT)&~ATA_BMCMD_START_STOP); 648 DELAY(1); 649 } 650 return 1; 651 } 652 653 if (ch->flags & ATA_DMA_ACTIVE) { 654 if (!((dmastat = ata_dmastatus(ch)) & ATA_BMSTAT_INTERRUPT)) 655 return 0; 656 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT); 657 DELAY(1); 658 } 659 return 1; 660 } 661 662 static void 663 ata_pci_locknoop(struct ata_channel *ch, int type) 664 { 665 } 666 667 static void 668 ata_pci_serialize(struct ata_channel *ch, int flags) 669 { 670 struct ata_pci_controller *scp = 671 device_get_softc(device_get_parent(ch->dev)); 672 673 switch (flags) { 674 case ATA_LF_LOCK: 675 if (scp->lock == ch->unit) 676 break; 677 while (!atomic_cmpset_acq_int(&scp->lock, -1, ch->unit)) 678 tsleep((caddr_t)ch->lock_func, PRIBIO, "atalck", 1); 679 break; 680 681 case ATA_LF_UNLOCK: 682 if (scp->lock == -1 || scp->lock != ch->unit) 683 break; 684 atomic_store_rel_int(&scp->lock, -1); 685 break; 686 } 687 return; 688 } 689 690 static int 691 ata_pci_print_child(device_t dev, device_t child) 692 { 693 struct ata_channel *ch = device_get_softc(child); 694 int retval = 0; 695 696 retval += bus_print_child_header(dev, child); 697 retval += printf(": at 0x%lx", rman_get_start(ch->r_io)); 698 699 if (ATA_MASTERDEV(dev)) 700 retval += printf(" irq %d", 14 + ch->unit); 701 702 retval += bus_print_child_footer(dev, child); 703 704 return retval; 705 } 706 707 static struct resource * 708 ata_pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 709 u_long start, u_long end, u_long count, u_int flags) 710 { 711 struct ata_pci_controller *controller = device_get_softc(dev); 712 struct resource *res = NULL; 713 int unit = ((struct ata_channel *)device_get_softc(child))->unit; 714 int myrid; 715 716 if (type == SYS_RES_IOPORT) { 717 switch (*rid) { 718 case ATA_IOADDR_RID: 719 if (ATA_MASTERDEV(dev)) { 720 myrid = 0; 721 start = (unit ? ATA_SECONDARY : ATA_PRIMARY); 722 end = start + ATA_IOSIZE - 1; 723 count = ATA_IOSIZE; 724 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 725 SYS_RES_IOPORT, &myrid, 726 start, end, count, flags); 727 } 728 else { 729 myrid = 0x10 + 8 * unit; 730 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev, 731 SYS_RES_IOPORT, &myrid, 732 start, end, count, flags); 733 } 734 break; 735 736 case ATA_ALTADDR_RID: 737 if (ATA_MASTERDEV(dev)) { 738 myrid = 0; 739 start = (unit ? ATA_SECONDARY : ATA_PRIMARY) + ATA_ALTOFFSET; 740 end = start + ATA_ALTIOSIZE - 1; 741 count = ATA_ALTIOSIZE; 742 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 743 SYS_RES_IOPORT, &myrid, 744 start, end, count, flags); 745 } 746 else { 747 myrid = 0x14 + 8 * unit; 748 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev, 749 SYS_RES_IOPORT, &myrid, 750 start, end, count, flags); 751 if (res) { 752 start = rman_get_start(res) + 2; 753 end = start + ATA_ALTIOSIZE - 1; 754 count = ATA_ALTIOSIZE; 755 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev, 756 SYS_RES_IOPORT, myrid, res); 757 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev, 758 SYS_RES_IOPORT, &myrid, 759 start, end, count, flags); 760 } 761 } 762 break; 763 764 case ATA_BMADDR_RID: 765 if (controller->bmaddr) { 766 myrid = 0x20; 767 start = (unit == 0 ? 768 controller->bmaddr : controller->bmaddr+ATA_BMIOSIZE); 769 end = start + ATA_BMIOSIZE - 1; 770 count = ATA_BMIOSIZE; 771 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 772 SYS_RES_IOPORT, &myrid, 773 start, end, count, flags); 774 } 775 } 776 return res; 777 } 778 779 if (type == SYS_RES_IRQ && *rid == ATA_IRQ_RID) { 780 if (ATA_MASTERDEV(dev)) { 781 #ifdef __alpha__ 782 return alpha_platform_alloc_ide_intr(unit); 783 #else 784 int irq = (unit == 0 ? 14 : 15); 785 786 return BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 787 SYS_RES_IRQ, rid, irq, irq, 1, flags); 788 #endif 789 } 790 else { 791 /* primary and secondary channels share interrupt, keep track */ 792 if (!controller->irq) 793 controller->irq = BUS_ALLOC_RESOURCE(device_get_parent(dev), 794 dev, SYS_RES_IRQ, 795 rid, 0, ~0, 1, flags); 796 controller->irqcnt++; 797 return controller->irq; 798 } 799 } 800 return 0; 801 } 802 803 static int 804 ata_pci_release_resource(device_t dev, device_t child, int type, int rid, 805 struct resource *r) 806 { 807 struct ata_pci_controller *controller = device_get_softc(dev); 808 int unit = ((struct ata_channel *)device_get_softc(child))->unit; 809 810 if (type == SYS_RES_IOPORT) { 811 switch (rid) { 812 case ATA_IOADDR_RID: 813 if (ATA_MASTERDEV(dev)) 814 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 815 SYS_RES_IOPORT, 0x0, r); 816 else 817 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev, 818 SYS_RES_IOPORT, 0x10 + 8 * unit, r); 819 break; 820 821 case ATA_ALTADDR_RID: 822 if (ATA_MASTERDEV(dev)) 823 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 824 SYS_RES_IOPORT, 0x0, r); 825 else 826 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev, 827 SYS_RES_IOPORT, 0x14 + 8 * unit, r); 828 break; 829 830 case ATA_BMADDR_RID: 831 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 832 SYS_RES_IOPORT, 0x20, r); 833 default: 834 return ENOENT; 835 } 836 } 837 if (type == SYS_RES_IRQ) { 838 if (rid != ATA_IRQ_RID) 839 return ENOENT; 840 841 if (ATA_MASTERDEV(dev)) { 842 #ifdef __alpha__ 843 return alpha_platform_release_ide_intr(unit, r); 844 #else 845 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 846 SYS_RES_IRQ, rid, r); 847 #endif 848 } 849 else { 850 /* primary and secondary channels share interrupt, keep track */ 851 if (--controller->irqcnt) 852 return 0; 853 controller->irq = NULL; 854 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev, 855 SYS_RES_IRQ, rid, r); 856 } 857 } 858 return EINVAL; 859 } 860 861 static int 862 ata_pci_setup_intr(device_t dev, device_t child, struct resource *irq, 863 int flags, driver_intr_t *intr, void *arg, 864 void **cookiep) 865 { 866 if (ATA_MASTERDEV(dev)) { 867 #ifdef __alpha__ 868 return alpha_platform_setup_ide_intr(child, irq, intr, arg, cookiep); 869 #else 870 return BUS_SETUP_INTR(device_get_parent(dev), child, irq, 871 flags, intr, arg, cookiep); 872 #endif 873 } 874 else 875 return BUS_SETUP_INTR(device_get_parent(dev), dev, irq, 876 flags, intr, arg, cookiep); 877 } 878 879 static int 880 ata_pci_teardown_intr(device_t dev, device_t child, struct resource *irq, 881 void *cookie) 882 { 883 if (ATA_MASTERDEV(dev)) { 884 #ifdef __alpha__ 885 return alpha_platform_teardown_ide_intr(child, irq, cookie); 886 #else 887 return BUS_TEARDOWN_INTR(device_get_parent(dev), child, irq, cookie); 888 #endif 889 } 890 else 891 return BUS_TEARDOWN_INTR(device_get_parent(dev), dev, irq, cookie); 892 } 893 894 static device_method_t ata_pci_methods[] = { 895 /* device interface */ 896 DEVMETHOD(device_probe, ata_pci_probe), 897 DEVMETHOD(device_attach, ata_pci_attach), 898 DEVMETHOD(device_shutdown, bus_generic_shutdown), 899 DEVMETHOD(device_suspend, bus_generic_suspend), 900 DEVMETHOD(device_resume, bus_generic_resume), 901 902 /* bus methods */ 903 DEVMETHOD(bus_print_child, ata_pci_print_child), 904 DEVMETHOD(bus_alloc_resource, ata_pci_alloc_resource), 905 DEVMETHOD(bus_release_resource, ata_pci_release_resource), 906 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 907 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 908 DEVMETHOD(bus_setup_intr, ata_pci_setup_intr), 909 DEVMETHOD(bus_teardown_intr, ata_pci_teardown_intr), 910 { 0, 0 } 911 }; 912 913 static driver_t ata_pci_driver = { 914 "atapci", 915 ata_pci_methods, 916 sizeof(struct ata_pci_controller), 917 }; 918 919 static devclass_t ata_pci_devclass; 920 921 DRIVER_MODULE(atapci, pci, ata_pci_driver, ata_pci_devclass, 0, 0); 922 923 static int 924 ata_pcisub_probe(device_t dev) 925 { 926 struct ata_channel *ch = device_get_softc(dev); 927 device_t *children; 928 int count, i; 929 930 /* find channel number on this controller */ 931 device_get_children(device_get_parent(dev), &children, &count); 932 for (i = 0; i < count; i++) { 933 if (children[i] == dev) 934 ch->unit = i; 935 } 936 free(children, M_TEMP); 937 938 ch->intr_func = ata_pci_intr; 939 ch->chiptype = pci_get_devid(device_get_parent(dev)); 940 switch (ch->chiptype) { 941 case 0x10001042: /* RZ 1000 */ 942 case 0x10011042: /* RZ 1001 */ 943 case 0x06401095: /* CMD 640 */ 944 case 0x00051191: /* Acard ATP850 */ 945 ch->lock_func = ata_pci_serialize; 946 break; 947 default: 948 ch->lock_func = ata_pci_locknoop; 949 } 950 return ata_probe(dev); 951 } 952 953 static device_method_t ata_pcisub_methods[] = { 954 /* device interface */ 955 DEVMETHOD(device_probe, ata_pcisub_probe), 956 DEVMETHOD(device_attach, ata_attach), 957 DEVMETHOD(device_detach, ata_detach), 958 DEVMETHOD(device_resume, ata_resume), 959 { 0, 0 } 960 }; 961 962 static driver_t ata_pcisub_driver = { 963 "ata", 964 ata_pcisub_methods, 965 sizeof(struct ata_channel), 966 }; 967 968 DRIVER_MODULE(ata, atapci, ata_pcisub_driver, ata_devclass, 0, 0); 969