1 /*- 2 * Copyright (c) 1998,1999,2000,2001,2002 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/disk.h> 35 #include <sys/module.h> 36 #include <sys/bus.h> 37 #include <sys/bio.h> 38 #include <sys/malloc.h> 39 #include <sys/devicestat.h> 40 #include <sys/sysctl.h> 41 #include <machine/stdarg.h> 42 #include <machine/resource.h> 43 #include <machine/bus.h> 44 #ifdef __alpha__ 45 #include <machine/md_var.h> 46 #endif 47 #include <sys/rman.h> 48 #include <pci/pcivar.h> 49 #include <pci/pcireg.h> 50 #include <dev/ata/ata-all.h> 51 52 /* device structures */ 53 struct ata_pci_controller { 54 struct resource *bmio; 55 int bmaddr; 56 struct resource *irq; 57 int irqcnt; 58 }; 59 60 /* misc defines */ 61 #define IOMASK 0xfffffffc 62 #define GRANDPARENT(dev) device_get_parent(device_get_parent(dev)) 63 #define ATA_MASTERDEV(dev) ((pci_get_progif(dev) & 0x80) && \ 64 (pci_get_progif(dev) & 0x05) != 0x05) 65 66 int 67 ata_find_dev(device_t dev, u_int32_t devid, u_int32_t revid) 68 { 69 device_t *children; 70 int nchildren, i; 71 72 if (device_get_children(device_get_parent(dev), &children, &nchildren)) 73 return 0; 74 75 for (i = 0; i < nchildren; i++) { 76 if (pci_get_devid(children[i]) == devid && 77 pci_get_revid(children[i]) >= revid) { 78 free(children, M_TEMP); 79 return 1; 80 } 81 } 82 free(children, M_TEMP); 83 return 0; 84 } 85 86 static void 87 ata_via_southbridge_fixup(device_t dev) 88 { 89 device_t *children; 90 int nchildren, i; 91 92 if (device_get_children(device_get_parent(dev), &children, &nchildren)) 93 return; 94 95 for (i = 0; i < nchildren; i++) { 96 if (pci_get_devid(children[i]) == 0x03051106 || /* VIA VT8363 */ 97 pci_get_devid(children[i]) == 0x03911106 || /* VIA VT8371 */ 98 pci_get_devid(children[i]) == 0x31021106 || /* VIA VT8662 */ 99 pci_get_devid(children[i]) == 0x31121106) { /* VIA VT8361 */ 100 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1); 101 102 if ((reg76 & 0xf0) != 0xd0) { 103 device_printf(dev, 104 "Correcting VIA config for southbridge data corruption bug\n"); 105 pci_write_config(children[i], 0x75, 0x80, 1); 106 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1); 107 } 108 break; 109 } 110 } 111 free(children, M_TEMP); 112 } 113 114 static const char * 115 ata_pci_match(device_t dev) 116 { 117 if (pci_get_class(dev) != PCIC_STORAGE) 118 return NULL; 119 120 switch (pci_get_devid(dev)) { 121 /* supported chipsets */ 122 case 0x12308086: 123 return "Intel PIIX ATA controller"; 124 125 case 0x70108086: 126 return "Intel PIIX3 ATA controller"; 127 128 case 0x71118086: 129 case 0x71998086: 130 case 0x84ca8086: 131 return "Intel PIIX4 ATA33 controller"; 132 133 case 0x24218086: 134 return "Intel ICH0 ATA33 controller"; 135 136 case 0x24118086: 137 case 0x76018086: 138 return "Intel ICH ATA66 controller"; 139 140 case 0x244a8086: 141 case 0x244b8086: 142 return "Intel ICH2 ATA100 controller"; 143 144 case 0x248a8086: 145 case 0x248b8086: 146 return "Intel ICH3 ATA100 controller"; 147 148 case 0x522910b9: 149 if (pci_get_revid(dev) >= 0xc4) 150 return "AcerLabs Aladdin ATA100 controller"; 151 else if (pci_get_revid(dev) >= 0xc2) 152 return "AcerLabs Aladdin ATA66 controller"; 153 else if (pci_get_revid(dev) >= 0x20) 154 return "AcerLabs Aladdin ATA33 controller"; 155 else 156 return "AcerLabs Aladdin ATA controller"; 157 158 case 0x05711106: 159 if (ata_find_dev(dev, 0x05861106, 0x02)) 160 return "VIA 82C586 ATA33 controller"; 161 if (ata_find_dev(dev, 0x05861106, 0)) 162 return "VIA 82C586 ATA controller"; 163 if (ata_find_dev(dev, 0x05961106, 0x12)) 164 return "VIA 82C596 ATA66 controller"; 165 if (ata_find_dev(dev, 0x05961106, 0)) 166 return "VIA 82C596 ATA33 controller"; 167 if (ata_find_dev(dev, 0x06861106, 0x40)) 168 return "VIA 82C686 ATA100 controller"; 169 if (ata_find_dev(dev, 0x06861106, 0x10)) 170 return "VIA 82C686 ATA66 controller"; 171 if (ata_find_dev(dev, 0x06861106, 0)) 172 return "VIA 82C686 ATA33 controller"; 173 if (ata_find_dev(dev, 0x82311106, 0)) 174 return "VIA 8231 ATA100 controller"; 175 if (ata_find_dev(dev, 0x30741106, 0) || 176 ata_find_dev(dev, 0x31091106, 0)) 177 return "VIA 8233 ATA100 controller"; 178 if (ata_find_dev(dev, 0x31471106, 0)) 179 return "VIA 8233 ATA133 controller"; 180 return "VIA Apollo ATA controller"; 181 182 case 0x55131039: 183 if (ata_find_dev(dev, 0x06301039, 0x30) || 184 ata_find_dev(dev, 0x06331039, 0x00) || 185 ata_find_dev(dev, 0x06351039, 0x00) || 186 ata_find_dev(dev, 0x06401039, 0x00) || 187 ata_find_dev(dev, 0x06451039, 0x00) || 188 ata_find_dev(dev, 0x06501039, 0x00) || 189 ata_find_dev(dev, 0x07301039, 0x00) || 190 ata_find_dev(dev, 0x07331039, 0x00) || 191 ata_find_dev(dev, 0x07351039, 0x00) || 192 ata_find_dev(dev, 0x07401039, 0x00) || 193 ata_find_dev(dev, 0x07451039, 0x00) || 194 ata_find_dev(dev, 0x07501039, 0x00)) 195 return "SiS 5591 ATA100 controller"; 196 else if (ata_find_dev(dev, 0x05301039, 0x00) || 197 ata_find_dev(dev, 0x05401039, 0x00) || 198 ata_find_dev(dev, 0x06201039, 0x00) || 199 ata_find_dev(dev, 0x06301039, 0x00)) 200 return "SiS 5591 ATA66 controller"; 201 else 202 return "SiS 5591 ATA33 controller"; 203 204 case 0x06491095: 205 return "CMD 649 ATA100 controller"; 206 207 case 0x06481095: 208 return "CMD 648 ATA66 controller"; 209 210 case 0x06461095: 211 return "CMD 646 ATA controller"; 212 213 case 0xc6931080: 214 if (pci_get_subclass(dev) == PCIS_STORAGE_IDE) 215 return "Cypress 82C693 ATA controller"; 216 return NULL; 217 218 case 0x01021078: 219 return "Cyrix 5530 ATA33 controller"; 220 221 case 0x74091022: 222 return "AMD 756 ATA66 controller"; 223 224 case 0x74111022: 225 return "AMD 766 ATA100 controller"; 226 227 case 0x74411022: 228 return "AMD 768 ATA100 controller"; 229 230 case 0x02111166: 231 return "ServerWorks ROSB4 ATA33 controller"; 232 233 case 0x02121166: 234 if (pci_get_revid(dev) >= 0x92) 235 return "ServerWorks CSB5 ATA100 controller"; 236 else 237 return "ServerWorks CSB5 ATA66 controller"; 238 239 case 0x4d33105a: 240 return "Promise ATA33 controller"; 241 242 case 0x4d38105a: 243 return "Promise ATA66 controller"; 244 245 case 0x0d30105a: 246 case 0x4d30105a: 247 return "Promise ATA100 controller"; 248 249 case 0x4d68105a: 250 case 0x6268105a: 251 if (pci_get_devid(GRANDPARENT(dev)) == 0x00221011 && 252 pci_get_class(GRANDPARENT(dev)) == PCIC_BRIDGE) { 253 static long start = 0, end = 0; 254 255 /* we belive we are on a TX4, now do our (simple) magic */ 256 if (pci_get_slot(dev) == 1) { 257 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end); 258 return "Promise TX4 ATA100 controller (channel 0+1)"; 259 } 260 else if (pci_get_slot(dev) == 2 && start && end) { 261 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end); 262 start = end = 0; 263 return "Promise TX4 ATA100 controller (channel 2+3)"; 264 } 265 else 266 start = end = 0; 267 } 268 return "Promise TX2 ATA100 controller"; 269 270 case 0x4d69105a: 271 return "Promise TX2 ATA133 controller"; 272 273 case 0x00041103: 274 switch (pci_get_revid(dev)) { 275 case 0x00: 276 case 0x01: 277 return "HighPoint HPT366 ATA66 controller"; 278 case 0x02: 279 return "HighPoint HPT368 ATA66 controller"; 280 case 0x03: 281 case 0x04: 282 return "HighPoint HPT370 ATA100 controller"; 283 case 0x05: 284 return "HighPoint HPT372 ATA133 controller"; 285 } 286 return NULL; 287 288 case 0x00051103: 289 switch (pci_get_revid(dev)) { 290 case 0x01: 291 return "HighPoint HPT372 ATA133 controller"; 292 } 293 return NULL; 294 295 case 0x00081103: 296 switch (pci_get_revid(dev)) { 297 case 0x07: 298 return "HighPoint HPT374 ATA133 controller"; 299 } 300 return NULL; 301 302 case 0x000116ca: 303 return "Cenatek Rocket Drive controller"; 304 305 /* unsupported but known chipsets, generic DMA only */ 306 case 0x10001042: 307 case 0x10011042: 308 return "RZ 100? ATA controller !WARNING! buggy chip data loss possible"; 309 310 case 0x06401095: 311 return "CMD 640 ATA controller !WARNING! buggy chip data loss possible"; 312 313 /* unknown chipsets, try generic DMA if it seems possible */ 314 default: 315 if (pci_get_class(dev) == PCIC_STORAGE && 316 (pci_get_subclass(dev) == PCIS_STORAGE_IDE)) 317 return "Generic PCI ATA controller"; 318 } 319 return NULL; 320 } 321 322 static int 323 ata_pci_probe(device_t dev) 324 { 325 const char *desc = ata_pci_match(dev); 326 327 if (desc) { 328 device_set_desc(dev, desc); 329 return 0; 330 } 331 else 332 return ENXIO; 333 } 334 335 static int 336 ata_pci_add_child(device_t dev, int unit) 337 { 338 device_t child; 339 340 /* check if this is located at one of the std addresses */ 341 if (ATA_MASTERDEV(dev)) { 342 if (!(child = device_add_child(dev, "ata", unit))) 343 return ENOMEM; 344 } 345 else { 346 if (!(child = 347 device_add_child(dev, "ata", 348 devclass_find_free_unit(ata_devclass, 2)))) 349 return ENOMEM; 350 } 351 return 0; 352 } 353 354 static int 355 ata_pci_attach(device_t dev) 356 { 357 struct ata_pci_controller *controller = device_get_softc(dev); 358 u_int8_t class, subclass; 359 u_int32_t type, cmd; 360 int rid; 361 362 /* set up vendor-specific stuff */ 363 type = pci_get_devid(dev); 364 class = pci_get_class(dev); 365 subclass = pci_get_subclass(dev); 366 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 367 368 if (!(cmd & PCIM_CMD_PORTEN)) { 369 device_printf(dev, "ATA channel disabled by BIOS\n"); 370 return 0; 371 } 372 373 /* is busmastering supported ? */ 374 if ((cmd & (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) == 375 (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) { 376 377 /* is there a valid port range to connect to ? */ 378 rid = 0x20; 379 controller->bmio = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 380 0, ~0, 1, RF_ACTIVE); 381 if (!controller->bmio) 382 device_printf(dev, "Busmastering DMA not configured\n"); 383 } 384 else 385 device_printf(dev, "Busmastering DMA not supported\n"); 386 387 /* do extra chipset specific setups */ 388 switch (type) { 389 390 case 0x522910b9: /* AcerLabs Aladdin need to activate the ATAPI FIFO */ 391 pci_write_config(dev, 0x53, 392 (pci_read_config(dev, 0x53, 1) & ~0x01) | 0x02, 1); 393 break; 394 395 case 0x4d38105a: /* Promise 66 & 100 (before TX2) need the clock changed */ 396 case 0x4d30105a: 397 case 0x0d30105a: 398 ATA_OUTB(controller->bmio, 0x11, ATA_INB(controller->bmio, 0x11)|0x0a); 399 /* FALLTHROUGH */ 400 401 case 0x4d33105a: /* Promise (before TX2) need burst mode turned on */ 402 ATA_OUTB(controller->bmio, 0x1f, ATA_INB(controller->bmio, 0x1f)|0x01); 403 break; 404 405 case 0x00041103: /* HighPoint HPT366/368/370/372 default setup */ 406 if (pci_get_revid(dev) < 2) { /* HPT 366 */ 407 /* turn off interrupt prediction */ 408 pci_write_config(dev, 0x51, 409 (pci_read_config(dev, 0x51, 1) & ~0x80), 1); 410 break; 411 } 412 /* turn off interrupt prediction */ 413 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1); 414 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1); 415 416 /* turn on interrupts */ 417 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1); 418 419 /* set clocks etc */ 420 pci_write_config(dev, 0x5b, 0x22, 1); 421 break; 422 423 case 0x00051103: /* HighPoint HPT372 default setup */ 424 case 0x00081103: /* HighPoint HPT374 default setup */ 425 /* turn off interrupt prediction */ 426 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1); 427 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1); 428 429 /* turn on interrupts */ 430 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1); 431 432 /* set clocks etc */ 433 pci_write_config(dev, 0x5b, 434 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1); 435 break; 436 437 case 0x05711106: /* VIA 82C586, '596, '686 default setup */ 438 /* prepare for ATA-66 on the 82C686a and 82C596b */ 439 if ((ata_find_dev(dev, 0x06861106, 0x10) && 440 !ata_find_dev(dev, 0x06861106, 0x40)) || 441 ata_find_dev(dev, 0x05961106, 0x12)) 442 pci_write_config(dev, 0x50, 0x030b030b, 4); 443 444 /* the southbridge might need the data corruption fix */ 445 if (ata_find_dev(dev, 0x06861106, 0x40) || 446 ata_find_dev(dev, 0x82311106, 0x10)) 447 ata_via_southbridge_fixup(dev); 448 /* FALLTHROUGH */ 449 450 case 0x74091022: /* AMD 756 default setup */ 451 case 0x74111022: /* AMD 766 default setup */ 452 case 0x74411022: /* AMD 768 default setup */ 453 /* set prefetch, postwrite */ 454 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1); 455 456 /* set fifo configuration half'n'half */ 457 pci_write_config(dev, 0x43, 458 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1); 459 460 /* set status register read retry */ 461 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1); 462 463 /* set DMA read & end-of-sector fifo flush */ 464 pci_write_config(dev, 0x46, 465 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1); 466 467 /* set sector size */ 468 pci_write_config(dev, 0x60, DEV_BSIZE, 2); 469 pci_write_config(dev, 0x68, DEV_BSIZE, 2); 470 break; 471 472 case 0x02111166: /* ServerWorks ROSB4 enable UDMA33 */ 473 pci_write_config(dev, 0x64, 474 (pci_read_config(dev, 0x64, 4) & ~0x00002000) | 475 0x00004000, 4); 476 break; 477 478 case 0x02121166: /* ServerWorks CSB5 enable UDMA66/100 depending on rev */ 479 pci_write_config(dev, 0x5a, 480 (pci_read_config(dev, 0x5a, 1) & ~0x40) | 481 (pci_get_revid(dev) >= 0x92) ? 0x03 : 0x02, 1); 482 break; 483 484 case 0x10001042: /* RZ 100? known bad, no DMA */ 485 case 0x10011042: 486 case 0x06401095: /* CMD 640 known bad, no DMA */ 487 controller->bmio = NULL; 488 device_printf(dev, "Busmastering DMA disabled\n"); 489 } 490 491 if (controller->bmio) { 492 controller->bmaddr = rman_get_start(controller->bmio); 493 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev, 494 SYS_RES_IOPORT, rid, controller->bmio); 495 controller->bmio = NULL; 496 } 497 498 /* 499 * the Cypress chip is a mess, it contains two ATA functions, but 500 * both channels are visible on the first one. 501 * simply ignore the second function for now, as the right 502 * solution (ignoring the second channel on the first function) 503 * doesn't work with the crappy ATA interrupt setup on the alpha. 504 */ 505 if (pci_get_devid(dev) == 0xc6931080 && pci_get_function(dev) > 1) 506 return 0; 507 508 ata_pci_add_child(dev, 0); 509 510 if (ATA_MASTERDEV(dev) || pci_read_config(dev, 0x18, 4) & IOMASK) 511 ata_pci_add_child(dev, 1); 512 513 return bus_generic_attach(dev); 514 } 515 516 static int 517 ata_pci_intr(struct ata_channel *ch) 518 { 519 u_int8_t dmastat; 520 521 /* 522 * since we might share the IRQ with another device, and in some 523 * cases with our twin channel, we only want to process interrupts 524 * that we know this channel generated. 525 */ 526 switch (ch->chiptype) { 527 case 0x00041103: /* HighPoint HPT366/368/370/372 */ 528 case 0x00051103: /* HighPoint HPT372 */ 529 case 0x00081103: /* HighPoint HPT374 */ 530 if (((dmastat = ata_dmastatus(ch)) & 531 (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) != ATA_BMSTAT_INTERRUPT) 532 return 1; 533 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT); 534 DELAY(1); 535 return 0; 536 537 case 0x06481095: /* CMD 648 */ 538 case 0x06491095: /* CMD 649 */ 539 if (!(pci_read_config(device_get_parent(ch->dev), 0x71, 1) & 540 (ch->unit ? 0x08 : 0x04))) 541 return 1; 542 break; 543 544 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */ 545 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */ 546 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */ 547 case 0x0d30105a: /* Promise OEM ATA100 */ 548 if (!(ATA_INL(ch->r_bmio, (ch->unit ? 0x14 : 0x1c)) & 549 (ch->unit ? 0x00004000 : 0x00000400))) 550 return 1; 551 break; 552 553 case 0x4d68105a: /* Promise TX2 ATA100 */ 554 case 0x6268105a: /* Promise TX2 ATA100 */ 555 case 0x4d69105a: /* Promise TX2 ATA133 */ 556 ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b); 557 if (!(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x20)) 558 return 1; 559 break; 560 } 561 562 if (ch->flags & ATA_DMA_ACTIVE) { 563 if (!((dmastat = ata_dmastatus(ch)) & ATA_BMSTAT_INTERRUPT)) 564 return 1; 565 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT); 566 DELAY(1); 567 } 568 return 0; 569 } 570 571 static int 572 ata_pci_print_child(device_t dev, device_t child) 573 { 574 struct ata_channel *ch = device_get_softc(child); 575 int retval = 0; 576 577 retval += bus_print_child_header(dev, child); 578 retval += printf(": at 0x%lx", rman_get_start(ch->r_io)); 579 580 if (ATA_MASTERDEV(dev)) 581 retval += printf(" irq %d", 14 + ch->unit); 582 583 retval += bus_print_child_footer(dev, child); 584 585 return retval; 586 } 587 588 static struct resource * 589 ata_pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 590 u_long start, u_long end, u_long count, u_int flags) 591 { 592 struct ata_pci_controller *controller = device_get_softc(dev); 593 struct resource *res = NULL; 594 int unit = ((struct ata_channel *)device_get_softc(child))->unit; 595 int myrid; 596 597 if (type == SYS_RES_IOPORT) { 598 switch (*rid) { 599 case ATA_IOADDR_RID: 600 if (ATA_MASTERDEV(dev)) { 601 myrid = 0; 602 start = (unit ? ATA_SECONDARY : ATA_PRIMARY); 603 end = start + ATA_IOSIZE - 1; 604 count = ATA_IOSIZE; 605 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 606 SYS_RES_IOPORT, &myrid, 607 start, end, count, flags); 608 } 609 else { 610 myrid = 0x10 + 8 * unit; 611 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev, 612 SYS_RES_IOPORT, &myrid, 613 start, end, count, flags); 614 } 615 break; 616 617 case ATA_ALTADDR_RID: 618 if (ATA_MASTERDEV(dev)) { 619 myrid = 0; 620 start = (unit ? ATA_SECONDARY : ATA_PRIMARY) + ATA_ALTOFFSET; 621 end = start + ATA_ALTIOSIZE - 1; 622 count = ATA_ALTIOSIZE; 623 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 624 SYS_RES_IOPORT, &myrid, 625 start, end, count, flags); 626 } 627 else { 628 myrid = 0x14 + 8 * unit; 629 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev, 630 SYS_RES_IOPORT, &myrid, 631 start, end, count, flags); 632 if (res) { 633 start = rman_get_start(res) + 2; 634 end = rman_get_start(res) + ATA_ALTIOSIZE - 1; 635 count = ATA_ALTIOSIZE; 636 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev, 637 SYS_RES_IOPORT, myrid, res); 638 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev, 639 SYS_RES_IOPORT, &myrid, 640 start, end, count, flags); 641 } 642 } 643 break; 644 645 case ATA_BMADDR_RID: 646 if (controller->bmaddr) { 647 myrid = 0x20; 648 start = (unit == 0 ? 649 controller->bmaddr : controller->bmaddr+ATA_BMIOSIZE); 650 end = start + ATA_BMIOSIZE - 1; 651 count = ATA_BMIOSIZE; 652 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 653 SYS_RES_IOPORT, &myrid, 654 start, end, count, flags); 655 } 656 } 657 return res; 658 } 659 660 if (type == SYS_RES_IRQ && *rid == ATA_IRQ_RID) { 661 if (ATA_MASTERDEV(dev)) { 662 #ifdef __alpha__ 663 return alpha_platform_alloc_ide_intr(unit); 664 #else 665 int irq = (unit == 0 ? 14 : 15); 666 667 return BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 668 SYS_RES_IRQ, rid, irq, irq, 1, flags); 669 #endif 670 } 671 else { 672 /* primary and secondary channels share interrupt, keep track */ 673 if (!controller->irq) 674 controller->irq = BUS_ALLOC_RESOURCE(device_get_parent(dev), 675 dev, SYS_RES_IRQ, 676 rid, 0, ~0, 1, flags); 677 controller->irqcnt++; 678 return controller->irq; 679 } 680 } 681 return 0; 682 } 683 684 static int 685 ata_pci_release_resource(device_t dev, device_t child, int type, int rid, 686 struct resource *r) 687 { 688 struct ata_pci_controller *controller = device_get_softc(dev); 689 int unit = ((struct ata_channel *)device_get_softc(child))->unit; 690 691 if (type == SYS_RES_IOPORT) { 692 switch (rid) { 693 case ATA_IOADDR_RID: 694 if (ATA_MASTERDEV(dev)) 695 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 696 SYS_RES_IOPORT, 0x0, r); 697 else 698 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev, 699 SYS_RES_IOPORT, 0x10 + 8 * unit, r); 700 break; 701 702 case ATA_ALTADDR_RID: 703 if (ATA_MASTERDEV(dev)) 704 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 705 SYS_RES_IOPORT, 0x0, r); 706 else 707 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev, 708 SYS_RES_IOPORT, 0x14 + 8 * unit, r); 709 break; 710 711 case ATA_BMADDR_RID: 712 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 713 SYS_RES_IOPORT, 0x20, r); 714 default: 715 return ENOENT; 716 } 717 } 718 if (type == SYS_RES_IRQ) { 719 if (rid != ATA_IRQ_RID) 720 return ENOENT; 721 722 if (ATA_MASTERDEV(dev)) { 723 #ifdef __alpha__ 724 return alpha_platform_release_ide_intr(unit, r); 725 #else 726 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 727 SYS_RES_IRQ, rid, r); 728 #endif 729 } 730 else { 731 /* primary and secondary channels share interrupt, keep track */ 732 if (--controller->irqcnt) 733 return 0; 734 controller->irq = NULL; 735 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev, 736 SYS_RES_IRQ, rid, r); 737 } 738 } 739 return EINVAL; 740 } 741 742 static int 743 ata_pci_setup_intr(device_t dev, device_t child, struct resource *irq, 744 int flags, driver_intr_t *intr, void *arg, 745 void **cookiep) 746 { 747 if (ATA_MASTERDEV(dev)) { 748 #ifdef __alpha__ 749 return alpha_platform_setup_ide_intr(child, irq, intr, arg, cookiep); 750 #else 751 return BUS_SETUP_INTR(device_get_parent(dev), child, irq, 752 flags, intr, arg, cookiep); 753 #endif 754 } 755 else 756 return BUS_SETUP_INTR(device_get_parent(dev), dev, irq, 757 flags, intr, arg, cookiep); 758 } 759 760 static int 761 ata_pci_teardown_intr(device_t dev, device_t child, struct resource *irq, 762 void *cookie) 763 { 764 if (ATA_MASTERDEV(dev)) { 765 #ifdef __alpha__ 766 return alpha_platform_teardown_ide_intr(child, irq, cookie); 767 #else 768 return BUS_TEARDOWN_INTR(device_get_parent(dev), child, irq, cookie); 769 #endif 770 } 771 else 772 return BUS_TEARDOWN_INTR(device_get_parent(dev), dev, irq, cookie); 773 } 774 775 static device_method_t ata_pci_methods[] = { 776 /* device interface */ 777 DEVMETHOD(device_probe, ata_pci_probe), 778 DEVMETHOD(device_attach, ata_pci_attach), 779 DEVMETHOD(device_shutdown, bus_generic_shutdown), 780 DEVMETHOD(device_suspend, bus_generic_suspend), 781 DEVMETHOD(device_resume, bus_generic_resume), 782 783 /* bus methods */ 784 DEVMETHOD(bus_print_child, ata_pci_print_child), 785 DEVMETHOD(bus_alloc_resource, ata_pci_alloc_resource), 786 DEVMETHOD(bus_release_resource, ata_pci_release_resource), 787 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 788 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 789 DEVMETHOD(bus_setup_intr, ata_pci_setup_intr), 790 DEVMETHOD(bus_teardown_intr, ata_pci_teardown_intr), 791 { 0, 0 } 792 }; 793 794 static driver_t ata_pci_driver = { 795 "atapci", 796 ata_pci_methods, 797 sizeof(struct ata_pci_controller), 798 }; 799 800 static devclass_t ata_pci_devclass; 801 802 DRIVER_MODULE(atapci, pci, ata_pci_driver, ata_pci_devclass, 0, 0); 803 804 static int 805 ata_pcisub_probe(device_t dev) 806 { 807 struct ata_channel *ch = device_get_softc(dev); 808 device_t *children; 809 int count, i; 810 811 /* find channel number on this controller */ 812 device_get_children(device_get_parent(dev), &children, &count); 813 for (i = 0; i < count; i++) { 814 if (children[i] == dev) 815 ch->unit = i; 816 } 817 free(children, M_TEMP); 818 ch->chiptype = pci_get_devid(device_get_parent(dev)); 819 ch->intr_func = ata_pci_intr; 820 return ata_probe(dev); 821 } 822 823 static device_method_t ata_pcisub_methods[] = { 824 /* device interface */ 825 DEVMETHOD(device_probe, ata_pcisub_probe), 826 DEVMETHOD(device_attach, ata_attach), 827 DEVMETHOD(device_detach, ata_detach), 828 DEVMETHOD(device_resume, ata_resume), 829 { 0, 0 } 830 }; 831 832 static driver_t ata_pcisub_driver = { 833 "ata", 834 ata_pcisub_methods, 835 sizeof(struct ata_channel), 836 }; 837 838 DRIVER_MODULE(ata, atapci, ata_pcisub_driver, ata_devclass, 0, 0); 839