1 /*- 2 * Copyright (c) 1998,1999,2000,2001,2002 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #include "opt_ata.h" 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/disk.h> 36 #include <sys/module.h> 37 #include <sys/bus.h> 38 #include <sys/bio.h> 39 #include <sys/malloc.h> 40 #include <sys/devicestat.h> 41 #include <sys/sysctl.h> 42 #include <machine/stdarg.h> 43 #include <machine/resource.h> 44 #include <machine/bus.h> 45 #ifdef __alpha__ 46 #include <machine/md_var.h> 47 #endif 48 #include <sys/rman.h> 49 #include <pci/pcivar.h> 50 #include <pci/pcireg.h> 51 #include <dev/ata/ata-all.h> 52 53 /* device structures */ 54 struct ata_pci_controller { 55 struct resource *bmio; 56 int bmaddr; 57 struct resource *irq; 58 int irqcnt; 59 }; 60 61 /* misc defines */ 62 #define IOMASK 0xfffffffc 63 #define GRANDPARENT(dev) device_get_parent(device_get_parent(dev)) 64 #define ATA_MASTERDEV(dev) ((pci_get_progif(dev) & 0x80) && \ 65 (pci_get_progif(dev) & 0x05) != 0x05) 66 67 int 68 ata_find_dev(device_t dev, u_int32_t devid, u_int32_t revid) 69 { 70 device_t *children; 71 int nchildren, i; 72 73 if (device_get_children(device_get_parent(dev), &children, &nchildren)) 74 return 0; 75 76 for (i = 0; i < nchildren; i++) { 77 if (pci_get_devid(children[i]) == devid && 78 pci_get_revid(children[i]) >= revid) { 79 free(children, M_TEMP); 80 return 1; 81 } 82 } 83 free(children, M_TEMP); 84 return 0; 85 } 86 87 static void 88 ata_via_southbridge_fixup(device_t dev) 89 { 90 device_t *children; 91 int nchildren, i; 92 93 if (device_get_children(device_get_parent(dev), &children, &nchildren)) 94 return; 95 96 for (i = 0; i < nchildren; i++) { 97 if (pci_get_devid(children[i]) == 0x03051106 || /* VIA VT8363 */ 98 pci_get_devid(children[i]) == 0x03911106 || /* VIA VT8371 */ 99 pci_get_devid(children[i]) == 0x31021106 || /* VIA VT8662 */ 100 pci_get_devid(children[i]) == 0x31121106) { /* VIA VT8361 */ 101 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1); 102 103 if ((reg76 & 0xf0) != 0xd0) { 104 device_printf(dev, 105 "Correcting VIA config for southbridge data corruption bug\n"); 106 pci_write_config(children[i], 0x75, 0x80, 1); 107 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1); 108 } 109 break; 110 } 111 } 112 free(children, M_TEMP); 113 } 114 115 static const char * 116 ata_pci_match(device_t dev) 117 { 118 if (pci_get_class(dev) != PCIC_STORAGE) 119 return NULL; 120 121 switch (pci_get_devid(dev)) { 122 /* supported chipsets */ 123 case 0x12308086: 124 return "Intel PIIX ATA controller"; 125 126 case 0x70108086: 127 return "Intel PIIX3 ATA controller"; 128 129 case 0x71118086: 130 case 0x71998086: 131 case 0x84ca8086: 132 return "Intel PIIX4 ATA33 controller"; 133 134 case 0x24218086: 135 return "Intel ICH0 ATA33 controller"; 136 137 case 0x24118086: 138 case 0x76018086: 139 return "Intel ICH ATA66 controller"; 140 141 case 0x244a8086: 142 case 0x244b8086: 143 return "Intel ICH2 ATA100 controller"; 144 145 case 0x248a8086: 146 case 0x248b8086: 147 return "Intel ICH3 ATA100 controller"; 148 149 case 0x522910b9: 150 if (pci_get_revid(dev) >= 0xc4) 151 return "AcerLabs Aladdin ATA100 controller"; 152 else if (pci_get_revid(dev) >= 0xc2) 153 return "AcerLabs Aladdin ATA66 controller"; 154 else if (pci_get_revid(dev) >= 0x20) 155 return "AcerLabs Aladdin ATA33 controller"; 156 else 157 return "AcerLabs Aladdin ATA controller"; 158 159 case 0x05711106: 160 if (ata_find_dev(dev, 0x05861106, 0x02)) 161 return "VIA 82C586 ATA33 controller"; 162 if (ata_find_dev(dev, 0x05861106, 0)) 163 return "VIA 82C586 ATA controller"; 164 if (ata_find_dev(dev, 0x05961106, 0x12)) 165 return "VIA 82C596 ATA66 controller"; 166 if (ata_find_dev(dev, 0x05961106, 0)) 167 return "VIA 82C596 ATA33 controller"; 168 if (ata_find_dev(dev, 0x06861106, 0x40)) 169 return "VIA 82C686 ATA100 controller"; 170 if (ata_find_dev(dev, 0x06861106, 0x10)) 171 return "VIA 82C686 ATA66 controller"; 172 if (ata_find_dev(dev, 0x06861106, 0)) 173 return "VIA 82C686 ATA33 controller"; 174 if (ata_find_dev(dev, 0x82311106, 0)) 175 return "VIA 8231 ATA100 controller"; 176 if (ata_find_dev(dev, 0x30741106, 0) || 177 ata_find_dev(dev, 0x31091106, 0)) 178 return "VIA 8233 ATA100 controller"; 179 if (ata_find_dev(dev, 0x31471106, 0)) 180 return "VIA 8233 ATA133 controller"; 181 return "VIA Apollo ATA controller"; 182 183 case 0x55131039: 184 if (ata_find_dev(dev, 0x06301039, 0x30) || 185 ata_find_dev(dev, 0x06331039, 0) || 186 ata_find_dev(dev, 0x06351039, 0) || 187 ata_find_dev(dev, 0x06401039, 0) || 188 ata_find_dev(dev, 0x06451039, 0) || 189 ata_find_dev(dev, 0x06501039, 0) || 190 ata_find_dev(dev, 0x07301039, 0) || 191 ata_find_dev(dev, 0x07331039, 0) || 192 ata_find_dev(dev, 0x07351039, 0) || 193 ata_find_dev(dev, 0x07401039, 0) || 194 ata_find_dev(dev, 0x07451039, 0) || 195 ata_find_dev(dev, 0x07501039, 0)) 196 return "SiS 5591 ATA100 controller"; 197 else if (ata_find_dev(dev, 0x05301039, 0) || 198 ata_find_dev(dev, 0x05401039, 0) || 199 ata_find_dev(dev, 0x06201039, 0) || 200 ata_find_dev(dev, 0x06301039, 0)) 201 return "SiS 5591 ATA66 controller"; 202 else 203 return "SiS 5591 ATA33 controller"; 204 205 case 0x06491095: 206 return "CMD 649 ATA100 controller"; 207 208 case 0x06481095: 209 return "CMD 648 ATA66 controller"; 210 211 case 0x06461095: 212 return "CMD 646 ATA controller"; 213 214 case 0xc6931080: 215 if (pci_get_subclass(dev) == PCIS_STORAGE_IDE) 216 return "Cypress 82C693 ATA controller"; 217 return NULL; 218 219 case 0x01021078: 220 return "Cyrix 5530 ATA33 controller"; 221 222 case 0x74091022: 223 return "AMD 756 ATA66 controller"; 224 225 case 0x74111022: 226 return "AMD 766 ATA100 controller"; 227 228 case 0x74411022: 229 return "AMD 768 ATA100 controller"; 230 231 case 0x01bc10de: 232 return "nVIDIA nForce ATA100 controller"; 233 234 case 0x02111166: 235 return "ServerWorks ROSB4 ATA33 controller"; 236 237 case 0x02121166: 238 if (pci_get_revid(dev) >= 0x92) 239 return "ServerWorks CSB5 ATA100 controller"; 240 else 241 return "ServerWorks CSB5 ATA66 controller"; 242 243 case 0x4d33105a: 244 return "Promise ATA33 controller"; 245 246 case 0x0d38105a: 247 case 0x4d38105a: 248 return "Promise ATA66 controller"; 249 250 case 0x0d30105a: 251 case 0x4d30105a: 252 return "Promise ATA100 controller"; 253 254 case 0x4d68105a: 255 case 0x6268105a: 256 if (pci_get_devid(GRANDPARENT(dev)) == 0x00221011 && 257 pci_get_class(GRANDPARENT(dev)) == PCIC_BRIDGE) { 258 static long start = 0, end = 0; 259 260 /* we belive we are on a TX4, now do our (simple) magic */ 261 if (pci_get_slot(dev) == 1) { 262 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end); 263 return "Promise TX4 ATA100 controller (channel 0+1)"; 264 } 265 else if (pci_get_slot(dev) == 2 && start && end) { 266 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end); 267 start = end = 0; 268 return "Promise TX4 ATA100 controller (channel 2+3)"; 269 } 270 else 271 start = end = 0; 272 } 273 return "Promise TX2 ATA100 controller"; 274 275 case 0x4d69105a: 276 case 0x5275105a: 277 case 0x6269105a: 278 return "Promise TX2 ATA133 controller"; 279 280 case 0x00041103: 281 switch (pci_get_revid(dev)) { 282 case 0x00: 283 case 0x01: 284 return "HighPoint HPT366 ATA66 controller"; 285 case 0x02: 286 return "HighPoint HPT368 ATA66 controller"; 287 case 0x03: 288 case 0x04: 289 return "HighPoint HPT370 ATA100 controller"; 290 case 0x05: 291 return "HighPoint HPT372 ATA133 controller"; 292 } 293 return NULL; 294 295 case 0x00051103: 296 switch (pci_get_revid(dev)) { 297 case 0x01: 298 return "HighPoint HPT372 ATA133 controller"; 299 } 300 return NULL; 301 302 case 0x00081103: 303 switch (pci_get_revid(dev)) { 304 case 0x07: 305 return "HighPoint HPT374 ATA133 controller"; 306 } 307 return NULL; 308 309 case 0x000116ca: 310 return "Cenatek Rocket Drive controller"; 311 312 /* unsupported but known chipsets, generic DMA only */ 313 case 0x10001042: 314 case 0x10011042: 315 return "RZ 100? ATA controller !WARNING! buggy chip data loss possible"; 316 317 case 0x06401095: 318 return "CMD 640 ATA controller !WARNING! buggy chip data loss possible"; 319 320 /* unknown chipsets, try generic DMA if it seems possible */ 321 default: 322 if (pci_get_class(dev) == PCIC_STORAGE && 323 (pci_get_subclass(dev) == PCIS_STORAGE_IDE)) 324 return "Generic PCI ATA controller"; 325 } 326 return NULL; 327 } 328 329 static int 330 ata_pci_probe(device_t dev) 331 { 332 const char *desc = ata_pci_match(dev); 333 334 if (desc) { 335 device_set_desc(dev, desc); 336 return 0; 337 } 338 else 339 return ENXIO; 340 } 341 342 static int 343 ata_pci_add_child(device_t dev, int unit) 344 { 345 device_t child; 346 347 /* check if this is located at one of the std addresses */ 348 if (ATA_MASTERDEV(dev)) { 349 if (!(child = device_add_child(dev, "ata", unit))) 350 return ENOMEM; 351 } 352 else { 353 if (!(child = 354 device_add_child(dev, "ata", 355 devclass_find_free_unit(ata_devclass, 2)))) 356 return ENOMEM; 357 } 358 return 0; 359 } 360 361 static int 362 ata_pci_attach(device_t dev) 363 { 364 struct ata_pci_controller *controller = device_get_softc(dev); 365 u_int8_t class, subclass; 366 u_int32_t type, cmd; 367 int rid; 368 369 /* set up vendor-specific stuff */ 370 type = pci_get_devid(dev); 371 class = pci_get_class(dev); 372 subclass = pci_get_subclass(dev); 373 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 374 375 if (!(cmd & PCIM_CMD_PORTEN)) { 376 device_printf(dev, "ATA channel disabled by BIOS\n"); 377 return 0; 378 } 379 380 #ifdef __sparc64__ 381 if (!(cmd & PCIM_CMD_BUSMASTEREN)) { 382 pci_write_config(dev, PCIR_COMMAND, cmd | PCIM_CMD_BUSMASTEREN, 2); 383 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 384 } 385 #endif 386 /* is busmastering supported ? */ 387 if ((cmd & (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) == 388 (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) { 389 390 /* is there a valid port range to connect to ? */ 391 rid = 0x20; 392 controller->bmio = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 393 0, ~0, 1, RF_ACTIVE); 394 if (!controller->bmio) 395 device_printf(dev, "Busmastering DMA not configured\n"); 396 } 397 else 398 device_printf(dev, "Busmastering DMA not supported\n"); 399 400 /* do extra chipset specific setups */ 401 switch (type) { 402 403 case 0x522910b9: /* AcerLabs Aladdin need to activate the ATAPI FIFO */ 404 pci_write_config(dev, 0x53, 405 (pci_read_config(dev, 0x53, 1) & ~0x01) | 0x02, 1); 406 break; 407 408 case 0x0d30105a: /* Promise 66 & 100 (before TX2) need the clock changed */ 409 case 0x4d30105a: 410 case 0x0d38105a: 411 case 0x4d38105a: 412 ATA_OUTB(controller->bmio, 0x11, ATA_INB(controller->bmio, 0x11)|0x0a); 413 /* FALLTHROUGH */ 414 415 case 0x4d33105a: /* Promise (before TX2) need burst mode turned on */ 416 ATA_OUTB(controller->bmio, 0x1f, ATA_INB(controller->bmio, 0x1f)|0x01); 417 break; 418 419 case 0x00041103: /* HighPoint HPT366/368/370/372 default setup */ 420 if (pci_get_revid(dev) < 2) { /* HPT366 */ 421 /* turn off interrupt prediction */ 422 pci_write_config(dev, 0x51, 423 (pci_read_config(dev, 0x51, 1) & ~0x80), 1); 424 break; 425 } 426 if (pci_get_revid(dev) < 5) { /* HPT368/370 */ 427 /* turn off interrupt prediction */ 428 pci_write_config(dev, 0x51, 429 (pci_read_config(dev, 0x51, 1) & ~0x03), 1); 430 pci_write_config(dev, 0x55, 431 (pci_read_config(dev, 0x55, 1) & ~0x03), 1); 432 433 /* turn on interrupts */ 434 pci_write_config(dev, 0x5a, 435 (pci_read_config(dev, 0x5a, 1) & ~0x10), 1); 436 437 /* set clocks etc */ 438 pci_write_config(dev, 0x5b, 0x22, 1); 439 break; 440 } 441 /* FALLTHROUGH */ 442 443 case 0x00051103: /* HighPoint HPT372 default setup */ 444 case 0x00081103: /* HighPoint HPT374 default setup */ 445 /* turn off interrupt prediction */ 446 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1); 447 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1); 448 449 /* turn on interrupts */ 450 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1); 451 452 /* set clocks etc */ 453 pci_write_config(dev, 0x5b, 454 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1); 455 break; 456 457 case 0x05711106: /* VIA 82C586, '596, '686 default setup */ 458 /* prepare for ATA-66 on the 82C686a and 82C596b */ 459 if ((ata_find_dev(dev, 0x06861106, 0x10) && 460 !ata_find_dev(dev, 0x06861106, 0x40)) || 461 ata_find_dev(dev, 0x05961106, 0x12)) 462 pci_write_config(dev, 0x50, 0x030b030b, 4); 463 464 /* the southbridge might need the data corruption fix */ 465 if (ata_find_dev(dev, 0x06861106, 0x40) || 466 ata_find_dev(dev, 0x82311106, 0x10)) 467 ata_via_southbridge_fixup(dev); 468 /* FALLTHROUGH */ 469 470 case 0x74091022: /* AMD 756 default setup */ 471 case 0x74111022: /* AMD 766 default setup */ 472 case 0x74411022: /* AMD 768 default setup */ 473 case 0x01bc10de: /* nVIDIA nForce default setup */ 474 /* set prefetch, postwrite */ 475 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1); 476 477 /* set fifo configuration half'n'half */ 478 pci_write_config(dev, 0x43, 479 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1); 480 481 /* set status register read retry */ 482 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1); 483 484 /* set DMA read & end-of-sector fifo flush */ 485 pci_write_config(dev, 0x46, 486 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1); 487 488 /* set sector size */ 489 pci_write_config(dev, 0x60, DEV_BSIZE, 2); 490 pci_write_config(dev, 0x68, DEV_BSIZE, 2); 491 break; 492 493 case 0x02111166: /* ServerWorks ROSB4 enable UDMA33 */ 494 pci_write_config(dev, 0x64, 495 (pci_read_config(dev, 0x64, 4) & ~0x00002000) | 496 0x00004000, 4); 497 break; 498 499 case 0x02121166: /* ServerWorks CSB5 enable UDMA66/100 depending on rev */ 500 pci_write_config(dev, 0x5a, 501 (pci_read_config(dev, 0x5a, 1) & ~0x40) | 502 (pci_get_revid(dev) >= 0x92) ? 0x03 : 0x02, 1); 503 break; 504 505 case 0x06461095: /* CMD 646 enable interrupts, set DMA read mode */ 506 pci_write_config(dev, 0x71, 0x01, 1); 507 break; 508 509 case 0x10001042: /* RZ 100? known bad, no DMA */ 510 case 0x10011042: 511 case 0x06401095: /* CMD 640 known bad, no DMA */ 512 controller->bmio = NULL; 513 device_printf(dev, "Busmastering DMA disabled\n"); 514 } 515 516 if (controller->bmio) { 517 controller->bmaddr = rman_get_start(controller->bmio); 518 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev, 519 SYS_RES_IOPORT, rid, controller->bmio); 520 controller->bmio = NULL; 521 } 522 523 /* 524 * the Cypress chip is a mess, it contains two ATA functions, but 525 * both channels are visible on the first one. 526 * simply ignore the second function for now, as the right 527 * solution (ignoring the second channel on the first function) 528 * doesn't work with the crappy ATA interrupt setup on the alpha. 529 */ 530 if (pci_get_devid(dev) == 0xc6931080 && pci_get_function(dev) > 1) 531 return 0; 532 533 ata_pci_add_child(dev, 0); 534 535 if (ATA_MASTERDEV(dev) || pci_read_config(dev, 0x18, 4) & IOMASK) 536 ata_pci_add_child(dev, 1); 537 538 return bus_generic_attach(dev); 539 } 540 541 static int 542 ata_pci_intr(struct ata_channel *ch) 543 { 544 u_int8_t dmastat; 545 546 /* 547 * since we might share the IRQ with another device, and in some 548 * cases with our twin channel, we only want to process interrupts 549 * that we know this channel generated. 550 */ 551 switch (ch->chiptype) { 552 case 0x00041103: /* HighPoint HPT366/368/370/372 */ 553 case 0x00051103: /* HighPoint HPT372 */ 554 case 0x00081103: /* HighPoint HPT374 */ 555 if (((dmastat = ata_dmastatus(ch)) & 556 (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) != ATA_BMSTAT_INTERRUPT) 557 return 1; 558 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT); 559 DELAY(1); 560 return 0; 561 562 case 0x06481095: /* CMD 648 */ 563 case 0x06491095: /* CMD 649 */ 564 if (!(pci_read_config(device_get_parent(ch->dev), 0x71, 1) & 565 (ch->unit ? 0x08 : 0x04))) 566 return 1; 567 break; 568 569 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */ 570 case 0x0d38105a: /* Promise Fasttrak 66 */ 571 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */ 572 case 0x0d30105a: /* Promise OEM ATA100 */ 573 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */ 574 if (!(ATA_INL(ch->r_bmio, (ch->unit ? 0x14 : 0x1c)) & 575 (ch->unit ? 0x00004000 : 0x00000400))) 576 return 1; 577 break; 578 579 case 0x4d68105a: /* Promise TX2 ATA100 */ 580 case 0x6268105a: /* Promise TX2 ATA100 */ 581 case 0x4d69105a: /* Promise TX2 ATA133 */ 582 case 0x5275105a: /* Promise TX2 ATA133 */ 583 case 0x6269105a: /* Promise TX2 ATA133 */ 584 ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b); 585 if (!(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x20)) 586 return 1; 587 break; 588 } 589 590 if (ch->flags & ATA_DMA_ACTIVE) { 591 if (!((dmastat = ata_dmastatus(ch)) & ATA_BMSTAT_INTERRUPT)) 592 return 1; 593 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT); 594 DELAY(1); 595 } 596 return 0; 597 } 598 599 static int 600 ata_pci_print_child(device_t dev, device_t child) 601 { 602 struct ata_channel *ch = device_get_softc(child); 603 int retval = 0; 604 605 retval += bus_print_child_header(dev, child); 606 retval += printf(": at 0x%lx", rman_get_start(ch->r_io)); 607 608 if (ATA_MASTERDEV(dev)) 609 retval += printf(" irq %d", 14 + ch->unit); 610 611 retval += bus_print_child_footer(dev, child); 612 613 return retval; 614 } 615 616 static struct resource * 617 ata_pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 618 u_long start, u_long end, u_long count, u_int flags) 619 { 620 struct ata_pci_controller *controller = device_get_softc(dev); 621 struct resource *res = NULL; 622 int unit = ((struct ata_channel *)device_get_softc(child))->unit; 623 int myrid; 624 625 if (type == SYS_RES_IOPORT) { 626 switch (*rid) { 627 case ATA_IOADDR_RID: 628 if (ATA_MASTERDEV(dev)) { 629 myrid = 0; 630 start = (unit ? ATA_SECONDARY : ATA_PRIMARY); 631 end = start + ATA_IOSIZE - 1; 632 count = ATA_IOSIZE; 633 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 634 SYS_RES_IOPORT, &myrid, 635 start, end, count, flags); 636 } 637 else { 638 myrid = 0x10 + 8 * unit; 639 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev, 640 SYS_RES_IOPORT, &myrid, 641 start, end, count, flags); 642 } 643 break; 644 645 case ATA_ALTADDR_RID: 646 if (ATA_MASTERDEV(dev)) { 647 myrid = 0; 648 start = (unit ? ATA_SECONDARY : ATA_PRIMARY) + ATA_ALTOFFSET; 649 end = start + ATA_ALTIOSIZE - 1; 650 count = ATA_ALTIOSIZE; 651 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 652 SYS_RES_IOPORT, &myrid, 653 start, end, count, flags); 654 } 655 else { 656 myrid = 0x14 + 8 * unit; 657 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev, 658 SYS_RES_IOPORT, &myrid, 659 start, end, count, flags); 660 if (res) { 661 start = rman_get_start(res) + 2; 662 end = start + ATA_ALTIOSIZE - 1; 663 count = ATA_ALTIOSIZE; 664 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev, 665 SYS_RES_IOPORT, myrid, res); 666 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev, 667 SYS_RES_IOPORT, &myrid, 668 start, end, count, flags); 669 } 670 } 671 break; 672 673 case ATA_BMADDR_RID: 674 if (controller->bmaddr) { 675 myrid = 0x20; 676 start = (unit == 0 ? 677 controller->bmaddr : controller->bmaddr+ATA_BMIOSIZE); 678 end = start + ATA_BMIOSIZE - 1; 679 count = ATA_BMIOSIZE; 680 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 681 SYS_RES_IOPORT, &myrid, 682 start, end, count, flags); 683 } 684 } 685 return res; 686 } 687 688 if (type == SYS_RES_IRQ && *rid == ATA_IRQ_RID) { 689 if (ATA_MASTERDEV(dev)) { 690 #ifdef __alpha__ 691 return alpha_platform_alloc_ide_intr(unit); 692 #else 693 int irq = (unit == 0 ? 14 : 15); 694 695 return BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 696 SYS_RES_IRQ, rid, irq, irq, 1, flags); 697 #endif 698 } 699 else { 700 /* primary and secondary channels share interrupt, keep track */ 701 if (!controller->irq) 702 controller->irq = BUS_ALLOC_RESOURCE(device_get_parent(dev), 703 dev, SYS_RES_IRQ, 704 rid, 0, ~0, 1, flags); 705 controller->irqcnt++; 706 return controller->irq; 707 } 708 } 709 return 0; 710 } 711 712 static int 713 ata_pci_release_resource(device_t dev, device_t child, int type, int rid, 714 struct resource *r) 715 { 716 struct ata_pci_controller *controller = device_get_softc(dev); 717 int unit = ((struct ata_channel *)device_get_softc(child))->unit; 718 719 if (type == SYS_RES_IOPORT) { 720 switch (rid) { 721 case ATA_IOADDR_RID: 722 if (ATA_MASTERDEV(dev)) 723 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 724 SYS_RES_IOPORT, 0x0, r); 725 else 726 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev, 727 SYS_RES_IOPORT, 0x10 + 8 * unit, r); 728 break; 729 730 case ATA_ALTADDR_RID: 731 if (ATA_MASTERDEV(dev)) 732 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 733 SYS_RES_IOPORT, 0x0, r); 734 else 735 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev, 736 SYS_RES_IOPORT, 0x14 + 8 * unit, r); 737 break; 738 739 case ATA_BMADDR_RID: 740 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 741 SYS_RES_IOPORT, 0x20, r); 742 default: 743 return ENOENT; 744 } 745 } 746 if (type == SYS_RES_IRQ) { 747 if (rid != ATA_IRQ_RID) 748 return ENOENT; 749 750 if (ATA_MASTERDEV(dev)) { 751 #ifdef __alpha__ 752 return alpha_platform_release_ide_intr(unit, r); 753 #else 754 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 755 SYS_RES_IRQ, rid, r); 756 #endif 757 } 758 else { 759 /* primary and secondary channels share interrupt, keep track */ 760 if (--controller->irqcnt) 761 return 0; 762 controller->irq = NULL; 763 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev, 764 SYS_RES_IRQ, rid, r); 765 } 766 } 767 return EINVAL; 768 } 769 770 static int 771 ata_pci_setup_intr(device_t dev, device_t child, struct resource *irq, 772 int flags, driver_intr_t *intr, void *arg, 773 void **cookiep) 774 { 775 if (ATA_MASTERDEV(dev)) { 776 #ifdef __alpha__ 777 return alpha_platform_setup_ide_intr(child, irq, intr, arg, cookiep); 778 #else 779 return BUS_SETUP_INTR(device_get_parent(dev), child, irq, 780 flags, intr, arg, cookiep); 781 #endif 782 } 783 else 784 return BUS_SETUP_INTR(device_get_parent(dev), dev, irq, 785 flags, intr, arg, cookiep); 786 } 787 788 static int 789 ata_pci_teardown_intr(device_t dev, device_t child, struct resource *irq, 790 void *cookie) 791 { 792 if (ATA_MASTERDEV(dev)) { 793 #ifdef __alpha__ 794 return alpha_platform_teardown_ide_intr(child, irq, cookie); 795 #else 796 return BUS_TEARDOWN_INTR(device_get_parent(dev), child, irq, cookie); 797 #endif 798 } 799 else 800 return BUS_TEARDOWN_INTR(device_get_parent(dev), dev, irq, cookie); 801 } 802 803 static device_method_t ata_pci_methods[] = { 804 /* device interface */ 805 DEVMETHOD(device_probe, ata_pci_probe), 806 DEVMETHOD(device_attach, ata_pci_attach), 807 DEVMETHOD(device_shutdown, bus_generic_shutdown), 808 DEVMETHOD(device_suspend, bus_generic_suspend), 809 DEVMETHOD(device_resume, bus_generic_resume), 810 811 /* bus methods */ 812 DEVMETHOD(bus_print_child, ata_pci_print_child), 813 DEVMETHOD(bus_alloc_resource, ata_pci_alloc_resource), 814 DEVMETHOD(bus_release_resource, ata_pci_release_resource), 815 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 816 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 817 DEVMETHOD(bus_setup_intr, ata_pci_setup_intr), 818 DEVMETHOD(bus_teardown_intr, ata_pci_teardown_intr), 819 { 0, 0 } 820 }; 821 822 static driver_t ata_pci_driver = { 823 "atapci", 824 ata_pci_methods, 825 sizeof(struct ata_pci_controller), 826 }; 827 828 static devclass_t ata_pci_devclass; 829 830 DRIVER_MODULE(atapci, pci, ata_pci_driver, ata_pci_devclass, 0, 0); 831 832 static int 833 ata_pcisub_probe(device_t dev) 834 { 835 struct ata_channel *ch = device_get_softc(dev); 836 device_t *children; 837 int count, i; 838 839 /* find channel number on this controller */ 840 device_get_children(device_get_parent(dev), &children, &count); 841 for (i = 0; i < count; i++) { 842 if (children[i] == dev) 843 ch->unit = i; 844 } 845 free(children, M_TEMP); 846 ch->chiptype = pci_get_devid(device_get_parent(dev)); 847 ch->intr_func = ata_pci_intr; 848 return ata_probe(dev); 849 } 850 851 static device_method_t ata_pcisub_methods[] = { 852 /* device interface */ 853 DEVMETHOD(device_probe, ata_pcisub_probe), 854 DEVMETHOD(device_attach, ata_attach), 855 DEVMETHOD(device_detach, ata_detach), 856 DEVMETHOD(device_resume, ata_resume), 857 { 0, 0 } 858 }; 859 860 static driver_t ata_pcisub_driver = { 861 "ata", 862 ata_pcisub_methods, 863 sizeof(struct ata_channel), 864 }; 865 866 DRIVER_MODULE(ata, atapci, ata_pcisub_driver, ata_devclass, 0, 0); 867