1 /*- 2 * Copyright (c) 1998,1999,2000,2001 S�ren Schmidt 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/disk.h> 35 #include <sys/module.h> 36 #include <sys/bus.h> 37 #include <sys/bio.h> 38 #include <sys/malloc.h> 39 #include <sys/devicestat.h> 40 #include <sys/sysctl.h> 41 #include <machine/stdarg.h> 42 #include <machine/resource.h> 43 #include <machine/bus.h> 44 #ifdef __alpha__ 45 #include <machine/md_var.h> 46 #endif 47 #include <sys/rman.h> 48 #include <pci/pcivar.h> 49 #include <pci/pcireg.h> 50 #include <dev/ata/ata-all.h> 51 52 /* misc defines */ 53 #define IOMASK 0xfffffffc 54 #define ATA_MASTERDEV(dev) ((pci_get_progif(dev) & 0x80) && \ 55 (pci_get_progif(dev) & 0x05) != 0x05) 56 57 struct ata_pci_softc { 58 struct resource *bmio; 59 int bmaddr; 60 struct resource *irq; 61 int irqcnt; 62 }; 63 64 int 65 ata_find_dev(device_t dev, u_int32_t type, u_int32_t revid) 66 { 67 device_t *children, child; 68 int nchildren, i; 69 70 if (device_get_children(device_get_parent(dev), &children, &nchildren)) 71 return 0; 72 73 for (i = 0; i < nchildren; i++) { 74 child = children[i]; 75 76 /* check that it's on the same silicon and the device we want */ 77 if (pci_get_slot(dev) == pci_get_slot(child) && 78 pci_get_vendor(child) == (type & 0xffff) && 79 pci_get_device(child) == ((type & 0xffff0000) >> 16) && 80 pci_get_revid(child) >= revid) { 81 free(children, M_TEMP); 82 return 1; 83 } 84 } 85 free(children, M_TEMP); 86 return 0; 87 } 88 89 static const char * 90 ata_pci_match(device_t dev) 91 { 92 if (pci_get_class(dev) != PCIC_STORAGE) 93 return NULL; 94 95 switch (pci_get_devid(dev)) { 96 /* supported chipsets */ 97 case 0x12308086: 98 return "Intel PIIX ATA controller"; 99 100 case 0x70108086: 101 return "Intel PIIX3 ATA controller"; 102 103 case 0x71118086: 104 case 0x71998086: 105 return "Intel PIIX4 ATA33 controller"; 106 107 case 0x24218086: 108 return "Intel ICH0 ATA33 controller"; 109 110 case 0x24118086: 111 return "Intel ICH ATA66 controller"; 112 113 case 0x244a8086: 114 case 0x244b8086: 115 return "Intel ICH2 ATA100 controller"; 116 117 case 0x522910b9: 118 if (pci_get_revid(dev) < 0x20) 119 return "AcerLabs Aladdin ATA controller"; 120 else 121 return "AcerLabs Aladdin ATA33 controller"; 122 123 case 0x05711106: 124 if (ata_find_dev(dev, 0x05861106, 0x02)) 125 return "VIA 82C586 ATA33 controller"; 126 if (ata_find_dev(dev, 0x05861106, 0)) 127 return "VIA 82C586 ATA controller"; 128 if (ata_find_dev(dev, 0x05961106, 0x12)) 129 return "VIA 82C596 ATA66 controller"; 130 if (ata_find_dev(dev, 0x05961106, 0)) 131 return "VIA 82C596 ATA33 controller"; 132 if (ata_find_dev(dev, 0x06861106, 0x40) || 133 ata_find_dev(dev, 0x30741106, 0)) 134 return "VIA 82C686 ATA100 controller"; 135 if (ata_find_dev(dev, 0x06861106, 0)) 136 return "VIA 82C686 ATA66 controller"; 137 return "VIA Apollo ATA controller"; 138 139 case 0x55131039: 140 return "SiS 5591 ATA33 controller"; 141 142 case 0x06491095: 143 return "CMD 649 ATA100 controller"; 144 145 case 0x06481095: 146 return "CMD 648 ATA66 controller"; 147 148 case 0x06461095: 149 return "CMD 646 ATA controller"; 150 151 case 0xc6931080: 152 if (pci_get_subclass(dev) == PCIS_STORAGE_IDE) 153 return "Cypress 82C693 ATA controller"; 154 break; 155 156 case 0x01021078: 157 return "Cyrix 5530 ATA33 controller"; 158 159 case 0x74091022: 160 return "AMD 756 ATA66 controller"; 161 162 case 0x74111022: 163 return "AMD 766 ATA100 controller"; 164 165 case 0x02111166: 166 return "ServerWorks ROSB4 ATA33 controller"; 167 168 case 0x4d33105a: 169 return "Promise ATA33 controller"; 170 171 case 0x4d38105a: 172 return "Promise ATA66 controller"; 173 174 case 0x0d30105a: 175 case 0x4d30105a: 176 return "Promise ATA100 controller"; 177 178 case 0x4d68105a: 179 case 0x6268105a: 180 return "Promise TX2 ATA100 controller"; 181 182 case 0x00041103: 183 switch (pci_get_revid(dev)) { 184 case 0x00: 185 case 0x01: 186 return "HighPoint HPT366 ATA66 controller"; 187 case 0x02: 188 return "HighPoint HPT368 ATA66 controller"; 189 case 0x03: 190 case 0x04: 191 return "HighPoint HPT370 ATA100 controller"; 192 default: 193 return "Unknown revision HighPoint ATA controller"; 194 } 195 196 /* unsupported but known chipsets, generic DMA only */ 197 case 0x10001042: 198 case 0x10011042: 199 return "RZ 100? ATA controller !WARNING! buggy chip data loss possible"; 200 201 case 0x06401095: 202 return "CMD 640 ATA controller !WARNING! buggy chip data loss possible"; 203 204 /* unknown chipsets, try generic DMA if it seems possible */ 205 default: 206 if (pci_get_class(dev) == PCIC_STORAGE && 207 (pci_get_subclass(dev) == PCIS_STORAGE_IDE)) 208 return "Generic PCI ATA controller"; 209 } 210 return NULL; 211 } 212 213 static int 214 ata_pci_probe(device_t dev) 215 { 216 const char *desc = ata_pci_match(dev); 217 218 if (desc) { 219 device_set_desc(dev, desc); 220 return 0; 221 } 222 else 223 return ENXIO; 224 } 225 226 static int 227 ata_pci_add_child(device_t dev, int unit) 228 { 229 device_t child; 230 231 /* check if this is located at one of the std addresses */ 232 if (ATA_MASTERDEV(dev)) { 233 if (!(child = device_add_child(dev, "ata", unit))) 234 return ENOMEM; 235 } 236 else { 237 if (!(child = device_add_child(dev, "ata", 2))) 238 return ENOMEM; 239 } 240 return 0; 241 } 242 243 static int 244 ata_pci_attach(device_t dev) 245 { 246 struct ata_pci_softc *sc = device_get_softc(dev); 247 u_int8_t class, subclass; 248 u_int32_t type, cmd; 249 int rid; 250 251 /* set up vendor-specific stuff */ 252 type = pci_get_devid(dev); 253 class = pci_get_class(dev); 254 subclass = pci_get_subclass(dev); 255 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 256 257 if (!(cmd & PCIM_CMD_PORTEN)) { 258 device_printf(dev, "ATA channel disabled by BIOS\n"); 259 return 0; 260 } 261 262 /* is busmastering supported ? */ 263 if ((cmd & (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) == 264 (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) { 265 266 /* is there a valid port range to connect to ? */ 267 rid = 0x20; 268 sc->bmio = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 269 0, ~0, 1, RF_ACTIVE); 270 if (!sc->bmio) 271 device_printf(dev, "Busmastering DMA not configured\n"); 272 } 273 else 274 device_printf(dev, "Busmastering DMA not supported\n"); 275 276 /* do extra chipset specific setups */ 277 switch (type) { 278 case 0x522910b9: /* Aladdin need to activate the ATAPI FIFO */ 279 pci_write_config(dev, 0x53, 280 (pci_read_config(dev, 0x53, 1) & ~0x01) | 0x02, 1); 281 break; 282 283 case 0x4d38105a: /* Promise 66 & 100 (before TX2) need the clock changed */ 284 case 0x4d30105a: 285 case 0x0d30105a: 286 ATA_OUTB(sc->bmio, 0x11, ATA_INB(sc->bmio, 0x11) | 0x0a); 287 /* FALLTHROUGH */ 288 289 case 0x4d33105a: /* Promise (before TX2) need burst mode turned on */ 290 ATA_OUTB(sc->bmio, 0x1f, ATA_INB(sc->bmio, 0x1f) | 0x01); 291 break; 292 293 case 0x00041103: /* HighPoint */ 294 switch (pci_get_revid(dev)) { 295 case 0x00: 296 case 0x01: 297 /* turn off interrupt prediction */ 298 pci_write_config(dev, 0x51, 299 (pci_read_config(dev, 0x51, 1) & ~0x80), 1); 300 break; 301 302 case 0x02: 303 case 0x03: 304 case 0x04: 305 /* turn off interrupt prediction */ 306 pci_write_config(dev, 0x51, 307 (pci_read_config(dev, 0x51, 1) & ~0x02), 1); 308 pci_write_config(dev, 0x55, 309 (pci_read_config(dev, 0x55, 1) & ~0x02), 1); 310 /* turn on interrupts */ 311 pci_write_config(dev, 0x5a, 312 (pci_read_config(dev, 0x5a, 1) & ~0x10), 1); 313 314 } 315 break; 316 317 case 0x05711106: 318 case 0x74091022: 319 case 0x74111022: /* VIA 82C586, '596, '686 & AMD 756, '766 default setup */ 320 321 /* set prefetch, postwrite */ 322 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1); 323 324 /* set fifo configuration half'n'half */ 325 pci_write_config(dev, 0x43, 326 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1); 327 328 /* set status register read retry */ 329 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1); 330 331 /* set DMA read & end-of-sector fifo flush */ 332 pci_write_config(dev, 0x46, 333 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1); 334 335 /* set sector size */ 336 pci_write_config(dev, 0x60, DEV_BSIZE, 2); 337 pci_write_config(dev, 0x68, DEV_BSIZE, 2); 338 339 /* prepare for ATA-66 on the 82C686a and rev 0x12 and newer 82C596's */ 340 if ((ata_find_dev(dev, 0x06861106, 0) && 341 !ata_find_dev(dev, 0x06861106, 0x40)) || 342 ata_find_dev(dev, 0x05961106, 0x12)) 343 pci_write_config(dev, 0x50, 0x030b030b, 4); 344 break; 345 346 case 0x10001042: /* RZ 100? known bad, no DMA */ 347 case 0x10011042: 348 case 0x06401095: /* CMD 640 known bad, no DMA */ 349 sc->bmio = NULL; 350 device_printf(dev, "Busmastering DMA disabled\n"); 351 } 352 353 if (sc->bmio) { 354 sc->bmaddr = rman_get_start(sc->bmio); 355 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev, 356 SYS_RES_IOPORT, rid, sc->bmio); 357 sc->bmio = NULL; 358 } 359 360 /* 361 * the Cypress chip is a mess, it contains two ATA functions, but 362 * both channels are visible on the first one. 363 * simply ignore the second function for now, as the right 364 * solution (ignoring the second channel on the first function) 365 * doesn't work with the crappy ATA interrupt setup on the alpha. 366 */ 367 if (pci_get_devid(dev) == 0xc6931080 && pci_get_function(dev) > 1) 368 return 0; 369 370 ata_pci_add_child(dev, 0); 371 372 if (ATA_MASTERDEV(dev) || pci_read_config(dev, 0x18, 4) & IOMASK) 373 ata_pci_add_child(dev, 1); 374 375 return bus_generic_attach(dev); 376 } 377 378 static int 379 ata_pci_intr(struct ata_softc *scp) 380 { 381 u_int8_t dmastat; 382 383 /* 384 * since we might share the IRQ with another device, and in some 385 * cases with our twin channel, we only want to process interrupts 386 * that we know this channel generated. 387 */ 388 switch (scp->chiptype) { 389 case 0x00041103: /* HighPoint HPT366/368/370 */ 390 if (((dmastat = ata_dmastatus(scp)) & 391 (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) != ATA_BMSTAT_INTERRUPT) 392 return 1; 393 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT); 394 DELAY(1); 395 return 0; 396 397 case 0x06481095: /* CMD 648 */ 398 case 0x06491095: /* CMD 649 */ 399 if (!(pci_read_config(device_get_parent(scp->dev), 0x71, 1) & 400 (scp->channel ? 0x08 : 0x04))) 401 return 1; 402 break; 403 404 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */ 405 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */ 406 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */ 407 case 0x0d30105a: /* Promise OEM ATA100 */ 408 case 0x4d68105a: /* Promise TX2 ATA100 */ 409 case 0x6268105a: /* Promise TX2v2 ATA100 */ 410 if (!(ATA_INL(scp->r_bmio, (scp->channel ? 0x14 : 0x1c)) & 411 (scp->channel ? 0x00004000 : 0x00000400))) 412 return 1; 413 break; 414 } 415 416 if (scp->flags & ATA_DMA_ACTIVE) { 417 if (!((dmastat = ata_dmastatus(scp)) & ATA_BMSTAT_INTERRUPT)) 418 return 1; 419 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT); 420 DELAY(1); 421 } 422 return 0; 423 } 424 425 static int 426 ata_pci_print_child(device_t dev, device_t child) 427 { 428 struct ata_softc *scp = device_get_softc(child); 429 int retval = 0; 430 431 retval += bus_print_child_header(dev, child); 432 retval += printf(": at 0x%lx", rman_get_start(scp->r_io)); 433 434 if (ATA_MASTERDEV(dev)) 435 retval += printf(" irq %d", 14 + scp->channel); 436 437 retval += bus_print_child_footer(dev, child); 438 439 return retval; 440 } 441 442 static struct resource * 443 ata_pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 444 u_long start, u_long end, u_long count, u_int flags) 445 { 446 struct ata_pci_softc *sc = device_get_softc(dev); 447 struct resource *res = NULL; 448 int channel = ((struct ata_softc *)device_get_softc(child))->channel; 449 int myrid; 450 451 if (type == SYS_RES_IOPORT) { 452 switch (*rid) { 453 case ATA_IOADDR_RID: 454 if (ATA_MASTERDEV(dev)) { 455 myrid = 0; 456 start = (channel ? ATA_SECONDARY : ATA_PRIMARY); 457 end = start + ATA_IOSIZE - 1; 458 count = ATA_IOSIZE; 459 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 460 SYS_RES_IOPORT, &myrid, 461 start, end, count, flags); 462 } 463 else { 464 myrid = 0x10 + 8 * channel; 465 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev, 466 SYS_RES_IOPORT, &myrid, 467 start, end, count, flags); 468 } 469 break; 470 471 case ATA_ALTADDR_RID: 472 if (ATA_MASTERDEV(dev)) { 473 myrid = 0; 474 start = (channel ? ATA_SECONDARY : ATA_PRIMARY) + ATA_ALTOFFSET; 475 end = start + ATA_ALTIOSIZE - 1; 476 count = ATA_ALTIOSIZE; 477 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 478 SYS_RES_IOPORT, &myrid, 479 start, end, count, flags); 480 } 481 else { 482 myrid = 0x14 + 8 * channel; 483 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev, 484 SYS_RES_IOPORT, &myrid, 485 start, end, count, flags); 486 if (res) { 487 start = rman_get_start(res) + 2; 488 end = rman_get_start(res) + ATA_ALTIOSIZE - 1; 489 count = ATA_ALTIOSIZE; 490 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev, 491 SYS_RES_IOPORT, myrid, res); 492 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev, 493 SYS_RES_IOPORT, &myrid, 494 start, end, count, flags); 495 } 496 } 497 break; 498 499 case ATA_BMADDR_RID: 500 if (sc->bmaddr) { 501 myrid = 0x20; 502 start = (channel == 0 ? sc->bmaddr : sc->bmaddr + ATA_BMIOSIZE); 503 end = start + ATA_BMIOSIZE - 1; 504 count = ATA_BMIOSIZE; 505 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 506 SYS_RES_IOPORT, &myrid, 507 start, end, count, flags); 508 } 509 } 510 return res; 511 } 512 513 if (type == SYS_RES_IRQ && *rid == ATA_IRQ_RID) { 514 if (ATA_MASTERDEV(dev)) { 515 #ifdef __alpha__ 516 return alpha_platform_alloc_ide_intr(channel); 517 #else 518 int irq = (channel == 0 ? 14 : 15); 519 520 return BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 521 SYS_RES_IRQ, rid, irq, irq, 1, flags); 522 #endif 523 } 524 else { 525 /* primary and secondary channels share interrupt, keep track */ 526 if (!sc->irq) 527 sc->irq = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev, 528 SYS_RES_IRQ, rid, 0, ~0, 1, flags); 529 sc->irqcnt++; 530 return sc->irq; 531 } 532 } 533 return 0; 534 } 535 536 static int 537 ata_pci_release_resource(device_t dev, device_t child, int type, int rid, 538 struct resource *r) 539 { 540 struct ata_pci_softc *sc = device_get_softc(dev); 541 int channel = ((struct ata_softc *)device_get_softc(child))->channel; 542 543 if (type == SYS_RES_IOPORT) { 544 switch (rid) { 545 case ATA_IOADDR_RID: 546 if (ATA_MASTERDEV(dev)) 547 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 548 SYS_RES_IOPORT, 0x0, r); 549 else 550 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev, 551 SYS_RES_IOPORT, 0x10+8*channel, r); 552 break; 553 554 case ATA_ALTADDR_RID: 555 if (ATA_MASTERDEV(dev)) 556 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 557 SYS_RES_IOPORT, 0x0, r); 558 else 559 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev, 560 SYS_RES_IOPORT, 0x14+8*channel, r); 561 break; 562 563 case ATA_BMADDR_RID: 564 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 565 SYS_RES_IOPORT, 0x20, r); 566 default: 567 return ENOENT; 568 } 569 } 570 if (type == SYS_RES_IRQ) { 571 if (rid != ATA_IRQ_RID) 572 return ENOENT; 573 574 if (ATA_MASTERDEV(dev)) { 575 #ifdef __alpha__ 576 return alpha_platform_release_ide_intr(channel, r); 577 #else 578 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 579 SYS_RES_IRQ, rid, r); 580 #endif 581 } 582 else { 583 /* primary and secondary channels share interrupt, keep track */ 584 if (--sc->irqcnt) 585 return 0; 586 sc->irq = 0; 587 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev, 588 SYS_RES_IRQ, rid, r); 589 } 590 } 591 return EINVAL; 592 } 593 594 static int 595 ata_pci_setup_intr(device_t dev, device_t child, struct resource *irq, 596 int flags, driver_intr_t *intr, void *arg, 597 void **cookiep) 598 { 599 if (ATA_MASTERDEV(dev)) { 600 #ifdef __alpha__ 601 return alpha_platform_setup_ide_intr(child, irq, intr, arg, cookiep); 602 #else 603 return BUS_SETUP_INTR(device_get_parent(dev), child, irq, 604 flags, intr, arg, cookiep); 605 #endif 606 } 607 else 608 return BUS_SETUP_INTR(device_get_parent(dev), dev, irq, 609 flags, intr, arg, cookiep); 610 } 611 612 static int 613 ata_pci_teardown_intr(device_t dev, device_t child, struct resource *irq, 614 void *cookie) 615 { 616 if (ATA_MASTERDEV(dev)) { 617 #ifdef __alpha__ 618 return alpha_platform_teardown_ide_intr(child, irq, cookie); 619 #else 620 return BUS_TEARDOWN_INTR(device_get_parent(dev), child, irq, cookie); 621 #endif 622 } 623 else 624 return BUS_TEARDOWN_INTR(device_get_parent(dev), dev, irq, cookie); 625 } 626 627 static device_method_t ata_pci_methods[] = { 628 /* device interface */ 629 DEVMETHOD(device_probe, ata_pci_probe), 630 DEVMETHOD(device_attach, ata_pci_attach), 631 DEVMETHOD(device_shutdown, bus_generic_shutdown), 632 DEVMETHOD(device_suspend, bus_generic_suspend), 633 DEVMETHOD(device_resume, bus_generic_resume), 634 635 /* bus methods */ 636 DEVMETHOD(bus_print_child, ata_pci_print_child), 637 DEVMETHOD(bus_alloc_resource, ata_pci_alloc_resource), 638 DEVMETHOD(bus_release_resource, ata_pci_release_resource), 639 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 640 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 641 DEVMETHOD(bus_setup_intr, ata_pci_setup_intr), 642 DEVMETHOD(bus_teardown_intr, ata_pci_teardown_intr), 643 { 0, 0 } 644 }; 645 646 static driver_t ata_pci_driver = { 647 "atapci", 648 ata_pci_methods, 649 sizeof(struct ata_pci_softc), 650 }; 651 652 static devclass_t ata_pci_devclass; 653 654 DRIVER_MODULE(atapci, pci, ata_pci_driver, ata_pci_devclass, 0, 0); 655 656 static int 657 ata_pcisub_probe(device_t dev) 658 { 659 struct ata_softc *scp = device_get_softc(dev); 660 device_t *children; 661 int count, i; 662 663 /* find channel number on this controller */ 664 device_get_children(device_get_parent(dev), &children, &count); 665 for (i = 0; i < count; i++) { 666 if (children[i] == dev) 667 scp->channel = i; 668 } 669 free(children, M_TEMP); 670 scp->chiptype = pci_get_devid(device_get_parent(dev)); 671 scp->intr_func = ata_pci_intr; 672 return ata_probe(dev); 673 } 674 675 static device_method_t ata_pcisub_methods[] = { 676 /* device interface */ 677 DEVMETHOD(device_probe, ata_pcisub_probe), 678 DEVMETHOD(device_attach, ata_attach), 679 DEVMETHOD(device_detach, ata_detach), 680 DEVMETHOD(device_resume, ata_resume), 681 { 0, 0 } 682 }; 683 684 static driver_t ata_pcisub_driver = { 685 "ata", 686 ata_pcisub_methods, 687 sizeof(struct ata_softc), 688 }; 689 690 DRIVER_MODULE(ata, atapci, ata_pcisub_driver, ata_devclass, 0, 0); 691